FPGA Architrecture

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FPGA Architecture FPGA Architecture By Suresh Balpande Browse:- www.sbalpande.webs.com

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Transcript of FPGA Architrecture

  • FPGA ArchitectureFPGA Architecture

    By Suresh Balpande Browse:- www.sbalpande.webs.com

  • FPGA A Detailed Look Based on the principle of functional completeness FPGA: Functionally complete elements (Logic

    Blocks) placed in an interconnect frameworkInterconnection framework comprises of wire Interconnection framework comprises of wire segments and switches; Provide a means to interconnect logic blocks

    Circuits are partitioned to logic block size, mapped and routed

    By Suresh Balpande Browse:- www.sbalpande.webs.com

  • A Fictitious FPGA Architecture(With Multiplexer As Functionally Complete Cell)

    Basic building block

    By Suresh Balpande Browse:- www.sbalpande.webs.com

  • Interconnection Framework

    FPGA Fine grained Fine grained Variable length

    interconnect segments Timing in general is not

    predictable; Timing extracted after placement and route

    By Suresh Balpande Browse:- www.sbalpande.webs.com

  • Field Programmability Field programmability is achieved through

    switches (Transistors controlled by memory elements or fuses)

    Switches control the following aspects Switches control the following aspects Interconnection among wire segments Configuration of logic blocks

    Distributed memory elements controlling the switches and configuration of logic blocks are together called Configuration Memory

    By Suresh Balpande Browse:- www.sbalpande.webs.com

  • SRAM Programming Technology Employs SRAM (Static RAM) cells

    to control pass transistors and/or transmission gates

    SRAM cells control the configuration of logic block as wellconfiguration of logic block as well

    Volatile Needs an external storage Needs a power-on configuration

    mechanism In-circuit re-programmable

    Lesser configuration time Occupies relatively larger area

    By Suresh Balpande Browse:- www.sbalpande.webs.com

  • Anti-fuse ProgrammingTechnology

    Though implementation differ, all anti-fuse programming elements share common property Uses materials which normally resides in high impedance

    state But can be fused irreversibly into low impedance state by

    applying high voltage

    By Suresh Balpande Browse:- www.sbalpande.webs.com

  • Anti-fuse Programming Technology Very low ON Resistance (Faster implementation of

    circuits) Limited size of anti-fuse elements; Interconnects

    occupy relatively lesser areaoccupy relatively lesser area Offset : Larger transistors needed for programming

    One Time Programmable Cannot be re-programmed

    (Design changes are not possible)

    Retain configuration after power off

    By Suresh Balpande Browse:- www.sbalpande.webs.com

  • EPROM, EEPROM or Flash BasedProgramming Technology

    EPROM Programming Technology Two gates: Floating and Select Normal mode:

    No charge on floating gate Transistor behaves as normal n-channel transistor

    Floating gate charged by applying high voltage Threshold of transistor (as seen by gate) increases Transistor turned off permanently

    Re-programmable by exposing to UV radiationBy Suresh Balpande Browse:- www.sbalpande.webs.com

  • EPROM Programming Technology

    Used as pull-down devices

    Consumes static powerpower

    By Suresh Balpande Browse:- www.sbalpande.webs.com

  • An Example Modulo-4 counter:

    Specification Modulo-4 counter: Logic

    Implementation

    By Suresh Balpande Browse:- www.sbalpande.webs.com

  • FPGA Implementation ofModulo-4 Counter

    By Suresh Balpande Browse:- www.sbalpande.webs.com

  • Xilinx FPGAs Symmetric Array based; Array

    consists of CLBs with LUTs and D-Flipflops

    N-input LUTs can implement any n-input boolean function

    Generic Xilinx Architecture

    Array embedded within the periphery of IO blocks

    Array elements interleaved with routing resources (wire segments, switch matrix and single connection points)

    Employs SRAM technologyBy Suresh Balpande Browse:- www.sbalpande.webs.com

  • FPGA XC 4000

    XC4000 CLB 3 LUTs and 2 Flip-flops in a

    two stage arrangement

    2 Outputs: Can be registered or combinational

    External signals can also be External signals can also be registered

    More of internal signals are available for connections

    Can implement any two independent functions of four variables or any single function of five variables

    By Suresh Balpande Browse:- www.sbalpande.webs.com

  • ALTERA CPLDS Hierarchical PLD structure

    First level: LABs (Functional blocks); LAB is similar to SPLDs

    Second Level: Interconnections among LABs

    LAB consists of

    Altera generic architecture

    LAB consists of Product term array Product term distribution Macro-cells Expander product terms

    Interconnection region: PIA EPROM/EEPROM based Example: MAX5K, MAX7K

    By Suresh Balpande Browse:- www.sbalpande.webs.com

  • MAX 5000 MAX5K Macrocell

    Three wide AND gate feed an OR gate (Sum of products) XOR gate may be used in arithmetic operations or in polarity selection One flipflop per macrocell; Outputs may be registered Flipflop preset and clear are via product terms; Clock may be either

    system clock or internally generated Output may be driven out or fedback Feedback is both local and global; Local feedback is within macrocell and

    is quickerBy Suresh Balpande Browse:- www.sbalpande.webs.com

    Interconnection Framework

    FPGAFine grainedVariable length interconnect segmentsTiming in general is not predictable; Timing extracted after placement and route

    SRAM Programming Technology

    Employs SRAM (Static RAM) cells to control pass transistors and/or transmission gatesSRAM cells control the configuration of logic block as wellVolatileNeeds an external storageNeeds a power-on configuration mechanismIn-circuit re-programmableLesser configuration timeOccupies relatively larger area

    Anti-fuse Programming Technology

    Though implementation differ, all anti-fuse programming elements share common propertyUses materials which normally resides in high impedance stateBut can be fused irreversibly into low impedance state by applying high voltage

    Field Programmability

    Field programmability is achieved through switches (Transistors controlled by memory elements or fuses)Switches control the following aspectsInterconnection among wire segmentsConfiguration of logic blocksDistributed memory elements controlling the switches and configuration of logic blocks are together called Configuration Memory

    Anti-fuse Programming Technology

    Very low ON Resistance (Faster implementation of circuits)Limited size of anti-fuse elements; Interconnects occupy relatively lesser areaOffset : Larger transistors needed for programmingOne Time ProgrammableCannot be re-programmed (Design changes are not possible)Retain configuration after power off

    EPROM, EEPROM or Flash Based Programming Technology

    EPROM Programming TechnologyTwo gates: Floating and SelectNormal mode: No charge on floating gateTransistor behaves as normal n-channel transistorFloating gate charged by applying high voltageThreshold of transistor (as seen by gate) increasesTransistor turned off permanentlyRe-programmable by exposing to UV radiation

    EPROM Programming Technology

    Used as pull-down devicesConsumes static power

    An Example

    Modulo-4 counter: Specification

    Modulo-4 counter: Logic Implementation

    FPGA Implementation of Modulo-4 Counter

    Xilinx FPGAs

    Symmetric Array based; Array consists of CLBs with LUTs and D-FlipflopsN-input LUTs can implement any n-input boolean functionArray embedded within the periphery of IO blocksArray elements interleaved with routing resources (wire segments, switch matrix and single connection points)Employs SRAM technology

    Generic Xilinx Architecture

    FPGA XC 4000

    XC4000 CLB

    3 LUTs and 2 Flip-flops in a two stage arrangement2 Outputs: Can be registered or combinationalExternal signals can also be registeredMore of internal signals are available for connectionsCan implement any two independent functions of four variables or any single function of five variables

    ALTERA CPLDS

    Hierarchical PLD structureFirst level: LABs (Functional blocks); LAB is similar to SPLDsSecond Level: Interconnections among LABsLAB consists ofProduct term arrayProduct term distributionMacro-cellsExpander product termsInterconnection region: PIAEPROM/EEPROM basedExample: MAX5K, MAX7K

    Altera generic architecture

    MAX 5000

    Three wide AND gate feed an OR gate (Sum of products)XOR gate may be used in arithmetic operations or in polarity selectionOne flipflop per macrocell; Outputs may be registeredFlipflop preset and clear are via product terms; Clock may be either system clock or internally generatedOutput may be driven out or fedbackFeedback is both local and global; Local feedback is within macrocell and is quicker

    MAX5K Macrocell


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