FPGA 2032 Roadmap : A Personal Perspectivexilinx.eetrend.com/files-eetrend-xilinx/forum/... ·...
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FPGA 2032 Roadmap :
A Personal Perspective
Page 1
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Blackberry
2012 1992
Learn from Yesterday
Courtesy : Don McMillan
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Cell Phone
2012 1972
Learn from Yesterday
Courtesy : Don McMillan
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Silicon Roadmap
Courtesy : IMEC
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Interconnect
NSN 5
15x drop in I/O-to-logic ratio
by 2020
Source: ITRS
• Growing gap between number of logic gates and I/O • Technology scaling favors logic density
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What Does 2.5D and 3D Buy Us?
Page 6
Connectivity
Capacity
Crossovers
RAM
Logic
Package Substrate
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3D versus 2.5D
3D 2.5D
Design Flow New Co-Design Evolutionary
Device impact Stress None
Cost High 65nm Interposer
Thermal Challenging Evolutionary
Testing New Methods Evolutionary
Reliability Challenging Evolutionary
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2.5D and 3D Interconnect
Decoupling Capacitances
Integrated Passives
ESD
Memory
Photonics IO
IO devices
Interconnect
Time
Cost
Smart Interposer
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Optical Interconnect
2012 2015 2020
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ASIC Use Model
System Verify
System Integrate
System Design
Legacy Design Port
and Re-verify
3rd party IP re-use
(including Xilinx IP)
New IP Design
New IP Verify
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Model of FPGA HW customer design effort
Design effort
(man-years)
Note: maximum 85% device utilization is assumed % design re-use (fabric only)
1.3 M LCs
2.6 M LCs
150 man-years ($30 million)
to complete the design of large
FPGA with 60% reuse
650K LCs
330K LCs
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SW Use Model : FPGA and Multi-core ASSP
12
Applications
Quality Metric (Performance/
Power/Area)
ASSP
FPGA
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Need for Design Tools
13
Hour Day Week Month
0.25
1
Year
4
16
64
256
Initial Design
Relative
Performance
Design-time
CPU
GPU
FPGA
Gap
Courtesy : David Thomas
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The Programmable Processing Platform A heterogeneous multicore
Application processors
– Hard core and soft core
– External and embedded
– Caches and large memory space
– Unified shared memory
– Full OS support
Streaming micro-engines
– Configurable (soft) vector cores
– Tiny memory footprint
– Many, distributed, memories
– Compute kernels, no OS
Fixed function datapaths
– C to Gates generated
– HDL coded
– Library IP component
DDR3 MemCon
Interconnect A
SMP CPU
X86 CPU DSP
High speed I/O
FPGAs provide a rich set of mapping options for complex algorithms and communication patterns
Discrete GPU
Micro- Engine Array
HW Datapaths
Interconnect B
FPGA
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Parallel Programming
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FPGA
Vid
eo
co
de
c
En
cry
ptio
n
Pa
cke
t
Pro
ce
ssin
g
FF
T
Se
arc
h
Application-Specific
Open CL Software Model
ARM Processor
A9
A9
Automated Hardware/software
partitioning & interfacing Unified
Compiler/Linker
Application Level Programming of Heterogeneous Multi-core
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The Design Stack
Confidential
Design Definition
Design Implementation
Time
Design Definition
Focus R&D on Core Competencies
In-house In-house In-house
Design Definition
Design Implementation
Design Methodology
Design Manufacturing EDA
Design Methodology EDA
Design Methodology
Foundry
Design Manufacturing
FPGA Platform
Design Implementation
Foundry
Design Manufacturing
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Conclusions : 2032 FPGA
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• Silicon Technology Roadmap continues
Challenges : Variability, Fault tolerance, Power limited, Cost
• 2.5 D and 3 D essential
Opportunity : Connectivity, Capacity, Heterogeneity
• HW Design Methods handle complexity
- Re-Use
- Modular Design Flow/Architecture + 10 min 1M LC P&R
- 33% utilization : dark silicon/fault tolerance
• Software Use Model
- Parallel programming
- Heterogeneous Multi-core
- Solve Timing Closure Copyright 2012 Xilinx
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The Singularity
Page 18
10 Transistors = 10 Neurons
Parallel Architecture
Synapse : 10 denser interconnect
Fault tolerant
Asynchronous
Adaptable
Content Addressable Memory
10 more energy efficient
10 10
3
7
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