FPF1320 / FPF1321 IntelliMAX™ Dual-Input Single-Output … · The FPF1320/21 is a Dual-Input...
Transcript of FPF1320 / FPF1321 IntelliMAX™ Dual-Input Single-Output … · The FPF1320/21 is a Dual-Input...
© Semiconductor Components Industries, LLC, 2011
July, 2021 − Rev. 31 Publication Order Number:
FPF1321/D
IntelliMAX� Dual-InputSingle-Output AdvancedPower Switch with TrueReverse-Current Blocking
FPF1320, FPF1321
DescriptionThe FPF1320/21 is a Dual−Input Single−Output (DISO) load switch
consisting of two sets of slew−rate controlled, low on−resistance,P−channel MOSFET switches and integrated analog features.The slew−rate−controlled turn−on characteristic prevents inrushcurrent and the resulting excessive voltage droop on the power rails.The input voltage range operates from 1.5 V to 5.5 V to align with therequirements of low−voltage portable device power rails. FPF1320/21performs seamless power−source transitions between two input powerrails using the SEL pin with advanced break−before−make operation.
FPF1320/21 has a TRCB function to block unwanted reversecurrent from output to input during ON/OFF states. The switch iscontrolled by logic inputs of the SEL and EN pins, which are capableof interfacing directly with low−voltage control signals (GPIO).
FPF1321 has 65 � on−chip load resistor for output quick dischargewhen EN is LOW.
FPF1320/21 is available in 1.0 mm x 1.5 mm WLCSP, 6−bump,with 0.5 mm pitch. FPF1321B is available in 1.0 mm x 1.5 mmWLCSP, 6−bump, 0.5 mm pitch with backside laminate.
Features• DISO Load Switches
• Input Supply Operating Range: 1.5 V ~ 5.5 V
• RON 50 m� at VIN = 3.3 V Per Channel (Typical)
• True Reverse − Current Blocking (TRCB)
• Fixed Slew Rate Controlled 130 �s for < 1 �F COUT
• ISW: 1.5 A Per Channel (Maximum)
• Quick Discharge Feature on FPF1321
• Logic CMOS IO Meets JESD76 Standard for GPIO Interface andRelated Power Supply Requirements
• ESD Protected:♦ Human Body Model: > 6 kV♦ Charged Device Model: > 1.5 kV♦ IEC 61000−4−2 Air Discharge: > 15 kV♦ IEC 61000−4−2 Contact Discharge: > 8 kV
• These are Pb−Free and Halide Free Devices
Applications• Smart Phones / Tablet PCs
• Portable Devices
• Near Field Communication (NFC) Capable SIM Card Power Supply
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MARKING DIAGRAM
WLCSP−6CASE 567RM
Qx = Specific Device Codex = S or T
&K = Traceability Code&. = Pin one dot&2 = Date Code&Z = Assembly plant code
Qx&K&.&2&Z
See detailed ordering and shipping information on page 12 ofthis data sheet.
ORDERING INFORMATION
FPF1320, FPF1321
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APPLICATION DIAGRAM
Figure 1. Typical Application
VIN_A
VIN_B
VINA
VINB
VOUT
GND
SEL EN
COUTCIN1
CIN2
FPF1320/21
BLOCK DIAGRAM
Figure 2. Functional Block Diagram (Output Discharge Path for FPF1321 Only)
VIN_A
VIN_B
VOUT
GNDSEL
EN
Controllogic
TRCB
TRCB
Turn−On Slew RateControlled Driver
Turn−On SlewRate Controlled
Driver
OutputDischarge(Optional)
FPF1320/21
FPF1320, FPF1321
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PIN CONFIGURATION
VOUT
Figure 3. Pin Assignments
A1 A2
B1 B2
C1 C2
A2 A1
B2 B1
C2 C1
Top View Bottom View
GND
VOUT
VINB
SEL
VINAEN
GND
SEL
EN
VOUT
VINB
VINAPin 1 Indicator
PIN DESCRIPTION
Pin # Name Description
A1 EN Enable input. Active HIGH. There is an internal pull−down resistor at the EN pin.
B1 SEL Input power selection inputs. See Truth Table. There are internal pull−down resistors at the SEL pins.
A2 VINA Supply Input. Input to the power switch A.
B2 VOUT Switch output
C1 GND Ground
C2 VINB Supply Input. Input to power switch B.
TRUTH TABLE
SEL EN Switch A Switch B VOUT Status
Low High ON OFF VINA VINA Selected
High High OFF ON VINB VINB Selected
X Low OFF OFF Floating for FPF1320 GND for FPF1321
Both Switches are OFF
FPF1320, FPF1321
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ABSOLUTE MAXIMUM RATINGS
Symbol Parameters Min Max Unit
VIN VINA, VINB, VSEL, VEN, VOUT to GND −0.3 6 V
ISW Maximum Continuous Switch Current per Channel − 1.5 A
PD Total Power Dissipation at TA = 25°C − 1.2 W
TSTG Operating and Storage Junction Temperature −65 150 °C
�JA Thermal Resistance, Junction−to−Ambient(1 in.2 Pad of 2−oz. Copper)
− 85 (Note 1) °C/W
− 110 (Note 2)
ESD Electrostatic Discharge Capability Human Body Model, JESD22−A114 6.0 − kV
Charged Device Model, JESD22−C101 1.5 −
Air Discharge (VINA, VINB to GND),IEC61000−4−2 System Level
15.0 −
Contact Discharge (VINA, VINB to GND),IEC61000−4−2 System Level
8.0 −
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.1. Measured using 2S2P JEDEC std. PCB.2. Measured using 2S2P JEDEC PCB cold−plate method.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameters Min Max Unit
VIN Input Voltage on VINA, VINB 1.5 5.5 V
TA Ambient Operating Temperature −40 85 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyondthe Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS VINA = VINB = 1.5 to 5.5 V, TA = −40 to 85°C unless otherwise noted. Typical values are atVINA = VINB = 3.3 V, TA = 25°C
Symbol Parameter Test Conditions Min Typ Max Unit
BASIC OPERATION
VINA, VINB Input Voltage − 1.5 − 5.5 V
ISD Shutdown Current SEL = HIGH or LOW, EN = GND,VOUT = GND, VINA = VINB = 5.5 V
− − 5 �A
IQ Quiescent Current IOUT = 0 mA, SEL = HIGH orLOW, EN = HIGH, VINA = VINB = 5.5 V
− 12 22 �A
RON
On−Resistance VINA = VINB = 5.5 V,IOUT = 200 mA, TA = 25°C
− 42 60 m�
VINA = VINB = 3.3 V,IOUT = 200 mA, TA = 25°C
− 50 −
VINA = VINB = 1.8 V,IOUT = 200 mA, TA = 25°C to 85°C
− 80 −
VINA = VINB = 1.5 V,IOUT = 200 mA, TA = 25°C
− − 170
VIH SEL, EN Input Logic High Voltage VINA, VINB = 1.5 V – 5.5 V 1.15 − − V
VIL SEL, EN Input Logic Low Voltage VINA, VINB = 1.8 V – 5.5 V − − 0.65 V
SEL, EN Input Logic Low Voltage VINA, VINB = 1.5 V – 1.8 V − − 0.60
VDROOP_OUT Output Voltage Droop while ChannelSwitching from Higher Input Voltage Lower Input Voltage (Note 3)
VINA = 3.3 V, VINB = 5 V, Switching from VINA → VINB, RL = 150 �, COUT = 1 �F
− − 100 mV
ISEL/IEN Input Leakage at SEL and EN Pin − − − 1.2 �A
FPF1320, FPF1321
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ELECTRICAL CHARACTERISTICS VINA = VINB = 1.5 to 5.5 V, TA = −40 to 85°C unless otherwise noted. Typical values are atVINA = VINB = 3.3 V, TA = 25°C (continued)
Symbol UnitMaxTypMinTest ConditionsParameter
BASIC OPERATION (continued)
RSEL_PD/REN_PD
Pull−Down Resistance at SEL or EN Pin − − 7 − M�
RPD Output Pull−Down Resistance SEL = HIGH or LOW, EN = GND,IFORCE = 20 mA, TA = 25°C,FPF1321
− 65 − �
TRUE REVERSE CURRENT BLOCKING
VT_RCB RCB Protection Trip Point VOUT − VINA or VINB − 45 − mV
VR_RCB RCB Protection Release Trip Point VINA or VINB −VOUT − 25 − mV
IRCB VINA or VINB Current During RCB VOUT = 5.5 V,VINA or VINB = Short to GND
− 9 15 �A
tRCB_ON RCB Response Time w hen Device isON (Note 3)
VINA or VINB = 5 V,VOUTVINA,B = 100 mV
− 5 − �s
DYNAMIC CHARACTERISTICS
tDON Turn−On Delay (Note 4) VINA or VINB = 3.3 V, RL = 150 �,CL = 1 �F, TA = 25°C, SEL: HIGH,EN: LOW → HIGH
− 120 − �s
tR VOUT Rise Time (Note 4) − 130 −
tON Turn−On Time (Note 6) − 250 −
tDOFF Turn−Off Delay (Note 4) VINA or VINB = 3.3 V, RL = 150 �,CL = 1 �F, TA = 25°C, SEL: HIGH,EN: HIGH→ LOW
− 15 − �s
tF VOUT Fall Time (Note 4) − 320 −
tOFF Turn−Off Time (Note 7) − 335 −
tDOFF Turn−Off Delay (Note 4, Note 5) VINA or VINB = 3.3 V, RL = 150 �,CL = 1 �F, TA = 25°C, SEL: HIGH,EN: HIGH→ LOW,Output Discharge Mode, FPF1321
− 6 − �s
tF VOUT Fall Time (Note 4, Note 5) − 110 −
tOFF Turn−Off Time (Note 5, Note 7) − 116 −
tTRANR Transition Time LOW → HIGH (Note 4) VINA = 3.3 V, VINB = 5 V, Switching from VINA → VINB, SEL: LOW → HIGH, EN: HIGH, RL = 150 �, CL = 1 �F, TA = 25°C
− 3 − �s
tSLH Switch−Over Rising Delay (Note 4) − 1 −
tTRANF Transition Time HIGH → LOW (Note 4) VINA = 3.3 V, VINB = 5 V,Switching from VINB → VINA, SEL: HIGH → LOW, EN: HIGH,RL = 150 �, C = 1 �F, TA = 25°C
− 45 − �s
tSHL Switch−Over Falling Delay (Note 4) − 5 −
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.3. This parameter is guaranteed by design and characterization; not production tested.4. tDON/tDOFF/tR/tF/tTRANR/tTRANF/tSLH/tSHL are defined in Figure 4.5. FPF1321 output discharge is enabled during off.6. tON = tR + tDON7. tOFF = tF + tDOFF
FPF1320, FPF1321
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TIMING DIAGRAM
Figure 4. Dynamic Behavior Timing Diagram
VINA
VINB
VOUT
SEL
EN
5 V
3.3 V
5 V
3.3 V
5 V
HI
HI
LO
LO LO
GND GND
50%
10%
90%
50% 50%
10%
90% 90% 90%
10%
50%
LO
tDON tR
tSHL
tTRANF tSLH tTRANR
VDROOP
tDOFF tF
Output dischargeof FPF1321
Shutdown Turn−on and VINA Switching fromVINA to VINB
Switching fromVINB to VINA
Shutdown
FPF1320, FPF1321
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TYPICAL CHARACTERISTICS
Figure 5. Supply Current vs. Temperature Figure 6. Supply Current vs. Supply Voltage
−40 −25 −10 205 35 50 65 800.0
5.0
10.0
15.0
20.0
25.0
1.5 20.0
10.0
14.0
Supply Voltage (V)
Qu
iece
nt
Cu
rren
t (�
A)
TJ, Junction Temperature (�C)
Qu
iece
nt
Cu
rren
t (�
A)
Figure 7. Shutdown Current vs. Temperature Figure 8. Shutdown Current vs. Supply Voltage
0
3000
4000
5000
6000
7000
Supply Voltage (V)
Sh
utd
ow
n C
urr
ent
(nA
)
TJ, Junction Temperature (�C)
Sh
utd
ow
n C
urr
ent
(nA
)
Figure 9. RON vs. Temperature Figure 10. RON vs. Supply Voltage
0
60
80
100
120
140
Supply Voltage (V)
RO
N, O
n R
esis
tan
ce (
m�
)
TJ, Junction Temperature (�C)
RO
N, O
n R
esis
tan
ce (
m�
)
VIN = 5.5 V
VIN = 1.5 V
12.0
8.0
6.0
4.0
2.0
2.5 3 3.5 4 4.5 5 5.5
2000
1000
−1000−40 −25 −10 205 35 50 65 80
0
3000
2000
1000
2500
1500
500
1.5 2 2.5 3 3.5 4 4.5 5 5.5
40
20
−40 −20 200 40 60 80 1.5 2 2.5 3 3.5 4 4.5 5 5.5
60
80
100
120
140
40
20
0
85°C
−40°C
25°C
VIN = 5.5 V
VIN = 1.5 V
85°C
−40°C25°C
VINA = 1.5 V
VINA = 1.8 V
VINA = 3.3 V
VINA = 5.5 V
IOUT = 200 mA IOUT = 200 mA
85°C
−40°C
25°C
FPF1320, FPF1321
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TYPICAL CHARACTERISTICS (continued)
Figure 11. VIL vs. Temperature Figure 12. VIL vs. Supply Voltage
−40 −25 −10 205 35 50 65 800.60
0.80
0.85
0.90
0.95
1.00
1.8 2.3
Supply Voltage (V)
Inp
ut
Lo
gic
Lo
w V
olt
age
(V)
TJ, Junction Temperature (�C)
Inp
ut
Lo
gic
Lo
w V
olt
age
(V)
Figure 13. VIH vs. Temperature Figure 14. VIH vs. Supply Voltage
Supply Voltage (V)
Inp
ut
Lo
gic
Hig
h V
olt
age
(V)
TJ, Junction Temperature (�C)
Inp
ut
Lo
gic
Hig
h V
olt
age
(V)
Figure 15. VIH/VIL vs. Supply Voltage Figure 16. RSEL_PD and REN_PD vs. Temperature
TJ, Junction Temperature (�C)
Pu
ll−D
ow
n R
esis
tan
ce (
M�
)
Supply Voltage (V)
Inp
ut
Lo
gic
Vo
ltag
e (V
)
2.8 3.3 3.8 4.3 4.8 5.3
−40 −25 −10 205 35 50 65 80
7.0
7.5
8.0
8.5
9.0
6.5
6.0
5.5
0.75
0.70
0.65
0.80
0.85
0.90
0.95
1.00
0.75
0.70
VIN = 1.5 V
VIN = 5.5 V
VIN = 3.3 V85°C
−40°C
25°C
0.60
0.80
0.85
0.90
0.95
1.00
0.75
0.70
0.65
VIN = 1.5 V
VIN = 5.5 V
VIN = 3.3 V
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
0.80
0.85
0.90
0.95
1.00
0.75
0.70
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
0.80
0.85
0.90
0.95
1.00
0.75
0.70
85°C
−40°C
25°C
25°C
VIH
VIL
EN = 6 V
EN = 1.5 V
−40 −20 200 40 60 80
FPF1320, FPF1321
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TYPICAL CHARACTERISTICS (continued)
tF
Figure 17. RSEL_PD and REN_PD vs. Supply Voltage Figure 18. tDON and tDOFF vs. Temperature
1.5 2.5 3.5 4.5 5.55.0
7.0
7.5
8.0
8.5
−40 −15
TJ, Junction Temperature (�C)
On
/Off
Del
ay T
ime
(�s)
Supply Voltage (V)
Pu
ll−D
ow
n R
esis
tan
ce (
M�
)
Figure 19. tR and tF with FPF1320 vs. Temperature Figure 20. tR and tF with FPF1321 vs. Temperature
TJ, Junction Temperature (�C)
Ris
e/F
all T
ime
(�s)
TJ, Junction Temperature (�C)
Ris
e/F
all T
ime
(�s)
Figure 21. Transition Time vs. Temperature Figure 22. Switch Over Time vs. Temperature
TJ, Junction Temperature (�C)
Sw
itch−O
ver
Del
ay (�
s)
TJ, Junction Temperature (�C)
Tran
siti
on
Tim
e (�
s)
10 35 60 85
−40 −15 10 35 60 85
2
3
4
5
1
0
6.5
6.0
5.5
99
119
139
159
179
79
59
VIN = 3.3 VCL = 1 �FRL = 150 �
85°C
−40°C
25°C
60
260
310
360
410
460
210
160
110
110
130
150
170
190
90
70
20
30
40
50
60
10
0
39
−1
19
10 10
30
50
−40 −15 10 35 60 85
−40 −15 10 35 60 85 −40 −15 10 35 60 85
2
3
4
5
1
tDON
tDOFF
tRVIN = 3.3 VCL = 1 �FRL = 150 �
tF
tR
VIN = 3.3 VCL = 1 �FRL = 150 �
tTRANR
tTRANF
VIN = 5 V to 3.3 VCL = 1 �FRL = 150 �
tSLH
tSHL
VIN = 5 V to 3.3 VCL = 1 �FRL = 150 �
FPF1320, FPF1321
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TYPICAL CHARACTERISTICS (continued)
Figure 23. TRCB Trip and Release vs. Temperature Figure 24. IRCB vs. Temperature
−40 −25 −10 5 20
50
70
10
40
20
TJ, Junction Temperature (�C)
IRC
B (�
A)
TJ, Junction Temperature (�C)
RC
B T
rip
/Rel
ease
A (
mV
)
Figure 25. RPD with FPF1321 vs. Temperature
Figure 26. Turn−On Response (VINA = 3.3 V, CIN = 1 �F, COUT = 1 �F, RL = 150 �,
SEL = LOW)
TJ, Junction Temperature (�C)
Ou
tpu
t P
ull
Do
wn
Res
ista
nce
(�
)
Figure 27. Turn−Off Response with FPF1320(VINA = 3.3 V, CIN = 1 �F, COUT = 1 �F, RL = 150 �,
SEL = LOW)
Figure 28. Turn−Off Response with FPF1321(VINA = 3.3 V, CIN = 1 �F, COUT = 1 �F, RL = 150 �,
SEL = LOW)
−40 −20 0 20 60 80
30
60
0
9.0
10.0
11.0
12.0
8.0
7.0
50.0
70.0
75.0
80.0
85.0
65.0
60.0
55.0
6.0
4.0
5.0
45.0
35 50 65 80
Trip
Release
−40 −25 −10 5 20 35 50 65 80
40
RPD
FPF1320, FPF1321
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TYPICAL CHARACTERISTICS (continued)
Figure 29. Power Source Transition from3.3 V to 5 V (VINA = 3.3 V, VINB = 5 V, CIN = 1 �F,
COUT = 1 �F, RL = 150 �)
Figure 30. Power Source Transition from 5 V to 3.3 V (VINA = 3.3 V, VINB = 5 V, CIN = 1 �F,
COUT = 1 �F, RL = 150 �)
Figure 31. TRCB During Off(VINA = VINB = Floating, VOUT = 5 V, CIN = 1 �F,
COUT = 1 �F, EN = LOW, No RL)
Figure 32. TRCB During On(VINA = 5 V, VOUT = 6 V, CIN = 1 �F, COUT = 1 �F,
EN = HIGH, No RL)
OPERATION AND APPLICATION DESCRIPTION
The FPF1320 and FPF1321 are dual−input single−outputpower multiplexer switches with controlled turn−on andseamless power source transition. The core is a 50 m�
P−channel MOSFET and controller capable of functioningover a wide input operating range of 1.5 V to 5.5 V perchannel. The EN and SEL pins are active−HIGH,GPIO/CMOS−compatible input. They control the state ofthe switch and input power source selection, respectively.TRCB functionality blocks unwanted reverse current duringboth ON and OFF states when higher VOUT than VINA orVINB is applied. FPF1321 has a 65 � output discharge pathduring off.
Input CapacitorTo limit the voltage drop on the input supply caused by
transient inrush current when the switch turns on intoa discharged load capacitor; a capacitor must be placedbetween the VINA or VINB pins to the GND pin. At least1 �F ceramic capacitor, CIN, placed close to the pins, isusually sufficient. Higher−value CIN can be used to reducemore the voltage drop.
Inrush CurrentInrush current occurs when the device is turned on. Inrush
current is dependent on output capacitance and slew ratecontrol capability, as expressed by:
IINRUSH � COUT �VIN � VINITIAL
tR� ILOAD (eq. 1)
FPF1320, FPF1321
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where:COUT: Output capacitance;tR: Slew rate or rise time at VOUT;VIN: Input voltage, VINA or VINB;VINITIAL: Initial voltage at COUT, usually GND; andILOAD: Load current.
Higher inrush current causes higher input voltage drop,depending on the distributed input resistance and inputcapacitance. High inrush current can cause problems.
FPF1320/1 has a 130 �s of slew rate capability under3.3 VIN at 1 �F of COUT and 150 � of RL so inrush currentand input voltage drop can be minimized.
Power Source SelectionInput power source selection can be controlled by the SEL
pin. When SEL is LOW, output is powered from VINA whileSEL is HIGH, VINB is powering output. The SEL signal isignored during device OFF.
Output Voltage Drop During TransitionOutput voltage drop usually occurs during input power
source transition period from low voltage to high voltage.The drop is highly dependent on output capacitance and loadcurrent.
FPF1320/1 adopts an advanced break−before−makecontrol, which can result in minimized output voltage dropduring the transition time.
Output CapacitorCapacitor COUT of at least 1 �F is highly recommended
between the VOUT and GND pins to achieve minimizedoutput voltage drop during input power source transition.This capacitor also prevents parasitic board inductance.
True Reverse−Current BlockingThe true reverse−current blocking feature protects the
input source against current flow from output to inputregardless of whether the load switch is on or off.
Board LayoutFor best performance, all traces should be as short as
possible. To be most effective, the input and outputcapacitors should be placed close to the device to minimizethe effect that parasitic trace inductance on normal andshort−circuit operation. Wide traces or large copper planesfor power pins (VINA, VINB, VOUT and GND) minimizethe parasitic electrical effects and the thermal impedance.
ORDERING INFORMATION
Part NumberTop
Mark Channel
Switch PerChannel (Typ.)
at 3.3 VIN
ReverseCurrent
BlockingOutput
DischargeRise Time
(tR) Package
FPF1320UCX QS DISO 50 m� Yes NA 130 �s 1.0 mm × 1.5 mm Wafer−Level Chip−ScalePackage (WLCSP)6−Bumps, 0.5 mm Pitch
FPF1321UCX QT DISO 50 m� Yes 65 � 130 �s
FPF1321BUCX QT DISO 50 m� Yes 65 � 130 �s 1.0 mm × 1.5 mm Wafer−Level Chip−ScalePackage (WLCSP)6−Bumps, 0.5 mm Pitch with Backside Laminate
PRODUCT−SPECIFIC DIMENSIONS
Product D E X Y
FPF1320UCX 1460 �m ±30 �m 960 �m ±30 �m 230 �m 230 �m
FPF1321UCX 1460 �m ±30 �m 960 �m ±30 �m 230 �m 230 �m
FPF1321BUCX 1460 �m ±30 �m 960 �m ±30 �m 230 �m 230 �m
IntelliMAX is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
WLCSP6 1.46x0.96x0.582CASE 567RM
ISSUE ODATE 30 NOV 2016
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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