Force Feedback in MEMS Inertial Sensors

Ain Shams University

Faculty of Engineering

Electronics and Communications Department

Force Feedback in MEMS Inertial Sensors

A ThesisSubmitted in partial fulfillment for the requirements of Master of Science

degree in Electrical Engineering

Submitted by:

Mohammad Adel ElbadryB.Sc. of Electrical Engineering

(Electronics and Communications Department)

Ain Shams University, 2005.

Supervised by:

Prof. Dr. Hany Fikry

Prof. Dr. Hisham Haddara

Cairo 2009

Curriculum Vitae

Name: Mohammad Adel Elbadry

Date of Birth: 20/8/1983

Place of Birth: Heliopolis, Egypt

First University Degree: B.Sc. in Electrical Engineering

Name of University: Ain Shams University

Date of Degree: June 2005

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Statement

This dissertation is submitted to Ain Shams University for the degree of

Master of Science in Electrical Engineering (Electronics and Communica-

tions Engineering).

The work included in this thesis was carried out by the author at the Elec-

tronics and Communications Engineering Department, Faculty of Engineer-

ing, Ain Shams University, Cairo, Egypt.

No part of this thesis was submitted for a degree or a qualification at any

other university or institution.

Name: Mohammad Adel Elbadry

Date: 04/05/2009

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AcknowledgmentsAll praise is due to Allah, Most Merciful, the Lord of the Worlds, Who taught man what he knewnot. I would like to thank God Almighty for bestowing upon me the chance, strength and abilityto complete this work.I wish to express my gratitude to my supervisors, Professor Hany Fikry and Professor HishamHaddara for their exceptional guidance, encouragement, flexibility, insightful thoughts and usefuldiscussions.I am deeply indebted to Dr. Ayman Elsayed, design manager at Si-Ware systems, whose help,stimulating suggestions and encouragement helped me in all the time of research for and writingof this thesis. I have learned a lot form him, on both the technical and personal levels. I am inno way capable of appropriately thanking him for his great help to me.I am also grateful to Dr. Hassan Aboushady, of LIP6, University of Paris VI, for his help andsupport in the system level studies. His help was a great boost to my work.Special thanks goes to my colleagues at Si-Ware systesm: Botros George, Ahmed Elshennawy,Ahmed Safwat, Ahmed Shaban and Mohamed Elkholy for the many fruitful discussions, encour-agement, as well as helping me revise the thesis.I would like also to thank Amr Misbah and Bichoy Waguih, my colleagues at IC Lab, Ain ShamsUniversity, for their generous help and support in IT problems.Many thanks are also due to my Professors and colleagues at IC Lab, Ain Shams University, fortheir knowledge, help and support.Finally I would like to express my love and gratitude to my parents and my brother for theirunconditional love and unlimited support.

Mohammad Adel ElbadryElectrical and Communications DepartmentFaculty of EngineeringAin Shams UniversityCairo, Egypt2009

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AbstractMohammad Adel Elbadry, ”Force Feedback in MEMS Inertial Sensors”, Master of

Science dissertation, Ain Shams University, 2009.

This thesis presents analysis of the non-idealities in the feedback path of ΣΔ Force-FeedbackMEMS inertial sensors as well as the circuit implementation of the reference voltage for thefeedback. A high-performance MEMS accelerometer sensing system is used as a test-vehicle forthe presented analysis and design.

On the system level, analysis is performed on the effect of clock-jitter in the feedback pathon the signal-to-noise (SNR) ratio of the accelerometer system. The effect of both white jitterand cumulative jitter are investigated. It is shown that cumulative jitter has negligible effect onthe SNR of high performance ΣΔ Force-Feedback systems. On the other hand, it is shown thatwhite jitter can severely limit the SNR of ΣΔ Force-Feedback systems. Analytical relations arederived for the effect of Jitter on SNR.

Analysis is also performed on the effect of the reference voltage noise, in the feedback path,on the SNR of ΣΔ Force-Feedback systems. Analytical relations are derived that describe theeffect of the reference noise on the achievebale SNR. It is shown that the reference noise doesnot limit the sensitivity of the system; it only affects the maximum achievable SNR. It is alsoshown that the maximum SNR will be independent on the signal level; it will only depend on theReference Voltage-to-Reference voltage noise ratio.

Based on the system-level analysis, specs are derived for the voltage reference for achievinga 110dB SNR on system level. The various reference-voltage technologies are overviewed, andbandgap technology is chosen. Circuit implementation of a low-noise bandgap reference circuit isthen performed on a SiGe 0.35μm BiCMOS technology. Three different topologies of the bandgapvoltage are implemented and simulated.

The 1st bandgap circuit is a conventional CMOS implementation of the bandgap circuitwith a 1st order temperature compensation. Chopping is used to overcome 1/f noise. Circuitimplementation is made to enable trimming the reference for minimum temperature coefficientin case of process variations. This reference achieves a total integrated noise of 1μV from 1 mHzto 100Hz with a reference voltage value of 1.2V.

The 2nd circuit is also a 1st order compensated bandgap that makes use of the npn bipolarsavailable in the technology to achieve the low-flicker noise target. The circuit is capable of

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generating a 1.2V and a 2.4V references simultaneously and achieves a total integrated noise ofless than 2μV (in the 1mHz-100Hz range) on the 2.4V reference.

In the 3rd circuit, a new higher-order temperature compensation technique is proposed andimplemented. The circuit achieves a 0.55ppm/◦C temperature coefficient over the -40◦C-125◦Ctemperature range. The integrated noise, however, is an order of magnitude larger than the othertwo implementations.

Key words: Voltage Reference, Bandgap, Low-Noise, Temperature Compensation, MEMS,Inertial Sensor, Accelerometer, chopping, Jitter, BiCMOS, SiGe, PTAT, CTAT, ΣΔ, Force-Feedback, Force-balancing

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SummaryChapter 1 is an introduction to the thesis.

Chapter 2 is an overview on MEMS Inertial Sensors and Interface circuits. Both MEMS ac-celerometers and MEMS gyroscopes are overviewed and their operating principles are presented.The different interface options (open-loop and close-loop) are presented and discussed

Chapter 3 discusses the non-idealities in the feedback path of ΣΔ Force-Feedback systems .Analysis is focused on the effect of clock jitter, reference voltage noise and pulse shape on theperformance of such systems

Chapter 4 presents an overview of the different reference voltage generation technologies. Theperformance metrics of voltage references are first defined. This is followed by an overview onvoltage reference technologies in both literature and industrial designs

Chapter 5 presents extensive analysis of bandgap references followed by three different imple-mentations of low-noise references for use in high performance force-feedback systems, includinga new temperature-compensation technique for achieving low temperature drift. The referencespecs are first derived (based on a MEMS accelerometer sensing system), then analysis is made forthe various performance metrics of bandgap references. Finally, circuit designs and simulationsare presented

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Contents

List of tables xiii

List of figures xiv

List of Symbols xx

List of Abbreviations xxii

1 Introduction 1

1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Overview on MEMS Inertial Sensors and Interface Circuits 4

2.1 MEMS Accelerometers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1.1 Principle of Operation . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 MEMS Gyroscopes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2.1 Principle of Operation . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 Interface circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3.1 Open Loop Architectures . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3.2 Force-Feedback Architectures . . . . . . . . . . . . . . . . . . . . . 12

2.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Feedback Non-idealities in ΣΔ Force-Feedback Systems 15

3.1 Generic ΣΔ Force-Feedback System . . . . . . . . . . . . . . . . . . . . . . 15

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3.2 The acceleration sensing system . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3 Non-idealities in ΣΔ Force-Feedback systems . . . . . . . . . . . . . . . . . 17

3.3.1 Pulse Shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.3.2 Effect of Clock Jitter in ΣΔ Force-Feedback systems . . . . . . . . 20

3.3.2.1 Effect of Jitter in Continuous time ΣΔ modulators . . . . 20

3.3.2.2 Decreasing sensitivity to Jitter . . . . . . . . . . . . . . . 24

3.3.2.2.1 Using Multi-bit Feedback DAC . . . . . . . . . . 24

3.3.2.2.2 Using Linear DAC pulse-shaping . . . . . . . . . 25

3.3.2.2.3 Using Quadratic DAC pulse-shaping . . . . . . . 26

3.3.2.3 Effect of Jitter in the acceleration sensing system . . . . . 27

3.3.2.4 Jitter Simulations . . . . . . . . . . . . . . . . . . . . . . 29

3.3.2.4.1 Using Multi-bit Feedback DAC . . . . . . . . . . 32

3.3.2.4.2 Using Linear DAC pulse-shaping . . . . . . . . . 32

3.3.2.4.3 Using Quadratic DAC pulse-shaping . . . . . . . 33

3.3.2.5 Accumulated Jitter . . . . . . . . . . . . . . . . . . . . . . 33

3.3.2.5.1 Effect of jitter for different jitter frequencies . . . 34

3.3.2.5.2 Maximum allowable close-in jitter . . . . . . . . . 35

3.3.2.5.3 Effect of clock with both white and accumulated jitter 35

3.3.2.6 Conclusions on Jitter . . . . . . . . . . . . . . . . . . . . . 36

3.3.3 Reference Voltage Noise . . . . . . . . . . . . . . . . . . . . . . . . 38

3.3.3.1 Reference Voltage multiplication . . . . . . . . . . . . . . 38

3.3.3.2 Effect of Reference Noise on SNR . . . . . . . . . . . . . . 39

3.3.3.2.1 Ffb refn is dominant . . . . . . . . . . . . . . . . 40

3.3.3.2.2 Ffb qnref is dominant . . . . . . . . . . . . . . . . 42

3.3.3.2.3 Ffb qn is dominant . . . . . . . . . . . . . . . . . 44

3.4 Proposed System and DAC specs . . . . . . . . . . . . . . . . . . . . . . . 46

4 Reference Voltage Generation: An Overview 47

4.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.1.1 Initial Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.1.2 Temperature Coefficient . . . . . . . . . . . . . . . . . . . . . . . . 48

4.1.3 Long-term Drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

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4.2 Reference Voltage Technologies . . . . . . . . . . . . . . . . . . . . . . . . 49

4.2.1 Zener-Based References . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.2.1.1 Review of Zener-Based References . . . . . . . . . . . . . 52

4.2.2 XFET references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.2.3 Floating-Gate References . . . . . . . . . . . . . . . . . . . . . . . . 57

4.2.3.1 Introduction to Floating-Gate transistors . . . . . . . . . . 57

4.2.3.2 Programming Techniques for Floating Gate transistors . . 58

4.2.3.3 Review of floating-gate references . . . . . . . . . . . . . . 59

4.2.4 Bandgap References . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4.2.4.1 Introduction to Bandgap references . . . . . . . . . . . . . 63

4.2.4.2 Review of Bandgap References . . . . . . . . . . . . . . . 65

4.2.4.2.1 Differential Bandgap references . . . . . . . . . . 67

4.2.4.2.2 Low-Voltage Bandgap References . . . . . . . . . 70

4.2.4.2.3 Higher-Order Compensated Bandgap References . 70

4.2.4.3 Performance of Commercial bandgap references . . . . . . 72

4.2.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5 Circuit Implementation 73

5.1 Choosing Reference Voltage Technology . . . . . . . . . . . . . . . . . . . . 73

5.2 Reference Voltage Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.2.1 Reference Voltage Value . . . . . . . . . . . . . . . . . . . . . . . . 75

5.2.2 Output Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.2.3 Drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.3 The Basic Bandgap Circuit: An overview . . . . . . . . . . . . . . . . . . . 76

5.3.1 Lateral versus Vertical PNP in bandgap circuits . . . . . . . . . . . 80

5.3.2 Long-term drift in bandgaps . . . . . . . . . . . . . . . . . . . . . . 83

5.3.3 Stability of the CMOS-compatible bandgap . . . . . . . . . . . . . 84

5.3.3.1 Evaluating the Loop Gain . . . . . . . . . . . . . . . . . . 84

5.3.3.2 Effect of output node choice on stability . . . . . . . . . . 88

5.3.4 Opamp Gain Requirement in the CMOS-compatible bandgap . . . 92

5.3.5 Supply Rejection in the CMOS-compatible Bandgap Circuit . . . . 95

5.3.5.1 DC Supply Rejection . . . . . . . . . . . . . . . . . . . . . 96

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5.3.5.2 High Frequency Supply Rejection . . . . . . . . . . . . . . 101

5.3.6 Noise in the CMOS-compatible Bandgap Circuit . . . . . . . . . . . 111

5.3.6.1 Opamp Noise Contribution . . . . . . . . . . . . . . . . . 112

5.3.6.2 RPT Noise Contribution . . . . . . . . . . . . . . . . . . . 113

5.3.6.3 RCT Noise Contribution . . . . . . . . . . . . . . . . . . . 114

5.3.6.4 Mp1 Noise Contribution . . . . . . . . . . . . . . . . . . . 116

5.3.6.5 Mp2 Noise Contribution . . . . . . . . . . . . . . . . . . . 117

5.3.6.6 Q2 Noise Contribution . . . . . . . . . . . . . . . . . . . . 118

5.3.6.7 Q1 Noise Contribution . . . . . . . . . . . . . . . . . . . . 120

5.3.6.8 Summary and discussion of noise contributions . . . . . . 122

5.3.7 Mismatch errors in the CMOS-compatible Bandgap Circuit . . . . . 123

5.3.7.1 Effect of Opamp’s input-offset voltage . . . . . . . . . . . 124

5.3.7.2 Effect of mismatch of PMOS current sources . . . . . . . . 125

5.3.7.3 Effect of mismatch of the BJT transistors . . . . . . . . . 127

5.3.7.4 Effect of resistor mismatch . . . . . . . . . . . . . . . . . . 128

5.4 Bandgap Reference Voltage Implementation . . . . . . . . . . . . . . . . . 130

5.4.1 Conventional Bandgap Reference: circuit 1 . . . . . . . . . . . . . . 130

5.4.1.1 Circuit 1: Bipolar transistor choice . . . . . . . . . . . . . 130

5.4.1.2 Circuit 1: Opamp choice and biasing . . . . . . . . . . . . 130

5.4.1.2.1 Noise Considerations in Opamp Design . . . . . . 132

5.4.1.2.2 Self-Bias Loop for the Opamp . . . . . . . . . . . 133

5.4.1.2.3 Bias of the cascode transistors . . . . . . . . . . . 136

5.4.1.3 Circuit 1: PMOS current-mirror and resistors . . . . . . . 137

5.4.1.4 Circuit 1: Startup circuit . . . . . . . . . . . . . . . . . . 139

5.4.1.5 Circuit 1: DC performance . . . . . . . . . . . . . . . . . 140

5.4.1.6 Circuit 1: Supply rejection . . . . . . . . . . . . . . . . . . 141

5.4.1.7 Circuit 1: Loop Stability . . . . . . . . . . . . . . . . . . . 142

5.4.1.8 Circuit 1: Noise Performance . . . . . . . . . . . . . . . . 143

5.4.1.9 Circuit 1: Using a Chopped Opamp . . . . . . . . . . . . 146

5.4.1.9.1 Choosing the chopping frequency . . . . . . . . . 146

5.4.1.9.2 Effect of Chopped Offset on SNR . . . . . . . . . 148

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5.4.1.9.3 Chopping configurations . . . . . . . . . . . . . . 150

5.4.1.9.4 Effect of switches on Stability . . . . . . . . . . . 151

5.4.1.9.5 Filtering the Chopped reference . . . . . . . . . . 152

5.4.1.9.6 Noise Performance of the Chopped bandgap . . . 153

5.4.1.10 Circuit 1: Trimming for Temperature Coefficient . . . . . 154

5.4.2 BiCMOS Bandgap Reference: Circuit 2 . . . . . . . . . . . . . . . . 158

5.4.2.1 Circuit 2: Voltage Headroom . . . . . . . . . . . . . . . . 158

5.4.2.2 Circuit 2: Expressions of Vbg2 and Vbg1 . . . . . . . . . . . 160

5.4.2.3 Circuit 2: BiCMOS Opamp . . . . . . . . . . . . . . . . . 161

5.4.2.3.1 Opamp headroom considerations . . . . . . . . . 161

5.4.2.3.2 Opamp tail current . . . . . . . . . . . . . . . . . 162

5.4.2.4 Choosing I ′ . . . . . . . . . . . . . . . . . . . . . . . . . . 163




5.4.3 Higher Order Compensated Bandgap: Circuit 3 . . . . . . . . . . . 166

5.4.3.1 Circuit 3: Basic Concept . . . . . . . . . . . . . . . . . . . 166

5.4.3.1.1 Previous Implementation . . . . . . . . . . . . . . 168

5.4.3.1.2 Suggested Implementation: A current-mode approach169




5.4.3.5 Circuit 3: Comparison with other compensation techniques 182

5.4.4 Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . 183

Conclusions 184

Future Work 185

Appendices 186

A MEMS acceleration system DA-IC model 186

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B Opamp Behavioral model 188

References 190

xiii

List of Tables

4.1 Key Specs of commercial Zener references . . . . . . . . . . . . . . . . . . 54

4.2 Key Specs of the XFET reference ADR425 . . . . . . . . . . . . . . . . . . 57

4.3 Key Specs of X60008A-50 . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4.4 Key Specs of commercial bandgap references . . . . . . . . . . . . . . . . . 72

5.1 Loop Gain Simulated versus Calculated values . . . . . . . . . . . . . . . . 87

5.2 PSR0 Simulated versus Calculated values . . . . . . . . . . . . . . . . . . 99

5.3 Noise Contribution of bandgap circuit components to the output noise . . . 122

5.4 Major Noise Contributors in Circuit 1 . . . . . . . . . . . . . . . . . . . . . 143

5.5 Comparison between circuit 3 and reported implementations . . . . . . . . 182

5.6 Performance Comparison of Circuits 1, 2, and 3 . . . . . . . . . . . . . . . 183

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List of Figures

2.1 Mechanical model for an accelerometer [Beeby 04] . . . . . . . . . . . . . . 5

2.2 A MEMS accelerometer structure [Yazdi 98] . . . . . . . . . . . . . . . . . 6

2.3 The Coriolis Effect [Beeby 04] . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Lumped gyroscope model [Beeby 04] . . . . . . . . . . . . . . . . . . . . . 9

2.5 MEMS Gyroscope of [Clark 96] . . . . . . . . . . . . . . . . . . . . . . . . 10

2.6 A conceptual Open-Loop sensing interface [Beeby 04] . . . . . . . . . . . . 11

2.7 Digital ΣΔ force-feedback [Petkov 05] . . . . . . . . . . . . . . . . . . . . . 13

3.1 Generic ΣΔ Force-Feedback System . . . . . . . . . . . . . . . . . . . . . 16

3.2 Effect of Rise-Fall time assymetry . . . . . . . . . . . . . . . . . . . . . . . 18

3.3 Effect of rise-fall time assymetry for NRZ case . . . . . . . . . . . . . . . . 19

3.4 SNR versue ΔTrf for NRZ case . . . . . . . . . . . . . . . . . . . . . . . . 19

3.5 Jitter Entry Points in a continuous-time ΣΔ modulator . . . . . . . . . . . 20

3.6 Effect of Clock Jitter at the sampling point . . . . . . . . . . . . . . . . . . 21

3.7 Effecr of Jitter on Feedback Pulse . . . . . . . . . . . . . . . . . . . . . . . 22

3.8 a RZ DAC pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.9 Using Multi-Bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.10 a linear DAC pulse-shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.11 a quadratic DAC pulse-shape . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.12 Block Diagram of the acceleration sensing system . . . . . . . . . . . . . . 28

3.13 Acceleration sensing system in in DA-IC with RZ feedback . . . . . . . . . 30

3.14 RZ pulse with jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.15 Output Spectra for different rms jitter values . . . . . . . . . . . . . . . . . 31

3.16 SJNR vs rms Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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3.17 Spectra for Sinusoidal 100ps rms jitter with different frequencies . . . . . . 34

3.18 Output spectrum for 100ns rms sinusoidal jitter . . . . . . . . . . . . . . . 35

3.19 Realistic clock with white noise floor and close-in noise skirt . . . . . . . . 36

3.20 Output spectra for a realistic clock and a clock with only white jitter . . . 37

3.21 Illustration of Vref multiplication . . . . . . . . . . . . . . . . . . . . . . . 38

3.22 Spectra for ideal system and system with dominant reference noise . . . . 41

3.23 Illustrating noise-folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.24 Spectra for ideal system and system with wideband ref. noise . . . . . . . . 43

3.25 Spectra for three different input accelerations . . . . . . . . . . . . . . . . 44

4.1 Box method definition for temperature coefficient . . . . . . . . . . . . . . 48

4.2 Illustration of long-term drift . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.3 I-V characteristics of a Zener-diode . . . . . . . . . . . . . . . . . . . . . . 50

4.4 Zener Diode structures [AMI 05] . . . . . . . . . . . . . . . . . . . . . . . . 51

4.5 The LM199 Zener reference [Nat 05a] . . . . . . . . . . . . . . . . . . . . . 52

4.6 Temperature-regulated Zener reference [Laude 80] . . . . . . . . . . . . . . 53

4.7 The XFETTM

reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.8 A floating-gate transistor [Guillermo 07] . . . . . . . . . . . . . . . . . . . 58

4.9 Programming the floating gate transistor . . . . . . . . . . . . . . . . . . . 59

4.10 Floating Gate reference in [Cook 04] . . . . . . . . . . . . . . . . . . . . . 60

4.11 Differential Dual Floating Gate [Ahuja 05] . . . . . . . . . . . . . . . . . . 61

4.12 Programming Loops for Floating-Gate reference in [Ahuja 05] . . . . . . . 62

4.13 Conceptual Bandgap Reference [Holman 94] . . . . . . . . . . . . . . . . . 63

4.14 Generating PTAT voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.15 The Brokaw bandgap reference [Brokaw 74] . . . . . . . . . . . . . . . . . . 65

4.16 The AD580 commercial reference [Pease 90] . . . . . . . . . . . . . . . . . 66

4.17 The LM4040 commercial reference [Nat 05b] . . . . . . . . . . . . . . . . . 67

4.18 Differential Bandgap Reference [Ferro 89] . . . . . . . . . . . . . . . . . . . 68

4.19 Switched Capacitor Differential Bandgap Reference [Nicollini 91] . . . . . . 69

4.20 Low Voltage Bandgap Reference [Banba 99] . . . . . . . . . . . . . . . . . 71

5.1 A Basic Bandgap circuit [Kujik 73] [Razavi 01] . . . . . . . . . . . . . . . . 77

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5.2 CMOS-compatible bandgap circuit . . . . . . . . . . . . . . . . . . . . . . 78

5.3 A cross section of a lateral PNP transistor in CMOS technology [Pertijs 06] 81

5.4 A cross section of a vertical PNP transistor in CMOS technology [Pertijs 06] 82

5.5 CMOS-compatible bandgap with positive and negative feedback indicated . 85

5.6 AC model used for evaluating Loop Gains in CMOS-compatible bandgap . 86

5.7 Equivalent AC model of the overall negative-feedback . . . . . . . . . . . . 88

5.8 Loop Gain and Phase for CL connected to Voutp and Vout . . . . . . . . . . 90

5.9 Model for evaluating the effect of finite Opamp gain . . . . . . . . . . . . . 93

5.10 Bandgap circuit with Offset voltage representing effect of finite gain . . . . 93

5.11 Model used for PSR evaluation . . . . . . . . . . . . . . . . . . . . . . . . 96

5.12 PSR0 versus Gop0 illustrating the possibility of a zero PSR0 . . . . . . . . 100

5.13 PSR and Loop Gain for Cc connected to ground . . . . . . . . . . . . . . . 105

5.14 PSR and Loop Gain for Cc connected to ground . . . . . . . . . . . . . . . 106

5.15 PSR and Loop Gain for Cc connected to Vdd and to ground . . . . . . . . . 108

5.16 PSR for Cc connected to Vdd at different Gop0 . . . . . . . . . . . . . . . . 109

5.17 Real Opamp used for validation of PSR . . . . . . . . . . . . . . . . . . . . 109

5.18 PSR for Cc connected to Vdd and ground for real Opamp . . . . . . . . . . 110

5.19 Noise sources in the CMOS-compatible bandgap circuit . . . . . . . . . . . 111

5.20 AC model for noise contribution of vnop . . . . . . . . . . . . . . . . . . . . 112

5.21 AC model for noise contribution of vnrpt . . . . . . . . . . . . . . . . . . . 113

5.22 AC model for noise contribution of vnrct1 . . . . . . . . . . . . . . . . . . . 115

5.23 AC model for noise contribution of inmp1 . . . . . . . . . . . . . . . . . . . 117

5.24 AC model for noise contribution of inmp2 . . . . . . . . . . . . . . . . . . . 118

5.25 AC model for noise contribution of inq2 . . . . . . . . . . . . . . . . . . . . 119

5.26 AC model for noise contribution of inq1 . . . . . . . . . . . . . . . . . . . . 121

5.27 Bandgap with Chopped Opamp . . . . . . . . . . . . . . . . . . . . . . . . 124

5.28 Bandgap with mismatch in PMOS current mirror . . . . . . . . . . . . . . 126

5.29 Bandgap with mismatch in BJT’s . . . . . . . . . . . . . . . . . . . . . . . 127

5.30 Bandgap with mismatch in resistors . . . . . . . . . . . . . . . . . . . . . . 129

5.31 Schematic for circuit 1 (startup not shown) . . . . . . . . . . . . . . . . . . 131

5.32 Common-Centroid Layout of BJT’s with 1:8 ratio . . . . . . . . . . . . . . 132

xvii

5.33 Possible solutions for biasing the Opamp . . . . . . . . . . . . . . . . . . . 134

5.34 Self-bias for the Opamp in circuit 1 . . . . . . . . . . . . . . . . . . . . . . 135

5.35 Self-bias Loop Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

5.36 Bias of the PMOS cascodes . . . . . . . . . . . . . . . . . . . . . . . . . . 137

5.37 Bias of the NMOS cascodes . . . . . . . . . . . . . . . . . . . . . . . . . . 138

5.38 Bandgap’s BJT’s with dummies . . . . . . . . . . . . . . . . . . . . . . . . 138

5.39 Startup circuit for circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

5.40 Circuit 1: Output voltage versus Temperature . . . . . . . . . . . . . . . . 140

5.41 Circuit 1: Supply Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . 141

5.42 Effect of filter on stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

5.43 Gain and Phase Response for Circuit 1 . . . . . . . . . . . . . . . . . . . . 144

5.44 Circuit 1: Noise PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

5.45 Illustrating chopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

5.46 Chopped noise spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

5.47 Monte-Carlo Simulation results for Offset . . . . . . . . . . . . . . . . . . . 148

5.48 Output bandgap with chopping (unfiltered) . . . . . . . . . . . . . . . . . 149

5.49 Effect of chopping on ΣΔ Output . . . . . . . . . . . . . . . . . . . . . . . 150

5.50 Chopping Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

5.51 Post-chopping filtering options . . . . . . . . . . . . . . . . . . . . . . . . . 152

5.52 Noise on the bandgap (after filter) . . . . . . . . . . . . . . . . . . . . . . . 153

5.53 Digital trimming of RCT (3-bit example) . . . . . . . . . . . . . . . . . . . 155

5.54 Trimming by changing PMOS mirror ratio . . . . . . . . . . . . . . . . . . 155

5.55 Worst Corner DC performance . . . . . . . . . . . . . . . . . . . . . . . . . 157

5.56 Schematic for circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

5.57 Headroom limitation for direct npn connection . . . . . . . . . . . . . . . . 160

5.58 Output Noise versus Opamp tail current . . . . . . . . . . . . . . . . . . . 162

5.59 Output bandgap voltage Vbg2 versus temperature . . . . . . . . . . . . . . . 164

5.60 PSR of Vbg2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

5.61 Noise PSD of Vbg2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

5.62 Higher Order compensated bandgap of [Meijer 82] . . . . . . . . . . . . . . 168

5.63 Current mode approach for Zero-TC . . . . . . . . . . . . . . . . . . . . . 170

xviii

5.64 Conceptual generation of Ivbe lin . . . . . . . . . . . . . . . . . . . . . . . . 171

5.65 Generating Ivbem0 and Ivbem1 . . . . . . . . . . . . . . . . . . . . . . . . . . 172

5.66 Generating Vbem0 and Vbem1 . . . . . . . . . . . . . . . . . . . . . . . . . . 173

5.67 Generating the PTAT compensation current IPT . . . . . . . . . . . . . . . 173

5.68 Schematic for circuit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

5.69 Schematic of PTAT compensation circuit used in circuit 3 . . . . . . . . . 176

5.70 Schematic for Opamp used in circuit 3 . . . . . . . . . . . . . . . . . . . . 177

5.71 DC performance for higher-order compensation versus temperature . . . . 178

5.72 Higher-order and first-order compensation for smallest resistance corner . . 179

5.73 Higher-order and first-order compensation for largest resistance corner . . . 180

5.74 PSR of Circuit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

5.75 Noise PSD of circuit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

A.1 DA-IC model of the MEMS element . . . . . . . . . . . . . . . . . . . . . . 187

A.2 DA-IC model of the second order system (force-to-displacement conversion) 187

B.1 Opamp Behavioral Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

xix

List of Symbols

g Gravitational Acceleration ≈ 9.8 m/s2

a Linear Acceleration, in m/s2

ωn Natural frequency of a 2nd order system, in rad/s

Q Quality Factor of a 2nd order system

F Force, in Newton

αvf Voltage-to-Force conversion factor, in N/V 2

Ω Angular Velocity, in rad/s

ΣΔ Sigma-Delta

fs Sampling Frequency, in Hz

ΔTrf Rise-Fall time mismatch, in seconds

Δt Timing Error, in seconds

Vdac DAC actuation voltage, in Volts

σt RMS Jitter, in seconds

Ts Sampling Time, in seconds

A Activity Factor

Ffb Feedback Force, in Newtons

Vref Reference Voltage, in Volts

Vref ideal Ideal Noiseless Reference Voltage, in Volts

vnref Reference Voltage Noise, in Volts

qn Quantization noise, in Volts

μvref Mean Value of the Reference Voltage, in Volts

σvref Reference Voltage’s Standard Deviation, in Volts

Vz Zener Voltage, in Volts

xx

Vbe Bipolar transistor base-emitter voltage, in Volts

Vgs Gate-Source Voltage of a FET, in Volts

Vp Pinch-Off Voltage of a JFET, in Volts

Idss JFET drain current at zero bias, in Volts

ε Silicon Dielectric Constant, in F/m

ND Donor Concentration, in m−3

NA Acceptor Concentration, in m−3

VT Thermal Voltage, in Volts

Ic BJT Collector Current, in Amperes

Is BJT Saturation Current, in Amperes

Vg0 Band-Gap voltage of Silicon at 0K, in Volts

Tr Reference Temperature, in Kelvins

gm Transconductance, in Siemens

β BJT Common-Emitter Current Gain

α BJT Common-base Current Gain

W MOSFET transistor Width, in meters

L MOSFET transistor Length, in meters

Cox Oxide Capacitance per unit area, in F/m2

Vth Threshold Voltage, in Volts

Veff Overdrive Voltage, in Volts

Cc Compensation Capacitance, in Farads

CL Load Capacitance, in Farads

fchop Chopping Frequency, in Hz

fcorner Noise Corner Frequency, in Hz

fBW Bandwidth, in Hz

Vpp Peak-to-Peak Voltage, in Volts

Vrms Root-Mean-Square Voltage, in Volts

xxi

List of Abbreviations

MEMS Micro Electro Mechanical Systems

DAC Digital to Analog Converter

ADC Analog to Digital Converter

C/V Capacitance to Voltage Converter

V/F Voltage to Force Converter

FFT Fast Fourier Transform

NRZ Non-Return to Zero

RZ Return to Zero

SNR Signal to Noise ratio

SJNR Signal to Jitter Noise ratio

IBN In Band Noise

OSR Over Sampling Ratio

BW Band Width

ENOB Effective Number Of Bits

AM Amplitude Modulation

FET Field Effect Transistor

JFET Junction FET

MOSFET Metal-Oxide-Semiconductor FET

XFET Extra Channel Implant FET

TC Temperature Coefficient

Tempco Temperature Coefficient

CMOS Complementary Metal-Oxide-Semiconductor

PTAT Proportional To Absolute Temperature

xxii

CTAT Complementary To Absolute Temperature

BJT Bipolar Junction Transistor

PSR Power Supply Rejection

CDS Correlated Double Sampling

DEM Dynamic Element Matching

LG Loop Gain

LDO Low Drop-Out regulator

SiGe Silicon-Germanium

xxiii

Chapter 1

Introduction

1.1 Motivation

Inertial sensors, which comprise gyroscopes and accelerometers, are used to measure either

the rotation rate or the acceleration of a body with respect to an inertial frame of reference

[Saukoski 08].

Traditionally, inertial sensors are not MEMS-based. These traditional inertial sensors

have extremely high sensitivity. However, they are very expensive, bulky and power con-

suming, restriciting their use to military and aerospace applications where size and power

consumption are secondary concerns [Jiang 03].

Micromachined (MEMS) inertial sensors have significantly potential cost, size and

weight advantages over traditional sensors. This has resulted in a proliferation of the

applications in which such sensors can be used [Barbour 01]. MEMS accelerometers have

their automotive applications, where they are used to activate safety systems, including air

bags, to implement vehicle stability systems and electronic suspension. They are also used

in biomedical applications for activity monitoring; in numerous consumer applications,

such as active stabilization of picture in camcorders, head-mounted displays and virtual

reality, three-dimensional mouse, and sport equipment; in industrial applications such as

robotics and machine and vibration monitoring; in many other applications, such as track-

ing and monitoring mechanical shock and vibration during transportation and handling of

a variety of equipment and goods; and in several military applications, including impact

1

2 Chapter 1. Introduction

and void detection and safing and arming in missiles and other ordnance. High-sensitivity

accelerometers are crucial components in self-contained navigation and guidance systems,

seismometry for oil exploration and earthquake prediction, and microgravity measurements

and platform stabilization in space. The impact of low-cost, small, high-performance, mi-

cromachined accelerometers in these applications is not just limited to reducing overall size,

cost, and weight. It opens up new market opportunities such as personal navigators for

consumer applications, or it enhances the overall accuracy and performance of the systems

by making formation of large arrays of devices feasible [Yazdi 98].

Micromachined gyroscopes for measuring rate or angle of rotation have also attracted

a lot of attention during the past few years for several applications. They can be used

either as a low-cost miniature companion with micromachined accelerometers to provide

heading information for inertial navigation purposes or in other areas, including automotive

applications for ride stabilization and rollover detection; some consumer electronic applica-

tions, such as video-camera stabilization, virtual reality, and inertial mouse for computers;

robotics applications; and a wide range of military applications. Conventional rotating

wheel as well as precision fiber-optic and ring laser gyroscopes are all too expensive and

too large for use in most emerging applications. Micromachining can shrink the sensor size

by orders of magnitude, reduce the fabrication cost significantly, and allow the electronics

to be integrated on the same silicon chip [Yazdi 98].

In high performance inertial sensing systems, force-balancing (also known as force-

feedback) can be used to raise the linearity, bandwidth and dynamic range of the system.

ΣΔ modulation is particularly attractive for implementing force-feedback because it is sim-

ple, provides a direct digital output and can be easily implemented in high density CMOS

technologies [Lemkin 97]. Achieving high performance in a feedback system translates to

achieving high performance in the system’s feedback path. Hence, this thesis discusses

the non-idealities in the feedback path of ΣΔ force-feedback systems. The reference volt-

age circuitry, which is a crucial component of the feedback electronics, is also designed to

achieve the high performance target.

1.2. Thesis Outline 3

1.2 Thesis Outline

The thesis is organized as follows: chapter 2 presents an overview on MEMS inertial

sensors and inteface circuits, chapter 3 discusses the non-idealities in the feedback path of

ΣΔ force-feedback inertial sensing systems, chapter 4 presents an overview on reference

voltage technologies and, finally, chapter 5 presents circuit analysis and design of high

performance bandgap reference circuits for the feedback DAC of a MEMS acceleration

sensing system.

Chapter 2

Overview on MEMS Inertial Sensors

and Interface Circuits

MEMS inertial sensors include both micromachined accelerometers and micromachined

gyroscopes. Accelerometers are devices used to measure linear acceleration (usually ex-

pressed in g, where g is the gravitational acceleration ≈ 9.8 m/s2) whereas gyroscopes

are devices used for measuring angular rate (usually expressed in ◦/s). In both devices,

the quantities are measured with respect to an inertial frame of reference (i.e. a frame of

reference tied to the moving object).

2.1 MEMS Accelerometers

Several MEMS acceleration sensors are available in the market, and they have been well

incorporated into many types of mass-produced goods, such as automobiles, pedometers

or exercise meters, cell phones, PDAs, gaming consoles, etc. These products require low-

cost and small-sized sensors rather than those providing optimum performance, and most

sensors are being developed to fulfill this demand. On the other hand, there are some

applications that require high resolution and stability in acceleration measurement, e.g.,

earthquake detection, inertial navigation systems, and seismic reflection profiling [Mae-

naka 08].

4

2.1. MEMS Accelerometers 5

2.1.1 Principle of Operation

For the vast majority of accelerometers, the mechanical sensing element consists of a proof

mass that is attached by a mechanical suspension system to a reference frame, as shown

in figure 2.1. Any inertial force due to acceleration will deflect the proof mass according

to Newtons second law. Ideally, such a system can be described mathematically in the

Laplace domain by [Beeby 04]:

Figure 2.1: Mechanical model for an accelerometer [Beeby 04]

x(s)

a(s)=

1

s2 + s. bm

+ km

(2.1)

where x is the displacement of the proof mass from its rest position with respect to a

reference frame, a is the acceleration to be measured, b is the damping coefficient, m is

the mass of the proof mass, k is the mechanical spring constant of the suspension system,

and s is the Laplace operator. This equation can be, more conveniently, expressed in the

form [Beeby 04]:

x(s)

a(s)=

1

s2 + s.ωn

Q+ ω2

n

(2.2)

where ωn =√

km

is the system’s natural resonant frequency, and Q =√

k.mb

is the

system’s quality factor. The mechanical system is, in essence, a second order filter for

6 Chapter 2. Overview on MEMS Inertial Sensors and Interface Circuits

the input acceleration. Since the force F = m.a, the above equations can also be used to

relate the proof mass’s displacement with the applied inertial force by simply scaling the

right-hand-side by 1m

(i.e. x(s)F (s)

= 1m.x(s)a(s)

).

The displacement x can, then, be sensed and measured to give an indication of the

acceleration. Many types of sensing mechanisms have been reported; the most common

of which is capacitive sensing [Yazdi 98]. Many commercial products are based on MEMS

accelerometers with capacitive sensing, such as the famous ADXL series by Analog devices

[Yazdi 98].

Figure 2.2: A MEMS accelerometer structure [Yazdi 98]

Figure 2.2 shows the structure of a MEMS accelerometer that measures in-plane ac-

celerations [Yazdi 98]. A proof mass made of Silicon is suspended by Silicon springs that

are tied to the Silicon substrate. Two sets of electrodes are present that form parallel-

plate capacitors with the proof mass: one set of electrodes is used for sensing and the

second is used for actuation (for use in force-balancing acceleration measurement). An in-

plane acceleration would caused the proof mass to move relative to the electrodes, in effect

changing the parallel plate capacitance between the proof mass and the sense electrodes.

2.2. MEMS Gyroscopes 7

A capacitance-to-voltage converter circuit (C/V) measures this change in capacitance and

convert it to a voltage signal.

2.2 MEMS Gyroscopes

Gyroscopes are widely used in the military and in aviation. They also form a founda-

tion for automotive stability control. New consumer applications demand an order of

magnitude lower cost, promising three orders of magnitude higher volume. These new

applications include: image stabilization for video still cameras and camera phones, GPS

dead reckoning for location-based GPS services (continuation of GPS navigation in periods

when satellites are not visible), gesture-based text writing, dialing, menu navigation, and

gaming [Bryzek 06].

2.2.1 Principle of Operation

Virtually all micromachined gyroscopes rely on a mechanical structure that is driven into

resonance and excites a secondary oscillation in either the same structure or in a second

one, due to the Coriolis force. The amplitude of this secondary oscillation is directly

proportional to the angular rate signal to be measured [Beeby 04].

The Coriolis force is a virtual force that depends on the inertial frame of the observer.

Consider a point moving linearily with a constant velocity on a rotating disk (the inertial

frame of reference) as shown in figure 2.3. A fixed observer on the rotating disk (the

inertial frame of reference) will see a curved trajectory for the moving point. Hence, to

the observer, the moving point is subject to a force causing a change in its velocity 1. This

force is perpendicular to both the linear motion of the moving point and the rotation of

the disk. If the linear velocity is vr, and the applied angular rate is Ω, then the resulting

Coriolis force seen by the observer is given by [Beeby 04]:

�FCoriolis = 2.m.�Ω × �vr (2.3)

1any change in velocity, in either magnitude or direction, implies an applied force


Figure 2.3: The Coriolis Effect [Beeby 04]

where m is the mass of the moving point. As can be seen from equation 2.3, the Coriolis

force is linearily proportional to the applied angular rate Ω and can, thus, be used as a

measure of its magnitude.

In figure 2.4, a lumped model of a simple gyroscope suitable for a micromachined

implementation is shown. The proof mass is excited to oscillate along the x-axis with a

constant amplitude and frequency. Rotation about the z-axis (the applied angular rate to

be measured) couples energy into an oscillation along the y-axis (through Coriolis effect)

whose amplitude is proportional to the rotational velocity. The Coriolis force causes a

change in the position of the proof mass in a manner that can be described by equation

2.2. The displacement can, then, be sensed and measured to give an indication of the

Coriolis force and, hence, give indication of the angular rate. It is to be noted that MEMS

accelerometers and gyros have, basically, the same structure. The only difference is that

single-axis gyros need two degrees-of-freedom, whereas single-axis accelerometers only need

one degree of freedom.

An example of a MEMS gyroscope is shown in [Clark 96] (figure 2.5). Comb drive

actuators are used to excite the structure to oscillate along one in-plane axis (x-axis). Any

angular rate signal about the out-of-plane axis (z-axis) excites a secondary motion along

the other in-plane axis (y-axis). This is, then, sensed by means of capacitive sensing (C/V)

2.3. Interface circuits 9

Figure 2.4: Lumped gyroscope model [Beeby 04]

to give a voltage read-out of the applied angular rate. Other implementations of the same

principle are also present in literature, as well as in industry [Beeby 04].

2.3 Interface circuits

Capacitive sensing is usually used for detection in either accelerometers or gyroscopes. A

capacitance-to-voltage converter (C/V) senses the change in capacitance (caused by the

movement of the proof mass) and converts the capacitance signal into a voltage signal. The

voltage signal can then be applied to an Analog-to-Digital Converter (ADC) to convert

the voltage signal into a digital reading. This arrangement is an open-loop measurement.

Alternatively, the C/V’s output voltage can be passed through an electronic filter and

fed-back to the inertial sensor to resist its movement. This arrangement is known as force-

balancing (or force-feedback). The system’s final output is the feedback force that balances

the original applied force. Feedback can be performed as a pure analog feedback or as a


Figure 2.5: MEMS Gyroscope of [Clark 96]

digital bang-bang type feedback. The digital option allows a ΣΔ loop to be built around

the inertial sensor and, hence, the system’s output will be directly the desired digital read-

out; no extra ADC would be needed. This type of feedback is widely used in capacitive

MEMS accelerometers and, more recently, in MEMS gyroscopes.

2.3.1 Open Loop Architectures

If the electrical output signal of the position measurement interface circuit is directly used

as the output signal of the inertial sensor, this is called an open loop sensor,as conceptu-

ally shown in figure 2.6. Most commercial micromachined accelerometers are open loop

in that they are the most simple devices possible and are thus low cost. The dynamics of

the mechanical sensing element are mainly to determine the characteristics of the sensor.

This can be problematic as the mass and spring constant are usually subject to consid-

erable manufacturing tolerances. Furthermore, second order effects for larger proof mass

deflection introduce nonlinear effects; such as the spring stiffening effect, for larger deflec-

tions. Nevertheless, for most automotive and other low-cost applications the achievable

performance is still acceptable [Beeby 04].


Figure 2.6: A conceptual Open-Loop sensing interface [Beeby 04]

The major advantages of the open-loop sensing architecture are:

1. Smaller electronic interface and, hence, lower cost than closed-loop counterparts

2. Open loop sensing is easier to design. The stability issues, that are inherently present

in any closed loop system, are of no concern in open loop systems.

3. Open loop sensing can operate at lower supply voltages (since no actuation is in-

volved; actuation voltages are usually high) than closed loop.

On the other hand, the open loop sensing architecture suffers from a number of draw-

backs:

1. It has a smaller dynamic range than the closed loop architecture. In open loop

architectures, the proof mass is left to move freely. This means that for large applied

forces, the proof mass gets closer to the fixed structure. Eventually, the proof mass

might collide with the structure which limits the maximum allowable input force.

2. It has lower linearity than the closed loop counterpart. This can be, again, attributed

to the motion of the proof mass. At large displacements, non-linearities in the spring

appear (the spring restoring force is no more a linear function of displacement) caus-

ing a non-linear force-to-displacement relation.


3. It has smaller bandwidth than the closed loop counterparts. This is specially trou-

blesome in vacuum-packaged MEMS components that have very high quality factors.

Such components are often needed to achieve low mechanical losses and, hence, higher

perfromance.

Nevertheless, open loop sensing remains valuable for low-cost, low-end applications

that require low to medium resolutions. For instance, the Analog Devices ADXL series

uses open loop sensing architectures [Beeby 04] and acheieve reasonable dynamic ranges.

2.3.2 Force-Feedback Architectures

The output signal of the position measurement circuit can be used, together with a suitable

controller, to steer an actuation mechanism that forces the proof mass back to its rest

position. The electrical signal proportional to this feedback force provides a measure of

the input signal (either acceleration or angular rate). This is usually referred to as a

closed loop, force-balanced, or force-feedback sensing. The feedback actuation signal is

most commonly implemented by electrostatic forces since for small gap sizes these forces

are relatively large [Beeby 04].

Electrostatic forces are always attractive [Beeby 04]. Hence, changing the direction of

the actuation force cannot be done by changing the polarity of the applied voltage; it has to

be done by having two separate electroded for moving in the two directions. Furthermore,

electrostatic forces are a nonlinear function of the applied voltage. The relation between

the actuation force and the applied actuation voltage can be expressed as:

F = αvf .V2 (2.4)

For comb-drives, the factor αvf is constant. For parallel-plate electrostatic actuation,

however, αvf is a non-linear function of the gap distance [Beeby 04]. Hence, the voltage-

to-force conversion process is highly non-linear imposing difficulties for feedback.

While Analog feedback is possible in MEMS inertial sensors, digital feedback is more

convenient and is gaining more interest in both the literature and the industry [Beeby 04].

Digital feedback places the inertial sensor in a ΣΔ feedback loop, with the inertial sensor

as the first stage of the loop filter and the electrostatic actuator performing the DAC


function [Petkov 05]. A block diagram of such a system is shown in figure 2.7. In this

block diagram, the only filter is the inertial sensor itself (recall from section 2.1.1 that

the mechanical sensor itself is in essence a second order filter). The input acceleration

(applied acceleration in case of accelerometer or Coriolis acceleration in case of a gyroscope)

causes the movement of the proof mass. This, in turn, causes a displacement that is

sensed by the C/V and converted into a voltage signal that is quantized by means of a

comaparator. Based on the comparator decision, the interface applies a feedback voltage

pulse to the sensor, generating electrostatic force, which attracts the proof mass in the

direction opposite its original deflection. The rate at which the comparator generates

decisions is much faster than the dynamics of the mechanical sensor, and therefore the

feedback pulse stream maintains the proof mass approximately neutral [Petkov 05]. The

digital output is an oversampled pulse-density modulated representation of the signal and,

thus, needs electronic filtering (decimation filter) to obtain the desired digital output.

Figure 2.7: Digital ΣΔ force-feedback [Petkov 05]

The second order ΣΔ force-feedback systems shown in figure 2.7 has a limited resolution

[Petkov 05]. For higher resolutions, a higher order ΣΔ modulator is needed [Petkov 05].

This can be done by incorporating additional electronic filters to the loop of figure 2.7.


Examples of such systems exist in [Petkov 05] [Wu 02] [Dong 05].

The major advantages of closed loop sensing are [Boser 96]:

• Improved accuracy as the sensing system becomes less sensitive to the non-idealities

in the forward path (that includes the sensor). The performance burden is laid on

the feedback path (i.e. feedback DAC of the ΣΔ system)instead.

• Increased sensor bandwidth

• Improved dynamic range due to much smaller displacement of the proof mass

• Improved linearity since the limited motion of the proof mass prevents the springs

from exhibiting non-linear behavior

The improved performance of closed-loop ΣΔ force-feedback systems comes, however, at

the cost of increased system complexity. Force-feedback systems require actuation circuitry,

as opposed to open loop systems where no actuation is needed. Furthermore, the use of

higher-order ΣΔ loops requires considerable design effort on the system and circuit levels to

ensure the system stability. Additional design effort and power consumption are needed to

implement the additional electronic filters. All these factors lead to increased complexity,

cost and power consumption. Nevertheless, for high-end applications (such as inertial

sensors for navigation systems) force-feedback is inevitable.

2.4 Conclusion

In this chapter, a brief overview on MEMS inertial sensors and their interfaces was pre-

sented. It is shown that ΣΔ force-feedback systems are ideally suited for high-performance

sensors that require high dynamic ranges, better linearity, larger bandwidths and smaller

sensitivity to the mechanical sensor non-idealities. With ΣΔ force-feedback, the high per-

formance burden is laid on the feedback DAC. Hence, the next chapter is dedicated to the

discussion of the non-idealities in the feedback of ΣΔ force-feedback systems.

Chapter 3

Feedback Non-idealities in ΣΔ

Force-Feedback Systems

In this chapter, the non-idealities in the feedback path of ΣΔ force-feedback systems are

discussed. A ΣΔ MEMS acceleration sensing system is used for the discussion. First,

the acceleration sensing system is briefly introduced. This is followed by a discussion of

the non-idealities of force-feedback systems, with application to the acceleration sensing

system. Based on this discussion, the DAC specs are defined for the accelerometer system

to achieve a maximum SNR of 110dB (corresponding to an ENOB of 18). While the

discussions are performed on the accelerometer system, they remain valid for any MEMS-

based inertial ΣΔ force-feedback system.

3.1 Generic ΣΔ Force-Feedback System

Figure 3.1 shows the generic form of a ΣΔ force-feedback System. The MEMS sensor acts

as the first stage of the ΣΔ loop (recall from section 2.1.1 that the MEMS mechanical

sensor acts as a second order filter). A Capacitance-to-Voltage (C/V) converter follows the

MEMS component to convert the change in capacitance to a voltage signal. Assuming a

discrete-time implementation for the electronic filter, the C/V is followed by a sample and

hold circuit and then a discrete-time electronic filter. To avoid the inherent non-linearity

due to the squaring in the voltage-to-force conversion, multi-bit feedback is avoided. Single-

15

16 Chapter 3. Feedback Non-idealities in ΣΔ Force-Feedback Systems

bit (two-level) feedback is used instead. Using two-level feedback simplifies the feedback

DAC which boils down to a voltage reference and a set of switches. Depending on the

reference voltage technology used, a multiplying Opamp might be needed following the

voltage reference circuit to generate the desired reference voltage Vref .

Figure 3.1: Generic ΣΔ Force-Feedback System

3.2 The acceleration sensing system

The acceleration sensing system used in the following sections is adopted from [El-Shennawy ed].

The MEMS component is a bulk micromachined accelerometer with a quality factor Q ≈ 2,

and a natural frequency fn ≈ 1.8kHz. A ΣΔ loop is built around the MEMS component as

in figure 3.1. To improve the system’s resolution, discrete-time electronic filters are added

to increase the ΣΔ’s order. Two systems are used alternatively to illustrate the discussed

concepts: a 3rd order ΣΔ force-feedback system (i.e. with a 1st order electronic filter) with

3.3. Non-idealities in ΣΔ Force-Feedback systems 17

a sampling frequency fs = 1.6384MHz and a 4th order ΣΔ force-feedback system (i.e.

with a 2nd order electronic filter) with a sampling frequency fs = 409.6kHz. The band-

width of interest is 100Hz (from 1mHz-100Hz), which is suitable for inertial navigation

applications [Beeby 04]. The choice of the sampling frequency and the order of the ΣΔ

system is done to ensure that the quantization noise floor is well below the traget level

(which correponds to an in-band SNR of 110dB), thus allowing the target SNR (of 110dB)

to be achieved.

3.3 Non-idealities in ΣΔ Force-Feedback systems

The application of feedback for MEMS-sensors improves the sensing system performance

as the system becomes less sensitive to the non-idealities of the MEMS component and the

associated forward-path electronics. As in any feedback system, the performance burden

is laid on the feedback path. In the context of ΣΔ Force-Feedback, the feedback element

is the single-bit DAC. Hence, the following sections are dedicated to the discussion of

the feedback DAC non-idealities and their effect on the proposed accelerometer system.

Accordingly, system specs are defined.

3.3.1 Pulse Shape

Two pulse shapes are in common use in ΣΔ modulators, namely: Return-to-Zero (RZ) and

Non-Return-to-Zero (NRZ) pulses [Cherry 00]. NRZ pulses are the easier to implement.

In addition, NRZ pulses allow a higher maximum input signal (and hence dynamic range),

as the pulse extends for the whole clock cycle. However, asymmetry in rise and fall times

can cause signal dependent errors. This can be explained by considering the extreme case

of a finite rise time and a zero fall time [Cherry 00]. As can be seen from figure 3.2(a),

the total area of the feedback pulses depends on their exact sequence [Cherry 00]. Both

sequences in figure 3.2(a) have two ones and one zero but each has a different total area.

In a 1st order modulator, asymmetry of NRZ rise and fall times causes 2nd order non-

linearity [Cherry 00]. In higher order modulators, it results in white noise that may be

larger than the quantization noise [Cherry 00].


(a) NRZ pulse (b) RZ pulse

Figure 3.2: Effect of Rise-Fall time assymetry

The effect of rise and fall time asymmetry on the performance of the system is tested

using Eldo R©. Figure 3.3 shows the system’s output spectrum for different values of rise-

fall time difference (ΔTrf ). The 3rd order system with fs = 1.6834MHz is used in this

simulation. The FFT conditions are: fs = 1.6834MHz, Nfft = 219, window=Hann.

It can be seen from figure 3.3 that the rise-fall time mismatch adds white noise as

expected. Besides, it adds a DC offset to the output stream. For a random bit stream,

the number of rising and falling edges will be equal. Having a mismatch between rise

and fall times will thus cause a residual offset. The Signal to Noise ratio versus ΔTrf is

shown in Figure 3.4 (excluding the effect of the DC offset). To achieve a SNR of 120dB, a

ΔTrf less than 20ps is required. This is a stringent requirement. This problem is usually

solved by using fully-differential DACs or using RZ pulses instead of NRZ ones [Cherry 00]

[Schreier 05]. RZ pulses do not suffer from the asymmetry of rise and fall times because

each pulse has a rising and a falling edge. Hence, the total area of the pulse-stream is not

pattern-dependent. This is illustrated in figure 3.2(b)


Figure 3.3: Effect of rise-fall time assymetry for NRZ case

Figure 3.4: SNR versue ΔTrf for NRZ case


3.3.2 Effect of Clock Jitter in ΣΔ Force-Feedback systems

Clock Jitter is a major source of noise in continuous time ΣΔ modulators. The pro-

posed ΣΔ Force Feedback system is a hybrid continuous time/discrete time system. The

MEMS component is, in effect, a continuous time system. The Capacitance-to-Voltage

converter (C/V) and the electronic filter are discrete-time systems. Due to the presence of

the continuous-time MEMS component, the proposed ΣΔ Force Feedback accelerometer

sensing system will suffer from the same jitter problems present in continuous time ΣΔ

modulators. Hence, the effect of jitter on continuous time ΣΔ modulators will first be

reviewed and then its effect on the proposed system will be evaluated.

3.3.2.1 Effect of Jitter in Continuous time ΣΔ modulators

Figure 3.5: Jitter Entry Points in a continuous-time ΣΔ modulator

Jitter in continuous time ΣΔ modulators causes errors in two points as shown in figure

3.5:

1. At the sampling point (before the quantizer). The time error Δt is converted into

a corresponding voltage error as shown in figure 3.6 . This error, however, is noise

shaped in the same manner as the quantization noise and thus has a limited effect

on the modulator’s noise [Cherry 00] [Ortmanns 06]


2. At the feedback DAC. Since the loop is a continuous time ΣΔ loop, the exact pulse

shape is important. Jitter will cause the area of the feed back pulses to change

randomly, effectively adding random noise to the feedback pulses. This noise is not

noise-shaped and actually sees the same transfer function as the input signal as

shown in figure 3.5. This makes the DAC feedback jitter a major and critical noise

source in high performance / high speed continuous time ΣΔ modulators. The DAC

jitter has a much less pronounced effect in Discrete-time ΣΔ modulators. This is

because in discrete time modulators, only the value of the sample - and not its area

- is important. Since the jitter hits the pulse at the tail of the exponential step

characteristics, it has a limited effect [Cherry 00] [Ortmanns 06] (refer to figure 3.7,

dotted lines represent the jittered clock)

The above statements are true for pulse-width jitter (i.e. jitter that results in random

variations in the width of feedback pulse). It was shown in [Oliaei 98] that pulse-delay jitter

has a minor effect on continuous time ΣΔ modulators. This can be intuitively explained

by the fact that pulse-delay jitter will have no impact on the area of the DAC pulse and

hence no net noise is added.

Figure 3.6: Effect of Clock Jitter at the sampling point

To calculate the noise added by Jitter, consider a RZ continuous-time ΣΔ modulator,

with a pulse-shape as shown in figure 3.8 [Ortmanns 06]:


(a) Continuous Tine (b) Discrete Time

Figure 3.7: Effecr of Jitter on Feedback Pulse

Figure 3.8: a RZ DAC pulse


In the presence of a timing jitter tj , the total area of the feedback pulse (the integrated

voltage over one-period) is:

I =

∫ βTs+tj

αTs

Vdac.dt = Vdac ((β − α)Ts + tj) (3.1)

The error in the integrated value (difference between the integrated value with jitter

and without jitter) is thus:

Error = Vdac ∗ tj (3.2)

If the jitter is assumed to be white Jitter with Gaussian distribution, then the mean of

the integration error will be given by:

Mean = μj =

∞∫−∞

Error ∗ 1√2πe

−t2

2σ2t dt = zero (3.3)

Where σt is the rms jitter in seconds. Hence, the variance of the integration error is:

σ2e =

∞∫−∞

(Error − μj)2 ∗ 1√

2πe

−t2

2σ2t dt = V 2

dac ∗ σ2t (3.4)

Hence, the voltage noise power due to jitter will be given by:

E2j = V 2

dac ∗σ2

t

T 2s

(3.5)

This noise is spread over the fs

2band. Only a fraction of this noise will affect the

in-band region. Hence, the in-band noise power (IBN) can be given by:

IBN =E2

j ∗ AOSR

= V 2dac ∗

σ2t

T 2s

∗ A

OSR(3.6)

Where:

OSR is Over Samplig Ratio = fs

2∗BW

A is Activity Factor ( Number of transitions per clock cycle ); A = 2 for RZ DACs

while A = 0.7 for NRZ DACs [Cherry 00] [Ortmanns 06]


Hence, the Signal to Jitter Noise Ratio (SJNR) can be written as:

SJNR = 10 ∗ Log⎛⎝ V 2

in

2 ∗ V 2dac ∗ σ2

t

T 2s∗ A

OSR

⎞⎠ (3.7)

The following notes can be made on the above equation (equation 3.7):

• The SJNR improves by 20 dB/decade of the rms Jitter. This means that if rms jitter

(σt) decreases 10 times, SJNR improves by 20 dB

• Since OSR = fs

2.BW, equation 3.7 can be rewritten as:

SJNR = 10 ∗ Log(

V 2in

2 ∗ V 2dac ∗ σ2

t ∗ fs.2.BW

)(3.8)

From this equation, it can be observed that SJNR would degrade by 10 dB/decade

of fs for constant BW and similarly would degrade by 10 dB/decade of BW for

constant fs. This agrees with intuition; increasing BW means more noise power is

taken degrading SJNR and increasing fs means that jitter would be a larger fraction

of the clock period adding more noise

3.3.2.2 Decreasing sensitivity to Jitter

Jitter can easily become the dominant noise-source in high speed/performance continuous-

time ΣΔ nodulators. This is often regarded as the major disadvantage of continuous-time

ΣΔ modulators [Cherry 00]. To decrease the sensitivity of continuous-time ΣΔ Modulators

to clock jitter, a number of methods can be used including: using multi-bit feedback DAC

[Ortmanns 06], using linear, quadratic or exponential DAC pulse-shaping [Ortmanns 06],

using sinusoidal DAC pulse shaping [Ortmanns 06] [Luschas 02] ,using switched-C DAC

[van Veldhoven 03] and using FIR DAC [Oliaei 03] [Putter 04] . In the following section,

some of these methods are explained briefly.

3.3.2.2.1 Using Multi-bit Feedback DAC Using a multi-bit Feedback DAC will

result in a multi-level Feedback waveform. In a multi-bit DAC, the difference between two


adjacent pulses will always be very near 1 LSB. Thus jitter will cause a smaller change in

the area of the feedback waveform. Hence, the effect of jitter will be greatly reduced. It is

to be noted, however, that this reduction will only happen for an NRZ feedback pulse. In

the case of a RZ waveform, the reduction will be much less pronounced since the pulse will

always return to zero (Figure 3.9). The improvement in clock jitter will almost be 6 dB

for each bit of the DAC (for NRZ pulses only) [Ortmanns 06]. The DAC used, however,

will be the limiting factor to the system’s linearity (it has to be as linear as the system).

(a) NRZ

(b) RZ

Figure 3.9: Using Multi-Bit DAC

3.3.2.2.2 Using Linear DAC pulse-shaping In this method, the DAC pulse takes

a linearly decaying shape as shown in figure 3.10.This will effectively reduce the area error

caused by jitter since jitter will only cause a change in the area of the pulse-tail; a region


Figure 3.10: a linear DAC pulse-shape

with a small amplitude. Following a similar procedure as that used to calculate the IBN

for a rectangular pulse-shape, it can be shown that the IBN in the case of a linearly shaped

DAC pulse will be [Ortmanns 06]:

IBN =V 2

dac

2 (β − α)2 ∗ σ4t

T 4s

∗ A

OSR(3.9)

The IBN is inversely proportional to the fourth power of the rms jitter σt, instead of

the second power as in the square pulse-shape. Hence, for the same σt the linear pulse

shape will produce smaller noise. Similarly, the SJNR for the linear pulse shape will have

-40dB/decade slope with σt. The use of a linear DAC pulse shape will come, however,

at the cost of a smaller allowable maximum input (since the area of the linear pulse is

half that of the rectangular pulse). To retain the same dynamic range, the linear pulse

amplitude has to be scaled. Moreover, all the ΣΔ coefficients need to be recalculated for

the new pulse-shape [Aboushady 02]

3.3.2.2.3 Using Quadratic DAC pulse-shaping In this method, the DAC pulse

takes a quadratically decaying shape as shown in figure 3.11. The reduced jitter sensitivity

comes from the smaller amplitude of the decaying tail. This reduces jitter sensitivity even

more than the linearly decaying case. It can be shown that the IBN in this case will

be [Ortmanns 06]:


Figure 3.11: a quadratic DAC pulse-shape

IBN =5V 2

dac

3 (β − α)4 ∗ σ6t

T 6s

∗ A

OSR(3.10)

Hence, The IBN is inversely proportional to the sixth power of the rms jitter σt, and the

SJNR has a -60dB/decade slope with σt. The quadratic pulse shape suffers from the same

problems of the linear pulse namely: reduced dynamic range and the need for recalculating

the loop coefficients

It is to be noted that higher order pulse-shaping will result in higher order reduction

in jitter sensitivity as can be seen from equations 3.9 and 3.10. Ultimately, exponential

pulse shaping can provide a jitter-immunity similar to that of discrete-time systems [Ort-

manns 06].

3.3.2.3 Effect of Jitter in the acceleration sensing system

The acceleration sensing system is a mixed continuous-time / discrete-time system (figure

3.12). The accelerometer together with the Capacitance-to-voltage converter represents the

continuous-time part while the integrator and the lead-compensation are implemented in

discrete-time. Even if the Capacitance-to-Voltage converter is implemented as a switched-

capacitor circuit, the accelerometer itself will always operate as a continuous-time system

since it responds to the average value of the feedback pulses (acting as 2nd order low pass


filter). Hence, the system will have the same sensitivity to jitter as a continuous-time ΣΔ

modulator.

Figure 3.12: Block Diagram of the acceleration sensing system

The effect of jitter on the acceleration sensing system can be analyzed as in [Ort-

manns 06]. If a rectangular feedback pulse is assumed, the signal-to-jitter noise ratio

(SJNR) will be similar to equation 3.7. However, this expression needs to be modified to the

specific case of the acceleration sensing system. The signal of interest in the acceleration-

sensing system is the force rather than the voltage. Therefore, the SJNR expression is a

force signal to force noise ratio rather than a voltage signal to voltage noise ratio. The

input force signal can be given as:

F = ms ∗ a (3.11)

Where:

ms is the mass of the MEMS accelerometer proof mass

a is the acceleration

The feedback voltage is converted in the accelerometer into a feedback force. The

relation between the feedback force and the feedback voltage can be given by:

Ffeeback = αvf ∗ (2Vdac)2 (3.12)


Where:

αvf is the Voltage to Force conversion factor

Vdac is the Single-ended DAC feedback voltage

Hence, the force signal to force jitter noise ratio for the acceleration-sensing system is

given by: (basically equation 3.7 with voltage replaced by force)

SJNRacc = 10 ∗ Log⎛⎝ F 2

in/2

F 2feedback ∗ σ2

t

T 2s∗ A

OSR

⎞⎠ (3.13)

This can be further expanded to:

SJNRacc = 10 ∗ Log⎛⎝ (ms ∗ a)2/

2

(2 ∗ αvf ∗ V 2dac)

2 ∗ σ2t

T 2s∗ A

OSR

⎞⎠ (3.14)

3.3.2.4 Jitter Simulations

To test the performance of the acceleration sensing system in presence of clock jitter, the

system’s model is built on Mentor Graphics’ DA-IC R© environment using Eldo’s Macro-

models [Men 07]. The discrete-time part of the system is built using the spice function

”FNZ” [Men 07]. This function performs implicit sample and hold operation, so no sample

and hold block is needed. A snapshot of the system is shown in figure 3.13 (more details

on the model can be found in Appendix A). The RZ DAC is implemented by multiplying

the comparator output by a 50% duty-cycle clock with jitter added to it as shown in figure

3.14. This clock is built using a Matlab code and read into the model using the ”.chrent”

Eldo command [Men 07]. The 3rd order system with fs = 1.683MHz is used in this section.

Simulations of the system in figure 3.13 were performed using Eldo (with fs = 1.683MHz,

Nfft = 219, window=Hann). The clock jitter is modeled as white noise with Gaussian dis-

tribution. The simulation results for 25ps, 100ps and 1ns of rms jitter are shown in Figure

3.15. The achieved Signal to Jitter Noise Ratios are 103dB, 95dB, and 75dB respectively.

It can be seen that the SJNR decreases by 20 dB/decade as predicted by equation 3.14.

Figure 3.16 shows the SJNR versus the rms jitter . The simulated results are verified

against the derived equation (equation 3.14 ). The deviation from the equation increases

at lower jitter values because jitter noise becomes a less dominant noise contributor.


Figure 3.13: Acceleration sensing system in in DA-IC with RZ feedback

Figure 3.14: RZ pulse with jitter


Figure 3.15: Output Spectra for different rms jitter values

Figure 3.16: SJNR vs rms Jitter


The simulation results suggest that the jitter noise might be the dominant noise source

in the sensing system. To achieve the target SNR of 110dB, we choose to set the SJNR

to 120dB (to give margin for other noise sources). Using equation 3.13, the required value

for the rms jitter is σt ≈ 3.5ps which is a tough requirement.

In section 3.3.2.2, a number of methods to decrease the effect of jitter were discussed

for electrical ΣΔ modulators. In the following sections, the use of these methods in the

acceleration sensing system is discussed

3.3.2.4.1 Using Multi-bit Feedback DAC This method decreases the jitter-induced

noise by 6 dB/bit in electrical ΣΔ modulators (with NRZ feedback). However, it imposes

tough requirements on the DAC since the multi-bit DAC has to be as linear as the whole

system. Achieving a high linearity in a multi-bit DAC is hard (as opposed to a single-bit

DAC which is inherently linear). The problem is even worse in the case of the sensing

system due to the non-linear relation between the force and the voltage (equation 3.12 ).

Using a multi-bit DAC in this case would introduce a severe non-linearity into the system.

Thus, this method is not suitable for the acceleration sensing system.

3.3.2.4.2 Using Linear DAC pulse-shaping This method can be used to improve

the jitter performance significantly. Due to the quadratic relation between force and volt-

age, a linearly shaped DAC pulse would give the same performance improvement as a

quadratic shaped DAC pulse in an electrical ΣΔ modulator. For a pulse of the shape shown

in figure 3.10, the expected SJNR expression would be: (adopted from [Ortmanns 06] and

replacing voltage with force)

SJNRacc = 10 ∗ Log⎛⎝ (ms ∗ a)2/

25

3(β−α)4∗ (2 ∗ αvf ∗ V 2

dac)2 ∗ σ6

t

T 6s∗ A

OSR

⎞⎠ (3.15)

As can be seen from equation 3.15, using a linear DAC pulse shape improves the jitter

immunity significantly over the square pulse shape. The SJNR vs σt slope is -60 dB/decade

as opposed to -20 dB/decade for the square pulse shape. However, in order to preserve

the system’s dynamic range, the shaped pulse has to be scaled so that the area under the

shaped force pulse is the same as that of the rectangular case. This can be expressed as:


∫Ffeedbackdt = αvfV

2sqTsq ⇒ Vdac = Vsq ∗

√3 (3.16)

Where:

Vdac is the DAC peak voltage in the case of linearly shaped pulse

Vsq is the DAC voltage for rectangular pulse

This means that using this shaping technique comes at the expense of higher voltage

levels, which might not be available (depending on the used technology). Furthermore, the

actual implementation of this shape will be harder than that of a rectangular pulse.

3.3.2.4.3 Using Quadratic DAC pulse-shaping Although this option will cause a

large relaxation in the jitter requirements, it will be much harder to implement than the

linearly shaped pulse. Besides, the DAC peak voltage will need to be significantly increased

to achieve the same dynamic range.

3.3.2.5 Accumulated Jitter

In the previous sections, the effect of white jitter noise on the performance of ΣΔ force-

feedback systems was discussed. Since the inertial sensing systems are usually narrow-band

(few tens of Hertz to few hundred Hertz), the accumulated (close-in) jitter can be of great

importance. Hence, this section discusses its effect. For this purpose, the 4th order system

with fs = 409.6kHz is used. This is the system that will be used hereafter throughout the

thesis.

To study the effect of close-in jitter, a deterministic jitter signal in the form of a sine

wave with a low frequency (≈ 10 Hz) and amplitude equal to the peak jitter value is

added to the feedback pulse. The edges of the pulse were modulated by the sine wave with

amplitude of 100ps. The output spectrum is the same as the ideal spectrum (with no clock

jitter). This can be intuitively explained as follows: since the modulating sine wave has a

very low frequency compared to the clock (clock frequency = 409.6 KHz, jitter frequency

= 10 Hz), the amount of time Δt by which each edge is jittered will almost be equal (i.e.

if the 1st edge moves by Δt1 and the 2nd edge moves by Δt2, then Δt1 ≈ Δt2). This in

turn means that the pulse width remains almost constant (no pulse-width jitter). The only


pronounced effect is a shift in the pulse position (pulse position jitter). This was shown

in [Oliaei 98] to have negligible effect on signal-to-noise ratio.

Based on this result, more simulations are made to evaluate the performance of the

system in the presence of close-in (low frequency) jitter noise. These are shown in the next

section. For all simulations in this section fs = 409.6kHz, Nfft = 219, and window=Hann.

3.3.2.5.1 Effect of jitter for different jitter frequencies The aim of this simulation

is to explore how low ”low-frequency” jitter is. To do so, a deterministic jitter with

sinusoidal shape is used to modulate the RZ pulse edges. The frequency of the sinusoidal

jitter is swept from 10 Hz to 100kHz (10Hz, 100Hz, 1kHz, 10kHz, 100kHz). The amplitude

of the jitter signal is kept constant at 100ps. The simulation results are shown in figure

3.17. It can be seen that jitter with frequencies up to 10kHz has negligible effect on the

output spectrum. At 100kHz and beyond, the SJNR is degraded to 86dB (as opposed to

the ideal 139dB). This is slightly worse than the SJNR obtained using a 100ps rms white

Gaussian jitter.

Figure 3.17: Spectra for Sinusoidal 100ps rms jitter with different frequencies


3.3.2.5.2 Maximum allowable close-in jitter The aim of this simulation is to de-

termine the maximum amount of allowable close-in jitter that would not degrade the

signal-to-noise ratio. For this purpose, a sinusoidal jitter with 10Hz frequency is used to

modulate the RZ pulses and its amplitude is swept.The simulation result at a jitter am-

plitude of 100ns is shown in figure 3.18. The SJNR is 96dB. Since the SJNR improves by

20dB for each decade of decrease in jitter, the maximum tolerable close-in jitter is 5ns rms

(for a SJNR of 120dB). This is three order of magnitude higher than the white jitter value,

indicating that close-in jitter has a negligible effect on the system performance.

Figure 3.18: Output spectrum for 100ns rms sinusoidal jitter

3.3.2.5.3 Effect of clock with both white and accumulated jitter The aim of

this simulation is to evaluate the effect of a realistic clock source that would have both a

white jitter noise floor and a close-in jitter noise skirt. For this purpose, a clock is built

that has a white jitter noise floor corresponding to white Gaussian noise wit 10ps rms value

and a close-in noise skirt formed by the cumulative summation (running integration) of

the white jitter samples. The spectrum of the clock is shown in figure 3.19


Figure 3.19: Realistic clock with white noise floor and close-in noise skirt

The results are shown in figure 3.20. It can be seen that the close-in jitter has no

noticeable effect on the output spectrum. The noise performance is the same as that of

a clock subject to only white jitter (the clock’s white noise floor). Simulations with 10

times higher noise floor and close-in noise show the same effect; only the white noise floor

determines the system SJNR performance.

3.3.2.6 Conclusions on Jitter

Based on the previous discussion, the following conclusions and decisions can be made

regarding the system’s clock and its jitter:

• While pulse-shaping is advantageous in terms of jitter immunity, it is hard to im-

plement in practice. Moreover, higher voltages for feedback would be needed if the

same dynamic range is to be retained. Hence, the square pulse shape is preferred

• Close-in jitter is of no concern on the narrow-band acceleration sensing system

• White Jitter degrades the output SNR. The relation between rms jitter value and

output Signa-to-Jitter-Noise-Ratio (SJNR) can be given by equation 3.14. Based


Figure 3.20: Output spectra for a realistic clock and a clock with only white jitter

on this equation, the required rms jitter (σt) for a 120dB SJNR is σt ≈ 3.5ps for

fs = 1.6834MHz and σt ≈ 7ps for fs = 409.6kHz


3.3.3 Reference Voltage Noise

The reference voltage generator is a critical block in the feedback path of the force-feedback

system. The value of the reference voltage determines the maximum allowable input ac-

celeration. On the other hand, the noise on the voltage reference can limit the system’s

performance. Hence, it is important to investigate the effect of the reference voltage noise

on the ΣΔ force feedback system’s performance.

3.3.3.1 Reference Voltage multiplication

(a) Actual DAC action

(b) Equivalent Model

Figure 3.21: Illustration of Vref multiplication

As shown in figure 3.1, the feedback force Ffb in a ΣΔ force feedback system is formed

by converting the feedback voltage into force through the voltage-to-force conversion block

(the voltage-to-force conversion is not an actual ”block” but, rather, a physical process).

The ΣΔ’s output is a stream of 1’s and 0’s. If the output is ’1’, a positive force (αvf .V2ref) is

applied in the feedback by applying a voltage equal to +Vref on the positive-force actuator.


If the output is ’0’, a negative force (−αvf .V2ref) is applied in the feedback by applying a

voltage equal to +Vref on the negative-force actuator. This can be regarded as having

an output bit-stream of ”1”s and ”-1”s that is multiplied by the scaled squared reference

voltage (αvf .V2ref). The ”1” - ”-1” bit-stream is a pulse density modulated representation

of the output (it is equal to the input signal + quantization noise). Thus, in effect, the

feedback force is the multiplication of the output signal and the scaled squared reference

voltage (αvf .V2ref) as shown in figure 3.21

3.3.3.2 Effect of Reference Noise on SNR

The effect of reference noise on SNR can be evaluated by finding the SNR in the feedback

force Ffb. This stems from the fact that the feedback force is applied to the input of

the system, in a similar manner to the input force. Thus, if the system’s non-linearity is

ignored, the SNR at the output due to reference noise will be equal to the SNR of the

feedback signal Ffb.

As discussed in the previous section, the feedback force Ffb is the multiplication of the

”1”-”-1” representation of the output bit stream (b (t)) and the scaled squared reference

voltage (αvf .V2ref). It is to be noted, however, that Vref is the summation of the ideal

reference voltage Vref ideal and the reference voltage noise. Hence, Ffb can be expressed as:

Ffb = b (t) .(αvf .V

2ref

)(3.17)

And Vref can be expressed as:

Vref = Vref ideal + vnref (t) (3.18)

Similarly, the bit stream b (t) is the summation of the input signal s (t) and the quan-

tization noise qn (t). Hence:

b (t) = s (t) + qn (t) (3.19)

Hence, the feedback force can be expanded into:


Ffb = αvf . (s (t) + qn (t)) . (Vref ideal + vnref (t))2

= αvf . (s (t) + qn (t)) .(V 2

ref ideal + v2nref (t) + 2.Vref ideal.vnref (t)

)≈ αvf . (s (t) + qn (t)) .

(V 2

ref ideal + 2.Vref ideal.vnref (t)) (3.20)

Where the term v2nref (t) has been ignored. This can further be expanded into:

Ffb = αvf .(s (t) .V 2

ref ideal + 2.Vref ideal.s (t) .vnref (t) + qn (t) .V 2ref ideal + 2.Vref ideal.qn (t) .vnref (t)

)(3.21)

The expression of Ffb in equation 3.21 contains one signal component and three noise

components. The signal component (Ffb sig) is the term αvf .s (t) .V 2ref ideal. The three

noise components are: a quantization noise component (Ffb qn) equal to αvf .qn (t) .V 2ref ideal,

a reference noise component (Ffb refn) equal to αvf .2.Vref ideal.s (t) .vnref (t) and a noise

component that is a multiplication of reference noise and quantization noise (Ffb qnref)

and is equal to αvf .2.Vref ideal.qn (t) .vnref (t). Hence, the force-signal to force-noise ratio in

the feedback will be given by:

SNRfb = 10. log

(F 2

fb sig

F 2fb qn + F 2

fb refn + F 2fb qnref

)(3.22)

Where the various noise components are assumed uncorrelated and hence are added in

an rms sense. Depending on which noise term is dominant, the expression of SNRfb will

change. The different cases will be discussed in the following sections.

3.3.3.2.1 Ffb refn is dominant If the voltage reference noise is the dominant noise

source, then SNRfb can be expressed as:

SNRfb = 10. log(

F 2fb sig

F 2fb refn

)= 10. log

(|s(t)|2.V 4

ref ideal

4.V 2ref ideal.|s(t)|2.|vnref (t)|2

)

= 10. log

(V 2

ref ideal

4.|vnref (t)|2) (3.23)


This is an interesting result. The SNR due to reference voltage noise is essentially

independent on the signal level. This can be explianed by the multiplicative nature of the

reference voltage noise. The equivelant noise at the feedback is the multiplication of the

reference voltage noise and the signal. Hence, noise scales with the signal making the SNR

signal-independent. Note that this result was obtained assuming that the other two noise

sources are non-dominant.

To verify this conclusion, a simulation is made on the accelerometer-sensing system

using Matlab Simulink R©. By design, the in-band quantization noise term Ffb qn is non-

dominant (the ideal SNR is 139 dB). To make sure that the Ffb qnref noise component

(resulting from a multiplication of reference noise and quantization noise) is non-dominant,

noise is added as a determinstic sine wave with low frequency (≈ 10Hz). This ensures

that multiplication of reference noise and quantization noise will not result in out-of-band

quantization noise folding back in-band (as will be shown in next section).

Figure 3.22: Spectra for ideal system and system with dominant reference noise

With a sinusoidal noise voltage (vnoise. sin(ωn.t)), the dominant noise component Ffb refn


can be expressed as:

Ffb refn = αvf .2.Vref ideal.s (t) .vnref (t)

= αvf .2.Vref ideal.s (t) .vnoise. sin (ωn.t)(3.24)

The signal of equation 3.24 is a double-side-band signal modulated on ωn and −ωn.

The amplitude of each side-band is half that of the original signal. Hence, the value of

|vnref (t)|2 will be given by:

|vnref (t)|2 = 2.(vnoise

2

)2

=v2

noise

2(3.25)

Hence, the SNR for a sinusoidal noise source of amplitude vnoise added to the reference

voltage will be given by:

SNRfb = 10. log

(V 2

ref ideal

4. |vnref (t)|2)

= 10. log

(V 2

ref ideal

2.v2noise

)(3.26)

Based on this result, achieving a 120 dB SNR would require vnoise =Vref ideal√

2.10−6. The

simulation was performed with Vref ideal = 5V and vnoise = 5√2μV ≈ 3.5μV . The result is

shown in figure 3.22. The SNR is 120 dB as expected. The sinusoidal noise appears as an

AM signal around the sinusoidal input signal.

3.3.3.2.2 Ffb qnref is dominant If the term Ffb qnref is the dominant noise source,

then SNRfb can be expressed as:

SNRfb = 10. log(

F 2fb sig

F 2fb qnref

)= 10. log

(V 2

ref ideal

4.|vnref (t).qn(t)|2) (3.27)

The Ffb qnref contains the multiplication of the quantization noise and the reference

voltage noise. This term can become a problem if the reference noise is wideband. In

such a case, the high frequency reference noise will be multiplied by the large out-of-band

quantization noise of the ΣΔ causing folding of the out-of-band quantization noise into the

in-band region. This is illustrated in figure 3.23.


Figure 3.23: Illustrating noise-folding

Figure 3.24: Spectra for ideal system and system with wideband ref. noise


To verify this conclusion, white noise is added to Vref ideal instead of the sinusoidal noise

added in the previous section. The total integrated in-band noise is chosen to be equal

to the previous section for the sake of comparison. It is found that the SNR degraded by

almost 20 dB, acheiving an SNR of 101 dB as opposed to the 120 dB of the narrow-band

reference noise case. The simulation result is shown in figure 3.24.

Figure 3.25: Spectra for three different input accelerations

3.3.3.2.3 Ffb qn is dominant The SNRfb in presence of the three noise sources can

be expanded into the form:

SNRfb = 10. log

( ∣∣s (t) .V 2ref ideal

∣∣2|2.Vref ideal.s (t) .vnref (t)|2 +

∣∣qn (t) .V 2ref ideal

∣∣2 + |2.Vref ideal.qn (t) .vnref (t)|2)

(3.28)


For the quantization noise term Ffb qn = qn (t) .V 2ref ideal to be dominant, the other noise

terms have to be non-dominant. This can be done by: decreasing the input signal (which

would decrease the noise added by any term multiplied by s (t)), and making the reference

noise band-limited (to decrease the effect of out-of-band quantization noise folding). By

doing so, the SNR would be dominated by the quantization noise term Ffb qn and will,

thus, be given by:

SNRfb = 10. log

(|s (t)|2|qn (t)|2

)(3.29)

Equation 3.29 shows that SNR with quantization noise as the dominant source is signal-

dependent. This means that for small input signals (i.e. input signals which make quanti-

zation noise dominant), the SNR will depend on the signal level. This is the opposite case

for large input signals where the reference noise will be dominant and hence, SNR will be

signal-independent. The important conclusion to be drawn from this discussion is that the

reference noise doesn’t limit the sensitivity of the system (i.e. doesn’t limit the minimum

detectable signal). This is due to the multiplicative nature of the reference noise which

makes this noise decrease as the input signal decreases.

To verify these conclusions, a simulation is made in which the reference noise is a low-

frequency sinusoidal signal (the same as that used in section 3.3.3.2.1). Three input signals

are used: an acceleration signal of magnitude 3g, a signal of magnitude 0.3g and a signal

of magnitude 0.03g. With a factor of 10 between each two successive signals, the expected

difference in SNR between successive signals is 20 dB. The simulation result is shown in

figure 3.25

The SNR’s for the 3g, the 0.3g and the 0.03g signals are 120dB, 117dB and 99dB

respectively. Although the 3g and the 0.3g signals are 20dB apart, the output SNR due to

both signals only differs by 3dB. This supports the claim of a signal-independent SNR for

large input signals. The 0.03g signal, on the other hand, is separated from the 0.3g signal

by 20 dB. The SNR difference between the two is close to 20 dB. This supports the claim

for a signal-dependent SNR for small input signals.


3.4 Proposed System and DAC specs

The proposed system is the 4th order ΣΔ force-feedback acceleration sensing system with a

sampling clock fs = 409.6kHz and a bandwidth of 100Hz (adopted from [El-Shennawy ed]).

The actuation feedback voltage is 5V. The target SNR in the proposed accelerometer

system is 110dB, corresponding to an ENOB of 18. To achieve this target, we choose to

design each source of noise in the feedback to achieve an SNR of 120dB (to leave a 10dB

margin for other noise sources). Based on this design criteria, the specs for rms jitter σt

and noise can be derived as follows:

• In section 3.3.2.4, the rms white jitter for an SNR of 120dB was calculated to be

equal 3.5ps. This, however, was based on a clock frequency of 1.6834MHz. For the

409.6KHz clock, this value can be recalculated using equation 3.13 to be equal to

7ps. The close-in jitter has negligible effect and is not included in the noise budget

• The total integrated noise in the band 1mHz-100Hz for an SNR of 120dB can be

calculated using equation 3.26 to be equal to 3.5μV (based on an actuation volt-

age value of 5V). Alternatively, using the same equation the ratio vn

Vref idealcan be

calcualted to be equal to 0.7μ (to achieve the 120dB SNR target)

• To avoid the problems arising from the mismatch between the rise and fall time of

the feedback pulse, RZ feedback is used with 50% duty cycle

With the above specs, it is clear that the voltage reference design is challenging. A

very low noise spec is required in the low-frequency range which is plagued by the 1/f

noise. Hence, the rest of this thesis focuses on the design and implementation of the

voltage reference for this system. Chapter 4 presents an overview of the reference voltage

technologies. This is followed by chapter 5 which presents the design and implementation

of the reference voltage circuitry.

Chapter 4

Reference Voltage Generation: An

Overview

This chapter presents an overview on the various technologies used to generate voltage

references. The common definitions of the voltage reference specs are first presented. This

is followed by overview on four reference generation technologies, namely: Zener-based

References, XFET R© references, floating-gate references and Bandgap references. Both

industrial implementations and literature implementations are presented.

4.1 Definitions

Various parameters are used to characterize voltage references. In the following sections,

three basic parameters are defined.

4.1.1 Initial Accuracy

Initial Accuracy is defined as the output voltage tolerance of a reference after the device is

turned on and warmed up [Tex 99]. The initial accuracy of a reference quantifies the effect

of random process variations, mismatch, and package stresses on the dc accuracy of the

reference voltage. While the systematic component of these error sources can be accounted

for through careful calibration, the random component affects each sample uniquely and

47

48 Chapter 4. Reference Voltage Generation: An Overview

initial accuracy can therefore only be specified after statistical analysis of a large sample

size.

A more formal definition of Initial Accuracy is the ratio of the 3σ variation (3.σvref )

of a reference, over a large number of samples, to the mean value (μvref ), and is given

by [Gupta 07]:

InitialAccuracy = ±3σvref

μvref

(4.1)

4.1.2 Temperature Coefficient

The temperature coefficient is defined as the fractional variation in the reference voltage per

degree Celsius. It is commonly expressed in parts per million per degree Celsius (ppm/◦C).

The box method is the most-commonly used method for measuring the temeprature coeffi-

cient. Using the box method, the temperature coefficient (TC) can be expressed as [Tex 99]:

(refer to figure 4.1)

TC =Vmax − Vmin

Vnom (Tmax − Tmin)∗106 ppm/◦C (4.2)

Figure 4.1: Box method definition for temperature coefficient

4.2. Reference Voltage Technologies 49

4.1.3 Long-term Drift

Long-term Drift is defined as the slow change in reference voltage at constant temperature

after a long time. It is usually expressed in ppm/1000hr. It is to be noted that the drift

is not linear with time, but rather logarithmic. An alternative measurement unit is, thus,

ppm/√

1000hr. This means that if the reference voltage drifts X ppm in the 1st 1000 hours,

it would drift by X.√

2 ppm in the 1st 2000 hours; the drift in the 2nd 1000 hours is, thus,

smaller than in the 1st as illustrated in figure 4.2 [Tex 99]

Figure 4.2: Illustration of long-term drift

4.2 Reference Voltage Technologies

In this section, an overview is presented on the different reference voltage technologies.

Both industrial designs and designs in literature are overviewed. Modern voltage references

use four major technologies [Tex 99] [Xic 04]: buried-Zener based references, XFET-based

references, floating gate references and bandgap references. In the following sections, these

technologies are briefly reviewed.


4.2.1 Zener-Based References

Zener voltage references are based on Zener diodes. Buried Zener-diodes rely on Avalanche-

breakdown mechanism to obtain a stable voltage reference across both temperature and

time (and not on Zener-breakdown as their name suggests) [Lin 99]. The I-V characteristics

of such a diode are shown in figure 4.3. As can be seen from figure 4.3, reverse biasing a

zener-diode by a large-enough current source will cause its output voltage to be the constant

value Vz. The temperature coefficient of Vz is positive (i.e. Vz is proportional to absolute

temperature, or PTAT). To obtain a reference that is constant with temperature, a base-

emitter voltage Vbe can be added to Vz, since Vbe has a negative temperature coefficient

(i.e. Vbe is complementary to absolute temperature, or CTAT) [Lin 99].

Figure 4.3: I-V characteristics of a Zener-diode

Two types of Zener-diodes are available: surface-Zeners and buried-Zeners. The p-n

junction that constitutes a surface-zener is a surface p-n junction (i.e. formed by lateral

conncection of p and n type Silicon regions) as shown in figure 4.4(a) [AMI 05]. This makes

them susceptible to surface contamination making them noisy devices with unpredictable

drift. Surface Zeners are widely used in integrated circuits for ESD-protection, EPROMs

and as Zap-devices for trimming or memory applications [Lin 99]. Buried Zeners, on the


(a) Surface Zener

(b) Buried Zener

Figure 4.4: Zener Diode structures [AMI 05]


other hand, are formed by buried p-n junctions i.e. p-n junctions below the surface of the

substrate, formed by vertical stacking of p and n regions as shown in figure 4.4(b) [AMI 05].

Figure 4.5: The LM199 Zener reference [Nat 05a]

4.2.1.1 Review of Zener-Based References

The circuit shown in figure 4.5 is the core of the National Semiconductor LM199 Zener-

based references. This reference is a shunt-type reference (i.e. a two-terminal reference).

The reference voltage is the sum of a Zener voltage (Vz) and a bipolar transistor’s base-

emitter voltage Vbe to compensate for the PTAT behavior of Vz. Furthermore, the inte-

grated circuit is equipped with a temperature stabilizer (i.e. heating circuit, not shown)

to minimize the temperature variations of the Zener. It achieves a long-term drift of

20ppm/1000hr and a maximum temperature drift of 1ppm/◦C [Nat 05a].

The circuit shown in figure 4.6 is reported in [Laude 80]. It is a Zener-based reference

that uses a base-emitter voltage for 1st order compensation of the PTAT Zener voltage

Vz. The circuit employs thermal-feedback to temperature-stabilize the Zener-diode; the


Zener voltage Vz is compared with the internally generated reference voltage and the chip

temperature is adjusted accordingly (by controlling the current of a power-BJT). The

circuit achieves a very low temperature coefficient of 0.3ppm/◦C but at the cost of a hefty

power consumption (1W). The extrapolated long-term drift is 300ppm/1000hr.

Figure 4.6: Temperature-regulated Zener reference [Laude 80]

Table 4.1 shows the important specs of some of the commercially available Zener based

references. It can be seen that they are capable of achieving low temperature coefficients

and low long-term drift. The major drawback is their high power consumption (due to the

large bias current needed to reverse-bias the Zener diode), as well as their incompatibility

with modern CMOS processes; buried Zeners are found in only few proprietary technologies

and surface-zeners are noisy and have unpredictable drifts.


Component Tempco (ppm/◦C) drift (ppm/1khr) Noise 0.1Hz-10Hz (μVpp)

Maxim6325 [Max 01] 1 30 3

AD586 [Ana 05] 5 15 4

LM169 [Nat 94] 3 6 4

LM199 [Nat 05a] 0.5 20 N/A

VRE405 [Tha 00a] 0.6 6 3

Table 4.1: Key Specs of commercial Zener references

4.2.2 XFET references

XFETTM

is a proprietary technology patented by Analog Devices Incorporation [Bow-

ers 98]. This technology exploits the JFET characteristics to generate a low-noise, low

temperature coefficient voltage reference. To explain its principle of operation, consider

figure 4.7 which shows both a cross-section of the JFET (figure 4.7(a)) and the circuit used

to generate the XFET reference (figure 4.7(b)). The gate-to-source voltage of a JFET

transistor can be given by [Bowers 98]:

Vgs = Vp − Vp

√I

Idss

(4.3)

Where:

Vp is the JFET’s pinch-off voltage

I is the JFET drain current

Idss is the JFET’s drain current at zero bias

Hence, the difference in the gate-to-source voltage of the JFET transistors J1 and J2

can be given by:

ΔVgs = ΔVp −(Vp1

√I1Idss1

− Vp2

√I2Idss2

)(4.4)

Where I1 and I2 are the bias currents of transistors J1 and J2 respectively. The ratioI

Idsscan be given by:


I

Idss=

IWLβV 2

p

(4.5)

Where β is a process constant. By adjusting the current densities of J1 and J2 to be

equal (i.e. I1W1/L1

= I2W2/L2

) the gate-to-source voltage difference reduces to:

ΔVgs = ΔVp (4.6)

The pinch-off voltage of a JFET transistor can be given by:

Vp =a2qND

2ε

(1 +

NA

ND

)− ψo (4.7)

Where:

a is half the channel width

ε is Silicon’s dielectric constant

ND is the donor concentration in the N-well

NA is the channel’s acceptor concentration

ψo is the gate-channel built-in potential =kTq

ln(

NAND

n2i

)Hence, ΔVp reduces to:

ΔVp = a2qNd1

2ε

(1 + NA1

ND

)− a2qNd2

2ε

(1 + NA2

ND

)− Δψo

= a2qNd1

2ε

(1 + NA1

ND

)− a2qNd2

2ε

(1 + NA2

ND

)− kT

qln(

NA1

NA2

) (4.8)

The first two terms of the above equation (equation 4.8) have very weak temperature

dependence. The last term, however, is a linear CTAT term that can be controlled by

adjusting the implant ratio NA1

NA2. Hence, one of the two matched JFETs J1 and J2 is given

an extra channel implant (and is, hence, dubbed XFET). Precision control of this extra

implant allows precision control of the corresponding CTAT slope.

Refering to figure 4.7(b), the output voltage of the XFET reference generation circuit

can be given by:

Vo = ΔVp

(R1 +R2 +R3

R1

)+ IPTAT .R3 (4.9)


(a) p-channel JFET cross-section

(b) XFET reference circuit [Tex 99]

Figure 4.7: The XFETTM

reference



ADR425 [Ana 02] 3 50 3.4

Table 4.2: Key Specs of the XFET reference ADR425

The PTAT current component is used to compensate for the CTAT characteristics of

the ΔVp term, allowing for lower variation across temperature. The advantage of the XFET

approach over the bandgap approach is that the CTAT slope in the XFET is lower and

more linear than the CTAT slope of the bipolar’s Vbe. This allows for smaller variation

across temperature as well as lower noise. Furthermore, the CTAT slope is obtained by

matched components (as opposed to the absolute Vbe used in bandgap) which allows for

better long-term drift. Table 4.2 summarizes the key specs of the commercially available

XFET reference ADR425 [Ana 02].

4.2.3 Floating-Gate References

4.2.3.1 Introduction to Floating-Gate transistors

Floating gate technology is the technology used in flash memories. A floating gate is a

polysilicon gate surrounded by SiO2. Charge on the floating gate is stored permanently,

providing a long-term memory, because it is completely surrounded by a high-quality in-

sulator [Hasler 99]. To prevent charge leakage, no resistive path should exist between the

storing node and either supplies; the storage node is, thus, floating. Figure 4.8 shows a

floating-gate transistor [Guillermo 07]. There is no direct access to its gate but, rather, the

gate is accessed through the capacitors Ctun and Cin. Furthermore, the floating gate is usu-

ally formed by a single continuous poly line to avoid any contacts or diffusions [Ahuja 05].

In normal operation, the input to the floating gate transistor is applied through the capac-

itor Ctun. If the total charge on the floating-gate node is Q, and the total capacitance of

the floating-gate node is CT then the floating gate voltage Vfg in the presence of an input

voltage Vg can be given by [Guillermo 07]:

Vfg = VgCin

CT+

Q

CT(4.10)


The stored charge on the floating gate, in effect, changes the threshold voltage of the

transistor Mfg. Hence, Mfg can be used as a programmable transistor as well as an

analog memory cell. Floating gates are used in a wide-range of applications such as rail-

to-rail input Opamps [Ramrez-Angulo 01], in analog trimming [Jackson 01], and in voltage

references [Guillermo 07] [Ozalevli 06] [Ahuja 05].

Figure 4.8: A floating-gate transistor [Guillermo 07]

4.2.3.2 Programming Techniques for Floating Gate transistors

Two techniques are used for programming floating gates, namely: Fowler-Nordheim tunnel-

ing [Guillermo 07] [Ahuja 05] and Hot-Carrier Injection (HCI) [Guillermo 07] [Ozalevli 06].

In [Guillermo 07] and [Ozalevli 06], Fowler-Nordheim tunneling is used for coarse pro-

gramming and HCI is used for fine tuning. In [Ahuja 05], however, only Fowler-Nordheim

tunneling is used for programming. Tunneling is performed through the tunneling capaci-

tor Ctun, whereas HCI is performed through the floating gate transistor Mfg as shown in

figure 4.9

Fowler-Nordheim tunneling is the process by which electrons can tunnel through a

dielectric material. By applying a high positive voltage Vtun to the capacitor Ctun, electrons

tunnel from the floating gate to the voltage source Vtun effectively increasing the floating-

gate voltage Vfg [Guillermo 07] [Ahuja 05]. Fowler-Nordheim tunneling can also be used

to decrease the floating-gate voltage if a large negative voltage Vtun is used [Ahuja 05].


Hot carrier injection occurs in MOS transistors at high drain-to-source voltages whereby

energetic carriers cause generation of electron-hole pairs by impact ionozation near the

drain. If the control potential Vg is positive, some of the energitic hot electrons can move

into the floating gate effectively lowering its potential [Guillermo 07].

Figure 4.9: Programming the floating gate transistor

4.2.3.3 Review of floating-gate references

A number of voltage references based on floating gates are available in literature [Guillermo 07]

[Cook 04] [Ahuja 05]. These designs exploit the charge retention capabilities of floating

gates to implement a voltage reference. The designs in [Guillermo 07] represent volt-

ages that are referenced to the supply and, hence, will not be discussed. The designs

in [Cook 04] and [Ahuja 05] are voltage reference referenced to ground and will be dis-

cussed below.

The design in [Cook 04] is shown in figure 4.10. The block diagram, shown in figure

4.10(a), consists of a floating-gate followed by a buffer. The floating gate transistor will

constitute one of the input-pair transistors of the buffer. The buffer is composed of two

stages: a transconductance stage followed by a transimpedance stage. This arrangement

is used to reduce the parasitic coupling from the drain and source of the floating gate

transistor to the floating gate. The transimpedance stage is simply the input pair stage,

having a high impedance output. This is followed by a transimpedance stage (TIA) which

has a low-input impedance. Hence, the drain of the floating gate transistor is kept at

low-impedance, reducing the parasitic coupling from the drain to the floating gate, as can

be seen in figure 4.10(b). This circuit achieves a temperature coefficient of 54.6ppm/◦C.


Since the floating gate charge remains constant after programming (versus time and tem-

perature), the temperature coefficient of this reference is dominated by the capacitor’s

temperature coefficient [Ahuja 05].

(a) Block diagram (b) Circuit Implementation

Figure 4.10: Floating Gate reference in [Cook 04]

The design in [Ahuja 05] uses a differential dual floating gate architecture (shown

in figure 4.11) to overcome the temperature coefficient limitation of the previous design

in [Cook 04]. Two capacitors are used instead of a single capacitor: capacitor CS carries

a common mode voltage VCM and capacitor CF carries a voltage equal to VCM-VREF

(where VREF is the desired reference voltage value). When CF is connected in closed loop

(with initial value VCM-VREF), the output voltage will be equal to VREF. While the

use of two capacitors didn’t add an advantage in terms of the reference voltage value, it

represents a great improvement to the temperature variation problem. The capacitors CS

and CF are poly capacitors whose temperature coefficients depend on the bias volatge. It


is shown in [Ahuja 05] that the temperature coefficient of VREF (TCV REF ) is given by:

TCV REF ≈ −αcf + (αcf − αcs) ∗ V CM

VREF(4.11)

Where αcf and αcs are the temperature coefficients of the poly capacitors CF and CS,

respectively.

Hence, for a given reference voltage VREF, there exists a certain value for VCM that

achieves the minimum possible TCV REF

Figure 4.11: Differential Dual Floating Gate [Ahuja 05]

Programming of this reference is done by the use of Fowler-Nordheim tunneling only.

Two loops are used for programming. The loop involving CMAmp is used for setting the

VCM value on the capacitor CS, and the loop invlolving REFAmp is used for setting the

voltage VREF-VCM on the capacitor CF as shown in figure 4.12.

To program VCM, the voltage VPP (a high voltage generated from an on-chip voltage

charge pump) is applied. A current source of 10nA is connected to the gates of the source

followers in the CMAmp loop. Hence, when the tunnel diodes (i.e. the programming

capacitors) are off the voltage on the common source transistors’ gates will rise gradually

(since they constitute capacitors charges by a constant current source). When this voltage

is high enough, tunneling occurs and the loop is closed. Hence, the negative terminal of the


Opamp will hold the same potential VCM as its positive terminal by virtue of feedback.

Due to symmetry, the same voltage VCM will be applied on the capacitor CS.

Figure 4.12: Programming Loops for Floating-Gate reference in [Ahuja 05]

To program VCM-VREF, a voltage VREF is applied to the capacitor CF (whose other

terminal is connected to the Opamp’s negative terminal). By using the same technique

as that used for VCM, the loop involving REFAmp is closed. Hence, REFAmp’s negative

terminal is held at VCM by virtue of feedback, forcing the voltage across CF to be VCM-

VREF.

If the voltage VCM needs to be decreased, tunneling can be enabled in the reverse

direction by means of large negative voltage VNN that is also generated by an on-chip

charge pump.

In normal operation, the high voltage supplies VPP and VNN are turned off and the

capacitor CF is connected across the REFAmp Opamp, giving an output voltage VREF

that is temperature compensated.

This simple and elegant design is the core of the commercial product X60008A-50

[Xic 04]. The key specs of this product are summarized in table 4.3. It is to be noted that

these specs are achieved at the very low power consumption of 800nA (maximum).



X60008A-50 [Xic 04] 1 10 30

Table 4.3: Key Specs of X60008A-50

4.2.4 Bandgap References

4.2.4.1 Introduction to Bandgap references

Bandgap references are, by far, the most popular references in integrated circuits. The

term ”Bandgap” referes to the energy band gap of Silicon, which is typically around 1.2V.

A conceptual implementation of a bandgap reference is shown in figure 4.13 [Holman 94].

The base-emitter voltage of a bipolar transistor is CTAT (Complementary To Absolute

Temperature), and its value at absolute Zero (i.e. Zero Kelvin) is almost equal to the

band-gap voltage of silicon Vg0. By adding a scaled version of the thermal voltage VT = k.Tq

(which is PTAT i.e. Proportional To Absolute Temperature) to Vbe, a constant voltage can

be obtained that is independent on temperature (to a 1st order) and almost equal to Vg0.

Vbe has a slope of -1.5mV - -2mV /K, whereas VT has a slope of 86μV/K. Hence, the scaling

factor K (in figure 4.13) should be around 17 to 23 [Razavi 01].

Figure 4.13: Conceptual Bandgap Reference [Holman 94]


Figure 4.14: Generating PTAT voltage

Generating a PTAT voltage can be easily done, as shown conceptually in figure 4.14,

by taking the difference between the base-emitter voltages (ΔVbe) of two matched bipolar

transistors operating at different current densities [Razavi 01]. The collector current Ic of

a bipolar transistor is given by:

Ic = Is.eVbeVT (4.12)

Where Is is the transistor’s saturation current.

Hence, ΔVbe can be expressed as:

ΔVbe = VT ln(

I1Is1

)− VT ln

(I2Is2

)= VT ln

(I1I2. Is2

Is1

)= VT ln

(I1I2.N) (4.13)

By adjusting the area ratio N and the current ratio I1I2

, the slope of the PTAT voltage

can be adjusted. The factor ln(N. I1

I2

)is, however, not enough to cancel the CTAT slope

of Vbe (since ln is a weak function of its argument); an extra gain factor is needed.


4.2.4.2 Review of Bandgap References

Bandgap technology is widely used in both industry and literature. In this section, a brief

overview is given of literature and some of the industrial implementations.

A widely used bandgap architecture is the Brokaw bandgap, shown in figure 4.15

[Brokaw 74]. The negative feedback loop formed by the Opamp forces the two Opamp

terminals to have equal voltages. Hence, both BJT’s will carry equal currents (since the

two bias resistors are equal and have equal voltage drops across them). The voltage drop

across the resistor R2 is the PTAT voltage ΔVbe. Thus, the current in Q1 (I1) and the

current in Q2 (I2) will be equal and given by:

I1 = I2 = I = VT . ln(N) (4.14)

Figure 4.15: The Brokaw bandgap reference [Brokaw 74]

Where N is the ratio of the areas of Q1 and Q2. The current in resistor R1 will be equal

to 2.I, and hence the output voltage can be given by:

Vout = Vbe1 + 2.R1

R2

.VT . ln (N) (4.15)


The factor R1

R2is used to adjust the slope of the PTAT voltage to be equal to that

of the CTAT Vbe voltage. This architecture has the advantage of having a low output

impedance due to the shunt feedback at the output. This allows its output to be used

directly without the need for extra buffering. A variation of this architecture is used in the

commercial voltage reference AD580 [Pease 90], allowing the generation of output voltages

that are scaled versions of the bandgap voltage. The modified architecture is shown in

figure 4.16

Figure 4.16: The AD580 commercial reference [Pease 90]

Another popular industrial design is that of the LM4040 product [Nat 05b]. It is a

shunt-type reference, as shown in figure 4.17. Shunt-shunt feedback is used since the input

to the circuit is current (rather than voltage) and the circuit’s output is the reference

voltage. An elegant feature of this circuit is the way the ΔVbe is generated. An Opamp is

used whose input pair transistors are not equal in area, but rather have the area ratio of 1:N.

Both transistors are biased by equal currents. The inputs of these transistors are connected

across a resistor and, hence, the current in this resistor would be a PTAT current ΔVbe

R.

The advantage of this approach is that the ΔVbe generation transistors are simultaneously


used as the input stage of an Opamp that provides extra gain for the feedback loop.

Figure 4.17: The LM4040 commercial reference [Nat 05b]

4.2.4.2.1 Differential Bandgap references A differential implementation of the bandgap

reference is shown in figure 4.18(c) [Ferro 89]. The circuit is made-up by merging a positive

bandgap reference (i.e. one that is referenced to ground as in figure 4.18(a)) and a negative

bandgap reference (i.e. one that is referenced to Vdd as in figure 4.18(b)). The differential

output voltage is equal to the bandgap voltage. This can be explained by refering to figure

4.18(c); the voltage of the positive terminal Vr+ relative to that of the negative terminal

Vr− can be easily shown to be given by:

Vout = Vbe1 +R3

R1.VT . ln (10) (4.16)

Hence the differential voltage Vr is equal to the bandgap voltage. Another differential

implementation of the bandgap reference is shown in figure 4.19 [Nicollini 91]. This cir-


(a) Positive Ref. (b) Negative Ref. (c) Differntial Ref.

Figure 4.18: Differential Bandgap Reference [Ferro 89]

cuit uses a switched-capacitor technique to implement the differntial bandgap. Besides,

Correlated-Double-Sampling (CDS) is used to remove the Opamp input offset voltage and

flicker noise. In one phase (φ1) the offset is stored and in the next phase (φ2) the offset

is subtracted and the offset-free output is evaluated. The inputs to the switched-capacitor

circuit are the Vbe voltages of two matched BJT’s with differnt current densisties. These

Vbe’s are obtained by passing equal currents through two BJT’s that have an area ratio of

1:A.


(a) Offset Storage Phase φ1

(b) Amplification Phase φ2

Figure 4.19: Switched Capacitor Differential Bandgap Reference [Nicollini 91]


4.2.4.2.2 Low-Voltage Bandgap References The circuits discussed so far gener-

ate a reference equal to the bandgap voltage, which is around 1.2V. In state-of-the-art

CMOS technologies, the supply voltages may be as low as 1.2V which makes the previ-

ously discussed circuits unsuitable for this purpose. A circuit which is specially developed

for such low-voltage designs is shown in figure 4.20 [Banba 99]. This low voltage operation

is achieved by resorting to a current-mode approach for generating the bandgap voltage.

Assume the currents I1, I2 and I3 in figure 4.20 are equal , and each of them equal to I.

Assume also that the resistors R1 and R2 are equal, and each is equal to R. Then, I can

be expressed as:

I =Vf1

R+dVf

R3

(4.17)

If the diodes are implemented by diode-connected pnp substrate transistors, then Vf1 =

Vbe1 and dVf = ΔVbe = VT .ln(N). The output voltage is simply the current I multiplied

by the output resistance R4. Hence, the generated reference voltage Vref can be given as:

V ref = I.R4 = R4R

(Vf1 + R

R3dVf

)= R4

R

(Vbe1 + R

R3ΔVbe

)= R4

R

(Vbe1 + R

R3.VT . ln(N)

) (4.18)

The term in the parantheses is the conventional 1.2V bandgap reference. It can be seen

in equation 4.18 that the conventional 1.2V bandgap voltage is scaled by the factor RR3

,

allowing for sub-1.2V references and eliminating the supply limitation.

4.2.4.2.3 Higher-Order Compensated Bandgap References The bandgap cir-

cuits presented so far are 1st order compensated i.e. they cancel only the linear temper-

ature dependence of the Vbe voltage. Vbe has higher-order non-linear terms that cause a

residual temperature variance. For this purpose, higher-order temperature compensation

techniques can be used. The full-fledged Vbe equation is given by:

Vbe (T ) =

(Vg0 + (η −m) .

k.Tr

q

)− λ.T + (η −m) .

k

q.

(T − Tr − T. ln

(T

Tr

))(4.19)


Figure 4.20: Low Voltage Bandgap Reference [Banba 99]

Where:

Vg0 is the extrapolated bandgap voltage of Silicon at 0 Kelvin

λ is a constant that represents the slope of the linear component of Vbe (T )

Tr is the reference temperature

η is a process constant

m is the temperature exponent of the collector current Ic1

The term(Vg0 + (η −m) .k.Tr

q

)in the above equation is the constant term of Vbe, the

term −λ.T is the linear CTAT term and the term (η −m) .kq.(T − Tr − T. ln

(TTr

))is the

non-linear term. Higher order compensation schemes try to cancel, or minimize, this term.

For example, the circuit in [Song 83] tries to decrease the higher order term by adding

a PTAT 2 voltage to Vbe (i.e. a voltage that is proportinal to T 2). This is made possible

by generating ΔVbe from two transistors: one biased by the sum of a PTAT current and a

constant current and the other biased by the difference between a constant current and a

PTAT current. The Taylor expansion of such a ΔVbe contains PTAT and PTAT 2 terms.

The circuit in [Gunawan 93] genertaes a non-linear correction current INL which results

from the ΔVbe of two bipolars: one biased by a PTAT current IPTAT , and the other biased

by the sum of a constant current and INL. The term INL can be adjusted, under specific

conditions, to minimize the non-linear Vbe term. The output voltage is formed by dumping

INL, Ivbe and IPTAT into a reference resistor Rref (Ivbe is a CTAT current proportional to

1It is assumed that Ic ∝ T m. For a PTAT Ic, m=1. For a constant Ic, m=0



Max6133 [Max 03] 3 40 40

AD584 [Ana 01] 15 25 50

LM4140 [Nat 00] 3 60 2.2

Table 4.4: Key Specs of commercial bandgap references

Vbe and IPTAT is the corresponding 1st order compensation current).

[Lee 94] exploits the negative exponential characteristics of the BJT’s β (T ) to generate

a non-linear voltage term that minimizes the Vbe non-linearity.

[Leung 03] employs a temperature-dependent resistor ratio to decrease the Vbe non-

linearity. This temperature-dependent ratio is obtained by using two different type of

resistors with different temperature coefficients.

[Rincon-Mora 98] uses a piece-wise linear approach for the compensation process. At

the lower half of the temperature range, the conventional 1st order compensation is used

to decrease the temperature-variation of the bandgap voltage. In the upper half of the

temperature range, a non-linear compensation current (which is almost equal to zero in

the lower-half of temperature) is added, decreasing the temperature variation in the upper

half of the temperature range.

4.2.4.3 Performance of Commercial bandgap references

For the purpose of comparison with the other reference voltage technologies, table 4.4 shows

the key performance metrics of some of the commercially available bandgap reference chips.

Only commercial designs are included for a fair comparison with the other technologies (and

also because long-term drift is rarely reported in literature).

4.2.5 Conclusions

In this chapter, four different reference voltage technologies were overviewd namely: Zener-

Based References, XFET R© references, Floating-gate references and Bandgap references.

The discussions in this chapter are the basis for the next chapter which presents the

reference voltage implementation.

Chapter 5

Circuit Implementation

This chapter presents the design and the implementation of the reference voltage circuit

for the ΣΔ force-feedback acceleration sensing system proposed in section 3.4. The chapter

starts by discussing which technology to use for reference voltage generation, followed by a

discussion of the required specs. Then a detailed analysis is presented for the chosen circuit

topology. Finally, three circuit designs are presented to achieve the target specs. The

designs are implemented on austriamicrosystems AMS 0.35μm SiGe BiCMOS technology.

5.1 Choosing Reference Voltage Technology

In section 4.2, various reference voltage generation technologies were reviewed. The fol-

lowing conclusions can be drawn from this review:

• Zener-Based references are the best in terms of long-term drift (on the commercial

scale). They have low temperature drifts as well. While these characterisitics make

them favorable, Zener-Based references have many drawbacks. They generally have

high power consumption and require supply voltages of 5V or more [Tha 00b] [Lin 95].

Besides, Buried-Zeners - which are needed for high performance Zener references

[Tex 99] - are not a standard option in current CMOS technologies. Hence, Zener-

Based references are inherently imcompatible with modern CMOS technologies.

• XFETTMprovides low voltage operation together with low temperature and long-term

73

74 Chapter 5. Circuit Implementation

drifts. It can achieve a long term drift comparable to that of Zener-Based references.

XFETTM technology is, however, a properiatary technology that is patented by Ana-

log Devices Incorporation [Bowers 98]. This technology is, thus, not a standard

option in CMOS technologies.

• Floating-Gate references offer interesting possibilities. A recent publication [Ahuja 05]

shows a high-performance implementation of a floating-gate voltage reference that

achieves superior performance (a temperature coefficient of 1 ppm/oC, a long-term

drift of 10 ppm/√

1000hr with an ultra-low power consumption of 500 nA). The prob-

lem with Floating-Gate design, however, is the lack of the appropriate models needed

for simulation (models for Fowler-Norheim tunneling and hot-carrier effects). Some

models are available in literature [Rahimi 02], [Pavan 04]. However, these models re-

quire process data that are, generally, not provided by Semiconducor manufacturers.

• Bandgap References are inherently compatible with modern CMOS technologies.

Bandgap technology is very mature and has been widely used in literature and in

the industry. Bandgaps, however, usually have lower performance (when compared

to the afore-mentioned technologies) in terms of noise, temperature drift and long-

term drift. Nevertheless, low-cost and compatibility with CMOS technologies make

Bandgaps an attractive choice for implementing the Voltage Reference.

Based on the above discussion, Bandgap Technology will be adopted in this work. At-

tempts will be made to overcome the inherent performance limitations of CMOS-compatible

Bandgaps. In the following section, the basic bandgap circuit implementation is presented

and various aspects of its performance are analyzed.

5.2. Reference Voltage Specs 75

5.2 Reference Voltage Specs

This section discusses the required specs for the reference voltage circuit to achieve a

maximum SNR of 110dB for the acceleration sensing system (corresponding to an ENOB

of 18 bits).

5.2.1 Reference Voltage Value

The value of the reference voltage determines the maximum value of the feedback force.

This, in turn, determines the maximum allowable input force (that wouldn’t overload

the ΣΔ modulator). The maximum allowable force will be a fraction of the maximum

feedback force. The value of this fraction depends on the specific implementation of the

ΣΔ force-feedback loop (with higher-order loops generally having lower maximum inputs)

[Schreier 05].

Since the chosen technology limits the supply voltage to 3.3V, the reference voltage

value is chosen to be 3V. This choice will result in reasonable headroom requirement for

reference voltage circuitry. With the bandgap voltage having a typical value of 1.2V, a

multiplying Opamp would be needed as shown in figure 3.1 to generate the 3V reference.

Only the voltage reference circuit - without the multiplying Opamp - will be implemented.

5.2.2 Output Noise

As discussed in section 3.4, the target SNR of 120dB from the voltage reference translates

to a vn

Vref idealratio of 0.7μ. Hence, for a 3V reference the total integrated noise in the

band 1mHz-100Hz should be equal to 2.1μV for the reference to achieve an SNR of 120dB.

This budget should be distributed between the reference voltage generation circuit and

the multiplting Opamp. Since the bandgap reference generation circuitry would be much

noisier than the multiplying Opamp, this budget is totally allocated to the bandgap circuit.

It is assumed that the multiplying Opamp can achieve an output noise much smaller than

this value (since uncorrelated noise sources add in a rms manner, ”much smaller” will

correspond to a factor of 4). Note that even if the multiplying Opamp adds more noise,

the overall system spec of 110dB can still be achieved due to the 10dB design margin. Since


the 1.2V bandgap circuit is multiplied by 2.5 to get the 3V reference, the output noise from

the 1.2V bandgap circuit should be around 0.9μV in the band from 1mHz-100Hz.

5.2.3 Drift

No specific value is required for the drift (which includes both drift with temperature and

long-term drift). Nevertheless, minimizing drift can help reduce system cost by reducing

the time intervals between which the system needs to be recalibrated. Towards this end,

a discussion is presented in section 5.3.2 on the measures that can be taken to reduce

long-term drift. Furthermore, a new temperature compensation technique is presented in

section 5.4.3 to achieve low temperature drift.

5.3 The Basic Bandgap Circuit: An overview

As discussed in the previous section, Bandgap technology is chosen for the reference voltage

implementation.

Figure 5.1 [Kujik 73] [Razavi 01] shows a basic Bandgap circuit. If an ideal Opamp is

assumed, then nodes 1 and 2 will be held at the same voltage. Hence:

V1 = V2 = Vbe1 (5.1)

where Vbe1 is the base-emitter voltage of the diode-connected transistor Q1. Hence, the

current flowing in the resistor RPT will be given by:

I2 =Vbe1 − Vbe2

RPT

(5.2)

But:

Vbe1 = VT ln

(I1Is1

)(5.3)

Vbe2 = VT ln

(I2Is2

)(5.4)

5.3. The Basic Bandgap Circuit: An overview 77

Figure 5.1: A Basic Bandgap circuit [Kujik 73] [Razavi 01]

Where Is1 and Is2 are the reverse saturation currents of transistors Q1 and Q2, respec-

tively. Therefore:

I2 =Vbe1 − Vbe2

RPT=

VT

RPTln

(I1I2.Is2Is1

)(5.5)

If transistors Q1 and Q2 are matched (i.e. made up of the same unit element), then the

ratio Is2

Is1is simply the ratio of the number of unit elements of both transistors, i.e. :

Is2Is1

= N (5.6)

Where it is assumed that transistor Q1 is made up of a single unit-element, whereas

transistor Q2 is made up of N unit elements. On the other hand, the currents I1 and I2

can be calculated as:

I1 =Vout − V1

RCT1

=Vout − Vbe1

RCT1

(5.7)

I2 =Vout − V2

RCT2

=Vout − Vbe1

RCT2

(5.8)

Where equation 5.1 was used. From equations 5.7 and 5.8, it can be seen that:


I1I2

=RCT2

RCT1(5.9)

Hence, equation 5.5 can be rewritten as:

I2 =VT

RPT. ln

(RCT2

RCT1.N

)(5.10)

If the resistors RCT1 and RCT2 are matched with the ratio RCT2

RCT1equal to M, then I2

can be rewritten as:

Figure 5.2: CMOS-compatible bandgap circuit

I2 =VT

RPT. ln (M.N) (5.11)

Hence, the output voltage Vout can be expressed as:

Vout = V2 + I2.RCT2 (5.12)


Substituting from equations 5.1 and 5.11 into equation 5.12, then Vout can be expressed

as:

Vout = Vbe1 +RCT2

RPT.VT . ln (N.M) (5.13)

Equation 5.13 is the equation of a bandgap voltage. As discussed in section 4.2.4,

the term Vbe is the CTAT term whereas the VT ln (N.M) term is the PTAT term. Since

the slope of the PTAT term with temperature is smaller than that of the CTAT term,

the factor RCT2

RPTis introduced to make both slopes equal and, hence, acheive the desired

reference that is constant with temperature (to a 1st order) [Razavi 01].

The circuit shown in figure 5.1 is thus a basic implementation of the Bandgap reference.

However, this circuit suffers from two major drawbacks:

1. NPN Bipolar transistors are used which are incompatible with the modern CMOS

technologies (which predominantly use P-type substrates) [Razavi 01]

2. The Opamp used has to supply the DC currents I1 and I2, which complicates the

design of the Opamp. The presence of a resistive load decreases the effective gain of

the Opamp, dictating the use of a low-impedance output stage

A more CMOS-compatible implementation of the bandgap circuit is shown in figure

5.2 [Mok 04]. The 1:M PMOS current mirror ensures that the ratio of the currents in

the two-branches is constant independent on the value of the RCT resistors (unlike the

implementation of figure 5.1). From figure 5.2, it can be concluded that:

Vout = Vbe1 +RCT

RPT.VT . ln (N.M) (5.14)

The following notes can be observed on the bandgap circuit in figure 5.2:

• The Opamp in figure 5.2 is not resistively loaded. Instead, it controls the gate

of the PMOS current mirrors. Hence, it is capacitively loaded. This relaxes the

requirements on the Opamp, making the use of single-stage topologies a viable option.

Single-stage topologies are generally more power-efficient than two-stage topologies

and they are, generally, easier to stabilize. This is a definite advantage over the

implementation in figure 5.1


• The NPN transistors in figure 5.1 are replaced by PNP transistors. PNP transistors

are readily available in all CMOS technologies. Two types of PNP transistors are

available for CMOS technologies, namely: vertical-PNP and lateral-PNP transistors

[Pertijs 06]. A discussion of which PNP type to use is presented in section 5.3.1

• The loop gain of the circuit in figure 5.2 is higher than that of the circuit in figure 5.1.

This can be attributed to the addition of an active element (the PMOS transistor) in

the feedback path of the circuit in figure 5.2. The circuit in figure 5.1, on the other

hand, has a purely passive feedback and, hence, a lower loop gain. This, in turn,

means that a higher Opamp gain would be required for the circuit in figure 5.1 than

that of figure 5.2 if the same error is to be achieved. A discussion of the Opamp gain

requirement is presented in section 5.3.4

In the following sections, a more elaborate discussion is presented on the various per-

formance aspects of the CMOS-compatible bandgap circuit (shown in figure 5.2). For this

discussion, the special (but very common) case of M=1 will be used.

5.3.1 Lateral versus Vertical PNP in bandgap circuits

Two flavors of PNP transistors exist in CMOS technologies: Lateral-PNPs and vertical-

PNPs [Pertijs 06]. A cross section of a lateral PNP transistos is shown in figure 5.3.

The lateral PNP transistor is basically a parasitic transistor that is formed by any PMOS

transistor. The N-Well constitutes the base of the transistor, whereas the emitter and the

collector are formed by P+ diffusions. The current flows laterally from the emitter (P+

diffusion), through the base (N-Well) and down to the collector (P+ diffusion). The base-

width is, thus, determined by the channel length of the PMOS transistor. Hence, small

base-widths are available allowing high common-emitter current-gain (β). To avoid the

operation of (the now parasitic) PMOS transistor, the gates are usually connected to the

supply voltage. This has the added advantage of pushing the holes in the base (N-Well)

away from the surface, decreasing the 1/f noise of the transistor. A problem with the lateral

PNP transistor is the existence of a parasitic vertical-PNP transistor formed by the p+

source (emitter), the N-well(base) and the substrate (collector). This parasitic transistor

(marked in grey in figure 5.3) causes a substantial part of the current injected by the


emitter to flow vertically into the substrate rather than laterally into the p+ collector. The

resulting Ie - Vbe characteristic is very non-ideal. Lateral pnp transistors therefore have to

be biased via their collector, which precludes their use in a diode-connected configuration.

Moreover, their Ic-Vbe characterisitics are far from ideal due to the presence of two paths

for the lateral current: a direct lateral path and a curved lateral path. At low currents,

the direct-lateral current dominates whereas the curved lateral component dominates at

higher currents (due to current-crowding) [Pertijs 06].

Figure 5.3: A cross section of a lateral PNP transistor in CMOS technology [Pertijs 06]

A cross section of a vertical PNP transistor is shown in figure 5.4 [Pertijs 06]. This is es-

sentially the same device as the parasitic transistor associated with lateral pnp transistors.

The emitter is formed by a P+ diffusion in an N-Well, the N-Well itself forms the base of

the transistor and the collector is formed by the P-substrate outside the N-Well. As a con-

sequence, the collector of a vertical PNP transistor has to be always connected to ground.

The base width of vertical PNP transistors is relatively large, as it is mainly determined

by the depth of the N-well (typically a few microns). As a result, the common-emitter

current-gain (β) of these transistors is very low compared to that of lateral PNP transis-

tors. Moreover, the current flow in verical PNP transistors is much more one-dimensional

than in lateral PNP transistors. As a result, their Ic-Vbe characteristic closely follows the

ideal exponential behavior over several decades of current. This, together with the fact


that the common-emitter current-gain (β) is constant over a wide range of emitter-currents,

results in an ideal Ie-Vbe characteristic that makes them suitable for use as diode-connected

transistors. Another advantage of the wide base of substrate pnp transistors is that varia-

tions in the depth of the N-well or the P+ diffusion will have relatively little effect on the

transistors saturation current. If the transistors emitter area is large enough, variations

due to lithographic errors will also be small. A lateral PNP transistor, in contrast, will have

an effective emitter area that varies with the depth of the P+ implant. Moreover, litho-

graphic errors will have a much larger effect, because they affect the relatively small base

width. Therefore, the relative spread of the saturation current of lateral PNP transistors is

expected to be larger than that of vertical PNP transistors in the same process [Pertijs 06].

Figure 5.4: A cross section of a vertical PNP transistor in CMOS technology [Pertijs 06]

Another advantage of vertical PNP over lateral PNP concerns the long-term stability.

Mismatches in the thermal coefficients of expansion (TCE) of different materials of the

wafers and packages cause mechanical stress that is temperature and time dependent.

These stresses, in turn, induce changes in the Ic-Vbe characteristic of bipolar transistors.

This is known as the Piezojunction effect. Piezojunction effect is found to be the main cause

of the long-term drift in bandgap circuits. It was found that vertical PNP transistors are

less prone to the Piezojunction effect and are , hence, favorable when it comes to long-term

drift [Meijer 01] [Creemer 01].


It can thus be concluded that vertical PNP transistors are a better choice for the imple-

mentation of high-performance bandgap circuits.

5.3.2 Long-term drift in bandgaps

The dependence of the bandgap voltage on mechanical stress is the main cause of long-term

drift and packaging-induced inaccuracy in such circuits [Fruett 03] [Creemer 01]. Stress

on the Silicon die is caused by the different thermal expansion coefficients of the package

substrate material and the Silicon die [Bastos 97]. The effect of this induced stress on

the bandgap circuit components (MOS transistors, bipolar transistors and resistors) will

be discussed briefly below.

It is shown in [Bastos 97] that mechanical stress induced mismatch in MOS transistors

is larger than the random mismatch due to process gradients. It is also shown that the

amount of induced stress depends on the die-bonding material; Polyimide bonding causes

smaller stresses compared to eutectic bonding. To minimize the effect of stress-induced

mismatch, common-centroid layout techniques can be used. Besides, care has to be taken

in layout to avoid stress induced by metallization; a rule of thumb is that metal layers

should not pass over critical circuit components. If this is not a viable option, symmetrical

metallization should be used so that matched components ”see” the same stress. Further-

more, placing the matched components at the center of the die (as opposed to the die edge)

is shown to reduce the sensitivity of matched components to stress [Creemer 01]. Even

with the use of these techniques, stress will still have a residual effect. To minimize this

effect, mismatch cancellation techniques (such as chopping, Dynamic Element Matching

and correlated-double sampling) can be used [Meijer 01].

Stress affects resistors through the piezoresistive effect [Creemer 01]. The piezoresistive

effect is defined as the change in the resistivity of a material when subjected to a mechanical

stress. For matching resistors, the same techniques used for matching transistors can be

applied. Furthermore, the effect of stress can be reduced by making up resistors of lateral

and vertical sections connected in series [Creemer 01].

Bipolar transistors are affected by stress through the piezojunctioin effect, which is

defined as the change in the bipolar transistor saturation current Is due to mechanical

stress [Creemer 01]. The piezojunction effect affects both the PTAT voltage (i.e. ΔVbe) and


the Vbe voltage. Since the PTAT voltage is formed by the difference between the Vbe’s of two

matched transistors, piezojunction effect has a limited effect on it [Fruett 03]. On the other

hand, the Vbe voltage is more sensitive to the piezojunction effect. It is shown in [Fruett 03]

that the effect of stress on Vbe is the major source of long-term drift in bandgap circuits.

To minimize the piezojunction effect, it is recommended to use substrate (i.e. vertical)

PNP transistors (rather than lateral PNP transistors or NPN transistors) [Creemer 01].

Another possible measure to reduce this effect is to place the Vbe-generating transistor in

the chip corner. As shown in [Bastos 97], the stress at the corner of the chip is minimal

(but the stress gradient is maximum). Since the Vbe generating transistor is also a part of

the ΔVbe-generating circuitry (that depends on matching), placing it at the chip corner will

compromise matching (due to increased stress gradients at chip corner). The advantage of

such a measure requires experimental verification, however.

To summarize, reducing the long-term drift in bandgap circuits translates to reducing

the effect of stress. Towards this end, the possible measures that can be taken include:

• Using common-centroid layout techniques for transistors and resistors

• Using mismatch cancellation techniques such as chopping, DEM and CDS

• Splitting resistors into lateral and vertical sections connected in series

• Using substrate pnp transistors

• Placing the Vbe generating transistor at the chip corner (this is a suggestion that

lacks experimental verification, however)

5.3.3 Stability of the CMOS-compatible bandgap

5.3.3.1 Evaluating the Loop Gain

The bandgap circuit in figure 5.2 includes both positive and negative feedback loops

[Razavi 01]. Figure 5.5 indicates both loops on the CMOS-compatible bandgap circuit.

It is to be noted that the positive feedback loop is associated with the negative terminal of

the Opamp, whereas the negative feedback loop is associated with the positive terminal of


Figure 5.5: CMOS-compatible bandgap with positive and negative feedback indicated

the Opamp. This can be attributed to the presence of the PMOS transistor which forms

an inverting common-source stage in the feedback path.

For stable operation, the gain around the negative feedback loop must be higher than

the gain around the positive feedback loop. This explains the choice of the Opamp connec-

tions; the negative terminal (associated with positive-feedback) is connected to the loop

with the smaller gain whereas the positive terminal (associated with negative-feedback) is

connected in the loop with the higher gain. To further explain this point, consider figure

5.6 which shows the AC model for both loops. To calculate the loop gain around the neg-

ative feedback loop, the positive feedback loop is deactivated by grounding the Opamp’s

negative terminal. To get the gain around the positive feedback loop, on the other hand,

the Opamp’s positive terminal is grounded.

Hence, the gain around the negative feedback loop Afb− will be given by:

Afb− = Aop.gmp.

(RPT +

1

gmQ2

)(5.15)

Where:


Aop is the open loop gain of the Opamp

gmp is the transconductance of the PMOS transistor

gmQ2 is the transconductance of the bipolar transistor Q2

Similarly, the gain around the positive feedback loop will be given by:

Afb+ = Aop.gmp.1

gmQ1(5.16)

Where gmQ1 is the transconductance of the bipolar transistor Q1. Since the same

currents flow in Q1 and Q2, then gmQ1 = gmQ2 and hence Afb+ can be expressed as:

Afb+ = Aop.gmp.1

gmQ2(5.17)

(a) Negative FeedbackLoop

(b) Positive FeedbackLoop

Figure 5.6: AC model used for evaluating Loop Gains in CMOS-compatible bandgap

Comparing the expressions of Afb− and Afb+, it can be seen that the negative feedback

loop gain is higher than the positive feedback loop gain making the overall loop a negative-

feedback loop. The overall negative feedback loop gain (LG) can now be expressed as:

LG = Afb− − Afb+ = Aop.gmp.RPT (5.18)


Aop0 (dB) RPT (kΩ) gmp(μS) Loop Gain simulated (dB) Loop Gain calculated (dB)

6010 35.4 50.88 50.98

5 49.28 47.69 47.83

8010 35.02 70.78 70.87

5 48.8 67.75 67.61

Table 5.1: Loop Gain Simulated versus Calculated values

This means that, in effect, the overall negative-feedback loop is as shown in figure 5.7.

To validate this conclusion, a number of simulations (using SpectreTM

circuit simulator)

are made on the CMOS-compatible bandgap circuit of figure 5.2 in which a behavioral

Opamp is used (the behavioral model is shown in Appendix B). Two different values are

used for Aop and two other values are used for RPT . For each combination of Aop and RPT

the loop gain is simulated and is also calculated by the equation 5.18. Table 5.1 shows

the comparison between simulation and calculation results. It can be seen that they are

in close agreement.

It is to be noted that the expression of LG given in equation 5.18 can be obtained

from the expression of Afb− by simply ignoring 1gmQ2

as compared to RPT . While this may

sound as a reasonable assumption at a first glance, careful analysis shows that it is not. In

ignoring 1gmQ2

, one would be tempted by the fact that bipolars have large transconductances

hence making the term 1gmQ2

negligible. However, analysis shows that:

gmQ2 =IcVT

=α.I

VT

(5.19)

Where α is the common-base current gain of the bipolar transistor [Sedra 98]. The

current I is PTAT and can be found by setting M=1 in equation 5.11. Doing so and

reevaluating 1gmQ2

, it is found that:

1

gmQ2=

RPT

α. ln (N)(5.20)

The value of N is commonly chosen to be eight to allow a symmetrical common-centroid

layout of the bipolars [Mok 04]. Hence, ln(N) is equal to about two. Furthermore, α is


Figure 5.7: Equivalent AC model of the overall negative-feedback

significantly less than one since vertical-PNP transistors have low β [Pertijs 06]. Conse-

quently, it can be concluded that the term 1gmQ2

cannot be ignored compared to RPT .

To assess the stability of the bandgap’s negative feedback loop, it is important to locate

the nodes that correspond to the dominant and non-dominant poles. Inspection of figure

5.5 suggests that there are two major poles: one located at the output of the Opamp and

the other located at the drain of the PMOS transistor on which the output is taken. The

Opamp’s output node is expected to have higher impedance (since high-impedance would

be required for large Opamp gain)1. Hence, the dominant pole will be set by the Opamp’s

output impedance and the gate-capacitance of the PMOS transistor (the capacitance of

the two-mirror transistors has to be taken into consideration). The load capacitance at

the PMOS drain together with the output resistance seen into the drain determine the

non-dominant pole.

5.3.3.2 Effect of output node choice on stability

As shown in figure 5.5, the output can be taken at either of the two nodes Vout or Voutp.

The voltage Vout is the output of the negative feedback loop, whereas Voutp is the output

1This assumes a single-stage Opamp. If a two-stage Opamp is used, the highest impedance node wouldbe an internal Opamp node


of the positive feedback loop; both outputs have the desired DC bandgap characteristics.

From a stability point of view, however, they are different. By intuition, it is better to

take the output voltage at Voutp: the output of the positive feedback loop. By doing so,

the load capacitance (CL) is placed at the output of the positive feedback loop where it is

unlikely to disrupt stability. To verify this conclusion, a simulation is made on a bandgap

circuit with a behavioral Opamp (the behavioral model is shown in Appendix B). The

load capacitance is placed once on Vout and once on Voutp, then the loop gain magnitude

and phase is simulated for each case. The results, shown in figure 5.8, are in agreement

with the intuitive conclusion; the phase margin for the Vout case is negative (almost -20o)

as opposed to a positive phase margin (almost +90o) for the Voutp case.

To get a better understanding of this result, the loop’s frequency response needs to be

evaluated for both cases. In both cases, the Opamp determines the dominant pole. Hence,

the Opamp’s frequency-dependent gain Aop(s) implicitly contains the dominant pole.

Consider first the case where CL is connected to Voutp. In this case, the overall negative

feedback loop gain (LG) will be given by:

LG = Afb− (s) − Afb+ (s)

= Aop(s).gmp.

((RPT + 1

gmQ

)−„

RCT + 1gmQ

«. 1sCL

RCT + 1gmQ

+ 1sCL

.1

gmQ

RCT + 1gmQ

)(5.21)

Where:

LG is the overall Loop Gain

gmQ is the transconductance of the Bipolar transistors (both transistors have the same

transconductance)

LG in equation 5.21 can be further reduced to:

LG = Aop(s).gmp.

((RPT + 1

gmQ

)−

1sCL

RCT + 1gmQ

+ 1sCL

. 1gmQ

)

= Aop(s).gmp.

((RPT + 1

gmQ

)− 1

1+sCL.

„RCT + 1

gmQ

« . 1gmQ

)(5.22)

Let the term(RCT + 1

gmQ

)be denoted by Reqp. Hence, LG can further be reduced to:


(a) CL connected to Voutp (b) CL connected to Vout

Figure 5.8: Loop Gain and Phase for CL connected to Voutp and Vout


LG = Aop(s).gmp.RPT .

((1 + 1

gmQ.RPT

)−

1gmQ.RPT

1+sCL.Reqp.

)= Aop(s).gmp.RPT

gmQ.RPT.((gmQ.RPT + 1) − 1

1+sCL.Reqp.)

= Aop(s).gmp.RPT

gmQ.RPT. (gmQ.RPT + 1) .

(1 − 1

(gmQ.RPT +1).(1+sCL.Reqp).

)

= Aop(s).gmp.RPT

gmQ.RPT.

((gmQ.RPT +1).(1+sCL.Reqp)−1

(1+sCL.Reqp).

)

= Aop(s).gmp.RPT

gmQ.RPT.

(gmQ.RPT .+sCL.Reqp.(1+gmQ.RPT )

(1+sCL.Reqp).

)(5.23)

Thus, LG can be finally put in the form:


⎛⎝1.+ sCL.Reqp.

(1 + 1

gmQ.RPT

)(1 + sCL.Reqp)

.

⎞⎠ (5.24)

From equation 5.24, it can be seen that taking the output at Voutp will cause the loop

gain equation to have a Left Half Plane (LHP) zero and a pole. The pole and zero are

very near in frequency (recall that gmQ.RPT =α.ln (N)≈2). They, thus, form a pole-zero

doublet. In the magnitude response, the pole and zero almost cancel each other (as they

are close in frequency). In the phase response, however, the LHP zero enhances stability

by increasing the phase. This can be clearly seen in figure 5.8(a)

Now, consider the case where CL is connected to Vout. In this case, the overall negative

feedback loop gain (LG) will be given by:

LG = Aop(s).gmp.

⎛⎝ 1

sCL

(RCT +RPT + 1

gmQ

)1

sCL+RCT +RPT + 1

gmQ

.RPT + 1

gmQ

RCT +RPT + 1gmQ

− 1

gmQ

⎞⎠ (5.25)

Let RCT +RPT + 1gmQ

be denoted by Reqn. Hence, LG can further be reduced to:

LG = Aop(s).gmp.

(RPT + 1

gmQ

1+s.CL.Reqn− 1

gmQ

)= Aop(s).

gmp

gmQ.(

gmQ.RPT +1

1+s.CL.Reqn− 1)

= Aop(s).gmp

gmQ.(

gmQ.RPT−s.CL.Reqn

1+s.CL.Reqn

) (5.26)


LG can finally be reduced to the form:


(1 − s.CL.Reqn

gmQ.RPT

1 + s.CL.Reqn

)(5.27)

From equation 5.27, it can be seen that taking the output at Vout will cause the loop

gain equation to have a Right Half Plane (RHP) zero and a pole. As in the case of Voutp,

the pole and zero form a pole-zero doublet. However, since the zero in this case is an RHP

zero, it degrades the loop’s stability by decreasing the phase as can be observed in figure

5.8(b).

The Loop’s stability can be improved, in general, by increasing the load capacitance

at the dominant-pole node i.e. by connecting a capacitor between the Opamp’s output

and AC ground. Two nodes can be used as AC ground: the circuit’s DC ground and

the circuit’s DC supply Vdd. Supply rejection requirements favor the use of Vdd as an AC

ground (a more elaborate discussion is to be presented in section 5.3.5).

5.3.4 Opamp Gain Requirement in the CMOS-compatible bandgap

In any negative feedback system, a high loop gain is desirable to minimize the feedback

error [Razavi 01]. The definition of the word ”high” depends on the application at hand.

In the context of the CMOS-compatible bandgap circuit of figure 5.2, the high loop gain

aims at equalizing the voltages of nodes 1 and 2. Hence, it is necessary to evaluate the

error between the voltages of the nodes 1 and 2 and, in turn, evaluate the effect of this

error on the final desired output bandgap voltage. Towards this end, figure 5.9 shows the

model used to evaluate the effect of the Opamp finite gain. Δv represents the error at the

Opamp input due to finite Opamp gain Aop (or, more generally, the finite loop gain). V1

is simply the voltage Vbe1. Thus, we have a negative feedback system whose input is Vbe1.

Hence, the error ΔV can be expressed as:

ΔV =Vbe1

1 + LG(5.28)

Where LG is the loop gain. From equation 5.18, the loop gain is given by the factor

Aop.gmp.RPT . Hence, the error will be given by:


Figure 5.9: Model for evaluating the effect of finite Opamp gain

Figure 5.10: Bandgap circuit with Offset voltage representing effect of finite gain


ΔV =Vbe1

1 + Aop.gmp.RPT(5.29)

Now that this error has been calculated, it has to be incorporated into the bandgap

circuit so that the value of the bandgap voltage reflects this error source. This can be done

by adding an offset voltage source (Vop = Vbe1

1+Aop.gmp.RPT) in series with the positive terminal

of the Opamp as shown in figure 5.10. The Opamp in figure 5.10 is an ideal Opamp, and

the offset voltage source Vop accounts for the Opamp’s finite gain.

With the source Vop present, the voltage V2 can be expressed as:

V2 = V1 − Vop = Vbe1 − Vop (5.30)

Hence, the current I will be given by:

I =Vbe1 − Vop − Vbe2

RPT

=VT . ln (N) − Vop

RPT

(5.31)

The output bandgap voltage will thus be given by the equation Vout = V2 + I.RCT ,

which can be further expanded to:

Vout ≈ Vbe1 +RCT

RPT

. (VT . ln (N) − Vop) (5.32)

Hence, the effect of the finite Opamp gain is to subtract a CTAT term (RCT

RPT.Vop ≈

RCT

RPT. Vbe1

1+gmp.Aop.RPT) from the bandgap voltage. This results in deviation of the bandgap

voltage from the expected value. To see the effect of this error, Vbe1 in the error term will

be decomposed into two components: Vbe avg that represents the average value of Vbe across

temperature, and Vbe T that represents the temperature-dependent portion of Vbe. Two

effects can be observed:

1. Vbe avg will cause an output offset voltage. This offset, however, will have no effect

on temperature compensation as it is temperature-independent

2. Vbe T will cause a variation in the bandgap’s curvature. Hence, it is expected to

worsen the output peak-to-peak variation across temperature


The constant output offset doesn’t deteriorate the bandgap voltage’s curvature; it just

shifts the whole bandgap characteristics. The most pronounced effect will be due to the

temperature-dependent offset Vbe T . The error term in equation 5.32 is equal to Vbe1 divided

by the loop gain and multiplied by the ratio RCT

RPT. For the common case of N=8, the ratio

RCT

RPTamounts to about 10. Hence, the error term is almost equal to Vbe1 divided by one

tenth of the loop gain. To make the error term negligible compared to Vbe1 (and hence make

its temperature effect negligible compared to Vbe1), it is necessary to make it less than Vbe1

by a factor of 10 at least. This, in turn, means that one tenth the loop gain should be

equal to 10 i.e. a loop gain of 100 (40 dB) or more would be needed. In fact, simulation

results indicate that a loop gain of about 50 dB or more is needed to achieve the smallest

peak-to-peak variation across temperature.

5.3.5 Supply Rejection in the CMOS-compatible Bandgap Cir-

cuit

An important performance aspect of a voltage-reference is its rejection to supply noise.

Ideally, the voltage reference should be completely insensitive to supply noise and supply

variations. However, circuit non-idealities will inevitably introduce some dependence on the

supply [Razavi 01]. The supply rejection of bandgap circuits was discussed in a number

of publications [Giustolisi 01] [Giustolisi 03] [Hoon 02]. [Giustolisi 01] discusses supply

rejection in Brokaw bandgap references, [Giustolisi 03] discusses supply rejection in Brokaw

bandgap references and in the bandgap reference of figure 5.1, while [Hoon 02] presents an

expression for the DC supply rejection of the CMOS-compatible bandgap. Hence, there is

a need for a complete and simple model that describes the supply rejection of the CMOS-

compatible bandgap circuit at DC as well as high frequencies. Special care is given to the

effect of the Opamp’s supply rejection which can be determintal to the overall bandgap’s

supply rejection [Gupta 04]2.

To remove ambiguity, the supply rejection will be defined as the small-signal transfer

function from the supply vdd to the bandgap output vout i.e.:

2 [Gupta 04] discusses supply rejection of LDOs. Nevertheless, the circuit structure of LDOs bearssignificant resemblance to the CMOS-compatible bandgap making [Gupta 04] a valuable reference


PSR =vout

vdd(5.33)

Where PSR is short for Power Supply Rejection. Hence improving supply rejection

implies minimizing PSR.

5.3.5.1 DC Supply Rejection

As discussed in section 5.3.3, the overall negative feedback in the CMOS-compatible

bandgap circuit can be represented by the small signal model of figure 5.7. Hence, this

model will be used to evaluate PSR. Towards this end, a small signal stimulus will be

connected to the vdd terminal and the corresponding output at vout will be evaluated. The

corresponding model is shown in figure 5.11. The resistor rds represents the small signal

output impedance of the PMOS transistor. The term Gop is the small signal gain from vdd

to the output of the Opamp.

Figure 5.11: Model used for PSR evaluation

Hence, the voltage v2 will be given by:


v2 = i.RPT (5.34)

The current i will have two components: the first corresponding to the gmp.vsg of the

PMOS transistor and the second corresponding to the current in the PMOS transistor’s

output resistance. Thus, i can be expressed as:

i = gmp. (vdd −Aop.v2 −Gop.vdd) +vdd − vout

rds

(5.35)

Substituting from equation 5.35 into equation 5.34, v2 can be expressed as:

v2 = gmp.RPT . (vdd − Aop.v2 −Gop.vdd) +RPT

rds. (vdd − vout) (5.36)

Rearranging equation 5.36, v2 can now be expressed as:

v2 =1

1 + gmp.RPT .Aop.

(gmp.RPT .vdd. (1 −Gop) +

RPT

rds. (vdd − vout)

)(5.37)

The output voltage vout can also be given by:

vout = v2 + v2.RCT

RPT

= v2.

(1 +

RCT

RPT

)(5.38)

Hence, substituting by v2 from equation 5.37 vout can be expressed as:

vout =1 + RCT

RPT

1 + gmp.RPT .Aop

.

(gmp.RPT .vdd. (1 −Gop) +

RPT

rds

. (vdd − vout)

)(5.39)

Rearranging equation 5.39, one gets:

vout

(1 +

RPT

rds

.1 + RCT

RPT

1 + gmp.RPT .Aop

)=

1 + RCT

RPT

1 + gmp.RPT .Aop

.

(gmp.RPT . (1 −Gop) +

RPT

rds

).vdd

(5.40)

Hence, the DC value of PSR (PSR0) can be expressed as:


PSR0 =vout

vdd=

1 + RCT

RPT

1 + gmp.RPT .Aop.

⎛⎜⎝gmp.RPT . (1 −Gop) + RPT

rds

1 + RPT

rds.

1+RCTRPT

1+gmp.RPT .Aop

⎞⎟⎠ (5.41)

The PSR expression of equation 5.41 is rather complex. Fortunately, some simplifica-

tions can be made to obtain a handy expression. The ratio RCT

RPTis typically much larger

than 1. Similarly, gmp.RPT .Aop represents the loop gain and is thus also much larger than

1. Thus, PSR0 can be approximated to:

PSR0 =

RCT

RPT

gmp.RPT .Aop.

⎛⎜⎝gmp.RPT . (1 −Gop) + RPT

rds

1 +RCTrds

gmp.RPT .Aop

⎞⎟⎠ (5.42)

Another approximation can be made on the above equation. The ratio RCT

rdsin the

denominator of the term in parentheses is much smaller than one. This is based on the

assumption that rds >> RCT , which is a reasonable assumption in pactice. Besides, the

ratio RCT

rdsis divided by the loop gain, further reducing its value. Hence, the DC value of

PSR can finally be represented as:

PSR0 =RCT

RPT.(1 −Gop)

Aop+

RCT

rds

gmp.RPT .Aop(5.43)

For the purpose of discussion, equation 5.43 can be rearranged as:

PSR0 =RCT

RPT.

((1 −Gop)

Aop+

1

gmp.rds.Aop

)(5.44)

To validate the expression reached in equation 5.44, a number of simulations are made

using a behavioral Opamp (the behavioral model is shown in Appendix B). Table 5.2

shows comparison between simulated and calclated values for two different Opamp gain

values, and three Opamp PSR values. The simple expression of equation 5.44 predicts

PSR0 within a 2 dB error, which is quite acceptable in practice.

The following notes can be made on the expression of PSR0 in equation 5.44:

• The ratio RCT

RPTis determined by N (the ratio of the areas of the Bipolar transistors).

For a given N, RCT

RPTshould be adujsted to make the slope of the PTAT voltage


Aop (dB) Gop gmp(μS) rds (MΩ) PSR0 sim. (dB) PSR0 calc. (dB)

600.9 35.41 14 -58.38 -59.65

1.0 35.41 14 -92 -93.73

800.95 35.02 14.48 -84.23 -85.5

1.0 35.02 14.48 -111.86 -113.93

Table 5.2: PSR0 Simulated versus Calculated values

(VT . ln (N)) equal to the slope of the Vbe voltage. Thus, RCT

RPTcannot be deliberately

set to adjust the desired PSR0

• The 2nd term of equation 5.44 is inversely proportional to the loop gain, and also

to the output resistance of the PMOS transistor rds. Thus, this term can be easily

minimized by either increasing the loop gain (basically through increasing the gain of

the Opamp Aop) or by increasing rds (by increasing the length of the PMOS transistor

or by adding a cascode transistor to the current mirror). Thus, through proper choice

of Aop and rds the 2nd term can be made non-dominant

• The 1st term of equation 5.44 is inversely proportional to the Opamp’s gain and

directly proportional to (1−Gop), where Gop is the PSR of the Opamp. Hence, this

term will be larger than the 2nd term. To minimize the 1st term, Gop should be

as close as possible to one i.e. the Opamp should have a poor PSR. This can be

intuitevly understood by observing figure 5.11; if the Opamp has a poor PSR, the

supply vdd will couple to the gate of the PMOS transistor minimizing vsg. This, in

turn, will minimize the current component gmp.vsg, hence, decreasing PSR. A similar

result was reached in [Gupta 04] in the context of LDO supply rejection. Towards

this end, it is better to use Opamps with PMOS current-mirror loads which achieve

a near-unity PSR (as opposed to Opamps with NMOS mirror loads that achieve a

near zero PSR) [Gupta 04]

• It can be seen from equation 5.44 that a zero value for PSR0 can be obtained if the

1st and 2nd terms cancel each other. The 2nd term of equation 5.44 is always positive.

The 1st term, however, can be made negative if Gop is made slightly larger than unity.


An important consequence of this observation is that PSR0 can actually be better

than 1Aop

. In the normal cases (where Gop is less than unity), PSR0 is worse (i.e.

larger) than 1Aop

. To illustrate this point, equation 5.44 can be rearranged as:

PSR0 =1

Aop

.RCT

RPT

.

((1 −Gop) +

1

gmp.rds

)(5.45)

It can be seen that PSR0 is equal to 1Aop

multiplied by a factor. This factor has two

coefficients: RCT

RPTand

((1 −Gop) + 1

gmp.rds

). The first coefficient is always greater

than one (for N=8 the factor RCT

RPTis around 10). The 2nd coefficient will be greater

than zero if Gop is less than one, which is the most common case. Tweaking the value

of Gop can make it slightly larger than one, effectively reducing the 2nd coefficient

and eventually decreasing the overall value of PSR0. For Gop = 1 + 1gmp.rds

, PSR0

will be equal to zero.

Figure 5.12: PSR0 versus Gop0 illustrating the possibility of a zero PSR0

To verify the above conclusion, a simulation is made with a behavioral Opamp (the

behavioral model is shown in Appendix B). To get a zero PSR, the Opamp’s Gop0

must be set with a very high precision (since the value of 1gmp.rds

is very small). For


this specific simulation, gmp is equal to 35μS and rds is equal to 14.48 MΩ. Hence,

the Gop0 value required for a zero PSR0 is approximately equal to 1.002. To avoid

the precision pitfall, Gop0 is swept from 1 to 1.004. The result, shown in figure 5.12,

shows that PSR0 decreases to very low values in the vicinity of Gop=1.002, thus

verifying the conclusion and further validating the PSR0 expression of equation 5.44

5.3.5.2 High Frequency Supply Rejection

Now that the value of PSR at DC (PSR0) has been evaluated and verified by simulation,

it’s important to evaluate the frequency charachteristics of PSR. This will be done on two

steps: first the frequency response of the Opamp gain (Aop) will be included, followed by

the frequency response of the Opamps PSR (Gop). For this purpose, a simplified version of

equation 5.41 will be used. Two simplifications are made: RCT

RPTis taken to be much larger

than one and the denominator of the term in brackets is approximated to 1. Hence, the

starting equation for frequency reponse evaluation will be:

PSR =

RCT

RPT

1 + gmp.RPT .Aop.

(gmp.RPT . (1 −Gop) +

RPT

rds

)(5.46)

This equation can be further simplified to:

PSR =RCT

1 + gmp.RPT .Aop

.

(gmp. (1 −Gop) +

1

rds

)(5.47)

To include the Opamp’s frequency response in the PSR equation, Aop will be replaced

by a frequency-dependent Aop(s). To obtain a simple expression that can give design

insight, it will be assumed that the Opamp’s frequency response has a single pole. This

is a reasonable assumption if the Opamp has a high enough phase margin. Hence, Aop(s)

can be expressed by:

Aop (s) =Aop0

1 + sp0

(5.48)

Where:

Aop0 is the DC gain of the Opamp

p0 is the Opamp’s dominant pole


Hence, substituting by the expression of Aop(s) from equation 5.48 into equation 5.47

the frequency dependent PSR(s) can be expressed as:

PSR (s) = RCT

1+gmp.RPT .Aop0

1+ sp0

.(gmp. (1 −Gop) + 1

rds

)

=RCT .

“1+ s

p0

”1+gmp.RPT .Aop0+

sp0

.(gmp. (1 −Gop) + 1

rds

) (5.49)

This can be finally put in the form:

PSR (s) =RCT .

(1 + s

p0

)(1 + gmp.RPT .Aop0) .

(1 + s

p0(1+gmp.RPT .Aop0)

) .(gmp. (1 −Gop) +1

rds

)(5.50)

gmp.RPT .Aop0 represents the DC loop gain and is, thus, much larger than 1. This allows

PSR (s) to be approximated as:

PSR (s) ≈ 1Aop0

.RCT

RPT.((1 −Gop) + 1

gmp.rds

).

“1+ s

p0

”

1+ s

p0(1+gmp.RPT .Aop0)

!

= PSR0.

“1+ s

p0

”

1+ s

p0(1+gmp.RPT .Aop0)

!(5.51)

To obtain the complete frequency dependence for PSR(s), the frequency dependence

of the Opamps’s PSR Gop(s) must be incorporated into equation 5.51. To do so, a single

pole model will be assumed for Gop(s) (in the same manner that was done for the gain

Aop(s)). Hence, Gop(s) will be expressed as:

Gop (s) =Gop0

1 + sps

(5.52)

Where:

Gop0 is the DC value of the Opamp’s PSR

ps is the dominant pole of Gop(s)

Modifying Gop(s) will only change the factor (1 −Gop) + 1gmp.rds

in equation 5.51. The

term (1 −Gop) + 1gmp.rds

will be named K. Hence:


K =(1 − Gop0

1+ sps

)+ 1

gmp.rds

= 1

gmp.rds.(1+ sps

).(1 + s

ps+ gmp.rds + s.gmp.rds

ps−Gop0.gmp.rds

)= 1

gmp.rds.(1+ sps

).(1 + gmp.rds. (1 −Gop0) + s

ps. (1 + gmp.rds)

) (5.53)

Since the term gmp.rds is much larger than one, the term sps. (1 + gmp.rds) will be

approximated to sps.gmp.rds. Thus, K can be approximated as:

K ≈ 1

gmp.rds.(1+ sps

).(1 + gmp.rds. (1 −Gop0) + s

ps.gmp.rds

)=

1+gmp.rds.(1−Gop0)

gmp.rds.(1+ sps

).(1 + s.gmp.rds

ps.(1+gmp.rds.(1−Gop0))

)= 1+gmp.rds.(1−Gop0)

gmp.rds.(1+ sps

).

(1 + s

ps.“

1gmp.rds

+(1−Gop0)”) (5.54)

This equation can be rearranged as:

K =

(1

gmp.rds

+ (1 −Gop0)

).

1 + s

ps.“

1gmp.rds

+(1−Gop0)”(

1 + sps

) (5.55)

Replacing the term(

1gmp.rds

+ (1 −Gop0))

by K0, K can finally be written as:

K = K0.1 + s

ps.K0(1 + s

ps

) (5.56)

By observing the expression of PSR0 of equation 5.45, it can also be expressed in terms

of K0 as:

PSR0 = K0.1

Aop

.RCT

RPT

(5.57)

By combining equations 5.57, 5.56 and 5.51 the complete expression for PSR(s) can

be finally expressed as:

PSR(s) = K0.1

Aop0.RCT

RPT.

(1 + s

p0

).(1 + s

K0.ps

)(1 + s

ps

).(1 + s

p0.(1+LG)

) (5.58)


Where:

K0 is equal to(

1gmp.rds

+ (1 −Gop0))

Gop0 is the DC value of the Opamp’s supply rejection

Aop0 is the Opamp’s open loop DC gain

LG is the loop gain of the CMOS-compatible bandgap and is equal to gmp.RPT .Aop0

p0 is the dominant pole of the Opamp (which is also the dominant pole of the loop)

ps is the dominant pole of the Opamp’s PSR

To validate the expression of equation 5.58, a number of simulations are made with a

behavioral Opamp (the behavioral model is shown in Appendix B). The following obser-

vations and conclusions can be made:

• When the Opamp’s compensation capacitor (Cc) is connected to ground, the dom-

inant pole of both the Opamp’s gain Aop(s) and the Opamp’s PSR Gop(s) will be

identical. Hence, p0 and ps will be equal in equation 5.58. Thus, the PSR(s) equation

will have a single pole and a single zero and will be given by:

PSR(s) = K0.1

Aop0.RCT

RPT.

1 + sK0.ps

1 + sp0(1+LG)

(5.59)

The zero is at a frequency ps.K0. Since K0 is a quantity much smaller than one, the

zero of PSR(s) is at a frequency much lower than the Opamp’s dominant pole. The

pole is at a frequency given by p0 (1 + LG) which is equal to the loop’s unity-gain

frequency. The simulation result of this case is shown in figure 5.13. The DC value of

PSR starts to increase by 20 dB/decade after the 1st zero. The zero, as expected, is at

a much lower frequency than the Loop Gain’s dominant pole. A pole appears in the

PSR response at the Loop Gain’s unity gain frequency (the frequency at which the

Loop Gain is zero dB). Figure 5.13 shows two poles at the unity gain frequency. The

additional pole can be attributed to the capacitance loading the bandgap’s output

(whose effect was ignored in our analysis).

• For the same case where Cc is connected to ground, we can observe from equation

5.59 that improving PSR0 (by decreasing K0) will simultaneously cause a reduction


Figure 5.13: PSR and Loop Gain for Cc connected to ground


of PSR bandwidth (as the zero frequency is equal to K0.ps). In fact, the product of1

PSR0and the PSR bandwidth (i.e. ps.K0) is constant and is given by:

1

PSR0.ps.K0 =

1

PSR0.p0.K0 = p0.Aop0.

RPT

RCT(5.60)

This suggests that there is a constant supply-rejection gain-bandwidth product in

the same manner that an Opamp would have a constant gain-bandwidth product.

Hence, improving PSR0 by varying Gop0 would inevitably result in a reduction in the

PSR bandwidth and vice-versa. Figure 5.14 shows a verification of this result: PSR0

is changed by varying Gop0 with a reduction in PSR bandwidth as PSR0 improves.

Figure 5.14: PSR and Loop Gain for Cc connected to ground

• In reaching equation 5.58, it was assumed that the Opamp’s Gop(s) has a single

pole and no zeroes. This will be true if the compensation capacitor (Opamp’s load


capacitor) is connected to ground. If Cc is connected to Vdd, however, Gop(s) has to

be rederived. Towards this end, consider a capacitor Cc connected between Vout and

Vdd in the model of figure B.1. vout can, thus, be expressed as:

vout = (vdd − vout) .s.Cc.Ro + gmvdd.vdd.Ro

= (vdd − vout) .s.Cc.Ro +Gop0.vdd

(5.61)

Where gmvdd.vdd.Ro was replaced with Gop0. Rearranging the equation, Gop(s) can

be found to be:

Gop(s) = Gop0.

(1 + s.Cc.Ro

Gop0

)(1 + s.Cc.Ro)

(5.62)

Connecting Cc to Vdd will thus create a zero and a pole. The pole-zero pair will

be very close in frequency if Gop0 is close to one (which is the case for single-stage

Opamps with PMOS current-mirror loads [Gupta 04]). Consider the following cases:

– If Gop0 is equal to one, the zero and pole will perfectly cancel each other. In this

case, Gop(s) will be frequency independent (i.e. Gop(s)=Gop0). Hence, equation

5.51 will represent PSR(s) i.e.:

PSR(s) = K0.1

Aop0.RCT

RPT.

1 + sp0

1 + sp0(1+LG)

(5.63)

Hence, the zero in PSR(s) is now located at the Opamp’s dominant pole p0.

Recall that for the case where Cc is connected to ground, the PSR(s) zero is

located at a frequency much lower than p0 (ps.K0, K0<<1). This means that

connecting Cc to Vdd effectively increases the PSR(s) bandwidth by the factor 1K0

without compromising PSR0. This agrees with circuit intuition, since connecting

Cc to Vdd enhances the coupling of vdd to the gate of the PMOS transistor at

higher frequencies. This, in turn, reduces the gmp.vsg current component at

higher frequencies leading to a wider bandwidth. Figure 5.15 shows simulation

results for the case where Gop0 is equal to one, with Cc connected once to ground

and once to Vdd


Figure 5.15: PSR and Loop Gain for Cc connected to Vdd and to ground

– For the case where Gop0 is not equal to one (i.e. less than 0.9), Gop(s) will contain

a zero and a pole. To obtain the complete PSR(s) expression, equation 5.51 has

to be evaluated by substituting the correct Gop(s) expression. Doing so is rather

complex and will yield an equally complex result. Alternatively, we can build on

the intuition of constant supply-rejection gain-bandwidth product to conclude

that Gop0<1 will result in an increase in PSR(s) bandwidth. Simulation results,

shown in figure 5.16, confirm this conclusion

To further validate the conclusions in this section, simulation is made with a real

Opamp. The simple current-mirror Opamp, shown in figure 5.17, is used for this purpose.

Simulations are made with Cc connected to ground and to Vdd. Simulation result for both

cases are shown in figure 5.18. The results show that conclusions and observations made

using the behavioral Opamp model are valid for the real Opamp case.


Figure 5.16: PSR for Cc connected to Vdd at different Gop0

Figure 5.17: Real Opamp used for validation of PSR


Figure 5.18: PSR for Cc connected to Vdd and ground for real Opamp


5.3.6 Noise in the CMOS-compatible Bandgap Circuit

As discussed in section 3.3.3, the reference voltage noise performance limits the maximum

achievable SNR in a ΣΔ-Force Feedback system. Hence, it is of importance to evaluate the

noise perfromance of the bandgap circuit and to identify the contribution of the various

components of the circuit. Figure 5.19 shows the various noise sources in the bandgap

circuit. In the following sections, the contribution of each of these sources to the output

noise will be evaluated. The analysis in this section closely follows [Holman 94].

Figure 5.19: Noise sources in the CMOS-compatible bandgap circuit


5.3.6.1 Opamp Noise Contribution

The AC model used to evaluate the effect of the Opamp noise is shown in figure 5.20. The

small siganl current iout can thus be given by:

Figure 5.20: AC model for noise contribution of vnop

iout = −gmp.Aop. (iout.RPT − vnop) (5.64)

Rearranging equation 5.64, one gets:

iout. (1 + gmp.Aop.RPT ) = gmp.Aop.vnop (5.65)

Hence, iout can finally be approximated as:

iout ≈ vnop

RPT

(5.66)

Thus, the output noise vout can be expressed as:


vout = iout.

(RPT +RCT +

1

gmQ

)=vnop

RPT

.

(RPT +RCT +

1

gmQ

)(5.67)

Finally, vout can be approximated as:

vout ≈ vnop.

(1 +

RCT

RPT

)(5.68)

As seen from equation 5.68, the Opamp’s input noise-voltage is multiplied by the ra-

tio RCT

RPT. This, in effect, amplifies the Opamp’s noise. Since the Opamp is the noisiest

component in the circuit, special care has to be given to its noise spec.

5.3.6.2 RPT Noise Contribution

Figure 5.21: AC model for noise contribution of vnrpt

The AC model used to evaluate the effect of the RPT noise is shown in figure 5.21. The

small siganl current iout can thus be given by:


iout = gmp.Aop. (−iout.RPT − vnrpt) (5.69)

From which iout can be expressed as:

iout =−gmp.Aop.vnrpt

(1 + gmp.Aop.RPT )≈ vnrpt

RPT

(5.70)

Hence, the voltage vout can be expressed as:

vout = iout.

(RPT +RCT +

1

gmQ

)=vnrpt

RPT

.

(RPT +RCT +

1

gmQ

)(5.71)

Hence, vout can be approximated as:

vout ≈ vnrpt.

(1 +

RCT

RPT

)(5.72)

It is to be noted that the noise of RPT is multiplied by the same factor as the noise of

the Opamp. However, the Opamp is noisier since it has more devices. Furthermore, the

noise of the Opamp can be decreased by increasing its current whereas the only way to

decrease the noise of RPT is to decrease RPT itself.

5.3.6.3 RCT Noise Contribution

The AC model used to evaluate the effect of the RCT noise (vnrct1)is shown in figure 5.22.

The small siganl current iout can thus be given by:

iout = −gmp.Aop.iout.RPT (5.73)

This equation can only be valid if iout=0. Hence, vout can simply be expressed as:

vout = vnrct1 (5.74)

Following the same line of reasoning it can be shown that vnrct2 (refer to figure 5.19)

doesn’t contribute to the output noise.


Figure 5.22: AC model for noise contribution of vnrct1


5.3.6.4 Mp1 Noise Contribution

The AC model used to evaluate the effect of the noise of the PMOS transistor Mp1 is shown

in figure 5.23. The small siganl voltage vg can thus be given by:

vg = Aop. (v2 − v1) (5.75)

Where the voltages v1 and v2 can be given by:

v2 = (inmp1 − gmp.vg) .(RPT + 1

gmQ

)v1 = −gmp.vg.

1gmQ

(5.76)

Substituting from equation 5.76 into equation 5.75 and reevaluating vg, it can be found

that:

vg = Aop.

(−gmp.vg.RPT + inmp1.

(RPT +

1

gmQ

))(5.77)

From which vg can be found to be:

vg =inmp1.Aop

1 + gmp.RPT .Aop.

(RPT +

1

gmQ

)(5.78)

Thus, the output voltage vout can now be expressed as:

vout = (inmp1 − gmp.vg)(RPT +RCT + 1

gmQ

)=(inmp1 − gmp.Aop.inmp1

1+gmp.RPT .Aop.(RPT + 1

gmQ

))(RPT +RCT + 1

gmQ

)= inmp1.

(1 − gmp.Aop

1+gmp.RPT .Aop.(RPT + 1

gmQ

))(RPT +RCT + 1

gmQ

)= inmp1.

(1− gmp.Aop

gmQ

1+gmp.RPT .Aop

)(RPT +RCT + 1

gmQ

)(5.79)

Hence, vout can finally be approximated as:

vout ≈ inmp1.1

gmQ

.

(1 +

RCT

RPT

+1

gmQ.RPT

)(5.80)


Figure 5.23: AC model for noise contribution of inmp1

5.3.6.5 Mp2 Noise Contribution

The AC model used to evaluate the effect of the noise of the PMOS transistor Mp2 is shown

in figure 5.24. The small siganl voltages v1 and v2 can thus be given by:

v1 = (inmp2 − gmp.vg) .1

gmQ

v2 = −gmp.vg.(RPT + 1

gmQ

) (5.81)

Thus, the gate voltage vg can be expressed as:

vg = Aop. (v2 − v1)

= −Aop.(gmp.vg.RPT + inmp2.

1gmQ

) (5.82)

From which vg can be finally expressed in the form:

vg =−inmp2.Aop.

1gmQ

1 + gmp.RPT .Aop(5.83)


Hence, vout can be found to be:

vout = −gmp.vg.(RPT +RCT + 1

gmQ

)=

gmp.inmp2.Aop. 1gmQ

1+gmp.RPT .Aop.(RPT +RCT + 1

gmQ

) (5.84)

This can finally be approximated as:

vout ≈ inmp2.1

gmQ.

(1 +

RCT

RPT+

1

gmQ.RPT

)(5.85)

This result is similar to that obtained for Mp1, which is intuitively satisfying given the

symmetry of the circuit.

Figure 5.24: AC model for noise contribution of inmp2

5.3.6.6 Q2 Noise Contribution

The AC model used to evaluate the effect of the noise of the BJT Q2 is shown in figure

5.25. The small siganl current iout can thus be given by:


iout = inq2 + gmQ.vx (5.86)

Figure 5.25: AC model for noise contribution of inq2

Alternatively, iout can be expressed as:

iout = gmp.Aop. (v1 − v2) (5.87)

The voltages v1 and v2 can be given by:

v1 = iout.1

gmQ

v2 = vx + iout.RPT

(5.88)

Thus, the difference (v1 − v2) can be expressed as:

v1 − v2 = iout.

(1

gmQ

− RPT

)− vx (5.89)


Substituting back into equation 5.87, iout can be expressed as:

iout = gmp.Aop.(iout.

(1

gmQ−RPT

)− vx

)⇒ iout = −gmp.Aop.vx

1−gmp.Aop.

„1

gmQ−RPT

« (5.90)

Thus, using equation 5.86 vx can be expressed in terms of iout as:

vx = iout.

(1

gmQ

− RPT

)(5.91)

Thus, iout can now be expressed in terms of inq2 as:

iout =inq2

gmQ.RPT(5.92)

Now, vout can be written as:

vout = vx + iout. (RPT +RCT )

= iout.(

1gmQ

− RPT

)+ iout. (RPT +RCT )

= iout.(

1gmQ

+RCT

) (5.93)

Substituting from equation 5.92 into equation 5.93, vout can finally be expressed as:

vout = inq2.1

gmQ

.

(1

gmQ.RPT

+RCT

RPT

)(5.94)

5.3.6.7 Q1 Noise Contribution

The AC model used to evaluate the effect of the noise of the BJT Q1 is shown in figure

5.26. The small siganl current iout can thus be given by:

iout = inq1 + gmQ.v1 (5.95)

Alternatively, iout can be expressed as:

iout = gmp.Aop. (v1 − v2) (5.96)

The voltage v2 can be given by:


v2 = iout.

(1

gmQ

+RPT

)(5.97)

Figure 5.26: AC model for noise contribution of inq1

Substituting by equation 5.97 into equation 5.96:

iout = gmp.Aop.(v1 − iout.

(1

gmQ+RPT

))⇒ iout ≈ v1„

1gmQ

+RPT

« (5.98)

Thus, v1 can be expressed as:

v1 = iout

(1

gmQ

+RPT

)(5.99)

Substituting back into equation 5.95, iout can be expressed in terms of inq1 as:

iout =inq1

gmQ.RPT(5.100)


Component Noise contribution to the output (V 2rms/Hz)

Opamp v2nop.

(1 + RCT

RPT

)2

RPT 4.kB.T.RPT .(1 + RCT

RPT

)2

RCT 4.kB.T.RCT

Mp1 i2nmp1.1

gm2Q.(1 + RCT

RPT+ 1

gmQ.RPT

)2

Mp2 i2nmp2.1

gm2Q.(1 + RCT

RPT+ 1

gmQ.RPT

)2

Q1 i2nq1.1

gm2Q.(1 + RCT

RPT+ 1

gmQ.RPT

)2

Q2 i2nq2.1

gm2Q.(

1gmQ.RPT

+ RCT

RPT

)2

Table 5.3: Noise Contribution of bandgap circuit components to the output noise

Hence, vout can finally be expressed as:

vout = iout

(1

gmQ

+RPT +RCT

)= inq1.

1

gmQ

.

(1 +

RCT

RPT

+1

gmQ.RPT

)(5.101)

5.3.6.8 Summary and discussion of noise contributions

Table 5.3 summarizes the noise contributions of the components of the bandgap circuit to

the output noise. It is to be noted that the expressions shown are valid for both thermal

and flicker noise.

With the noise contributions of all the components identified, the following observations

can be made:

• The Opamp noise is multiplied by the gain factor(1 + RCT

RPT

)2

. Hence, the Opamp

can easily become the major noise source in the bandgap circuit - in terms of both

flicker and thermal noise

• The noise contribution of the RPT resistor is larger than that of RCT . This can

be observed by approximating the contribution of RPT to 4.kB.T.RPT .(

RCT

RPT

)2

=

4.kB.T.RCT .RCT

RPT. Hence, the RPT noise is larger by the factor RCT

RPT


• The PMOS transistor noise and the bipolar transistor noise see roughly the same

transfer function to the output. Moreover, their noise currents are multiplied by

the fairly low-impedance 1gmQ

reducing their effect in comparison to the other terms.

Since gmQ = Ic

VT, increasing current would reduce 1

gmQand, hence, reduce the effect

of the PMOS and bipolar transistors on output noise. It is to be noted, however,

that for thermal noise increasing current would reduce the PMOS noise by a greater

factor than the bipolar noise (i2nqThermal ∝ Ic whereas i2nmpThermal ∝√Ic)

• A possible thermal noise optimization strategy (for reaching a specific noise power

spectral density) is:

– Start by minimizing the Opamp noise, then

– If the major noise contributor is RPT , then RPT has to be reduced

– If the major noise contributor is the bipolar transistor, then, again, RPT has to

be reduced (to increase Ic)

– If the major noise contributor is the PMOS transistor, then its transconductance

(gmp) can be reduced by reducing its WL

ratio

5.3.7 Mismatch errors in the CMOS-compatible Bandgap Cir-

cuit

In the context of the bandgap reference, there are four major sources of mismatch errors:

1. The Opamp’s input-offset voltage

2. The mismatch between the PMOS current sources

3. The mismatch between the Bipolar transistors

4. The mismatch between the RPT and RCT resistors

Each of these sources adds an error to the output bandgap voltage. In the following

sections, the errors caused by each source will be analyzed


5.3.7.1 Effect of Opamp’s input-offset voltage

Consider an Opamp which has an input-offset voltage Vos. The effect of this offset on the

bandgap output can be found by replacing Vop by Vos in figure 5.10 [Razavi 01]. Doing so,

and following the same procedure used in section 5.3.4 the output bandgap voltage can be

expressed as:

Vout = Vbe1 +RCT

RPT. (VT . ln (N) + Vos) (5.102)

Figure 5.27: Bandgap with Chopped Opamp

As can be seen from equation 5.102, the Opamp’s input offset voltage is amplified at the

output by the factor RCT

RPT(a factor of almost 10 for N=8). Hence, the Opamp’s input-offset

voltage is a major source of error in bandgap reference. While Vos in equation 5.102 is


assumed constant, it will be temperature and time dependent in practice. This means that

it can contribute significant error - not only to the bandgap’s absolute value - but also to

its temperature curvature and long-term drift. It is to be noted that Opamp’s with bipolar

input pairs will have smaller offset voltages than their CMOS counterparts [Sansen 06].

Besides, the offset of a bipolar pair has a more-predictable (PTAT) temperature behavior

[Sansen 06].

To minimize the effect of the Opamp’s offset, chopping can be performed around the

Opamp as shown in figure 5.27 [Sanduleanu 98] [Lian-xi 05] [Jiang 05] [Fruett 03]. This

has the added advantage of reducing the effect of the Opamp’s flicker noise at the bandgap

output.

5.3.7.2 Effect of mismatch of PMOS current sources

With mismatch in the PMOS current sources, the two branches of the bandgap circuit

will have unequal currents as shown in figure 5.28. With a current I flowing in Mp2 and a

current I+ΔI flowing in Mp1, the voltages Vbe1 and Vbe2 can be expressed as:

Vbe1 = VT . ln(

I+ΔIIs1

)Vbe2 = VT . ln

(I

Is2

) (5.103)

Where Is1 and Is2 are the reverse-saturation currents of transistors Q1 and Q2, respec-

tively. Hence, the PTAT voltage ΔVbe can now be expressed as:

ΔVbe = Vbe1 − Vbe2

= VT . ln(

Is2Is1. I+ΔI

I

)= VT . ln

(N.(1 + ΔI

I

))= VT . ln (N) + VT . ln

(1 + ΔI

I

) (5.104)

Hence, the bandgap output voltage with PMOS mismatch can now be expressed as:

Vout = Vbe1 +RCT

RPT.VT . ln (N) +

RCT

RPT.VT . ln

(1 +

ΔI

I

)(5.105)

Hence, the mismatch ΔII

between the PMOS current mirrors adds a PTAT error term

that is proportional to ln(1 + ΔI

I

). Note that ln (1 + y) ≈ y for small y. Hence, the error


term can be approximated as ΔII.VT .

RCT

RPT. Hence, the approximate value for the erroneous

bandgap voltage as a result of PMOS mismatch will be given by:

Vout ≈ Vbe1 +RCT

RPT.VT . ln (N) +

RCT

RPT.VT .

ΔI

I(5.106)

With typical 3σ values of 1% for ΔII

[Gupta 07], the error term due to mismatch will

be equal to around RCT

RPT. VT

100. This is a hundred times smaller than the PTAT term and,

hence, will contribute negligible error to the output.

Figure 5.28: Bandgap with mismatch in PMOS current mirror

The variance of the random error ΔII

(i.e. σ2(

ΔII

))is given by [Sansen 06]:

σ2

(ΔI

I

)= σ2

(Δβ

β

)+

4.σ2 (ΔVth)

(Vgs − Vth)2 (5.107)

Where β = μ.Cox.WL

(μ being the transistor’s mobility, Cox its oxide capacitance per

unit area and WL

its aspect ratio) and σ (ΔVth) is the standard deviation of the threshold

voltage mismatch ΔVth.


Hence, to improve the matching accuracy the two terms of equation 5.107 need to be

minimized. The 2nd term can be minimized by increasing the transistor’s overdrive voltage.

The first term, on the other hand, can be minimized by reducing the σ(

Δββ

). This can be

done by increasing the transistor’s area (σ(

Δββ

)∝ 1√

W.L) [Hastings 00] [Sansen 06].

It is to be noted that random mismatch is not the only source of the current mis-

match ΔI. Systematic mismatch in the Vds voltage of the two PMOS mirror devices can

contribute to current mismatch, due to the finite output impedance of MOS current mir-

rors [Sansen 06]. For this very reason, the resistor RCT was placed in each of the two

branches of the bandgap circuit. This is not essential for the operation of the circuit. Nev-

ertheless, it helps decrease the systematic mismatch between the Vds’s of the two PMOS

current mirrors. However, even with RCT present in both branches there will still be sys-

tematic mismatch since nodes 1 and 2 do not possess the same voltage (as a consequence

of the finite Opamp gain).

5.3.7.3 Effect of mismatch of the BJT transistors

Figure 5.29: Bandgap with mismatch in BJT’s


BJT mismatch will result from mismatch in the saturation current Is [Gupta 07]. Hence,

if Q1 has a saturation current Is and Q2 has a mismatched saturation current Is + ΔIs,

then Vbe1 and Vbe2 (refer to figure 5.29)can be expressed as:

Vbe1 = VT ln(

IIs

)Vbe2 = VT ln

(I

N.(Is+ΔIs)

) (5.108)

Following the same analysis performed in section 5.3.7.2, the output bandgap voltage

with BJT mismatch can be expressed as:

Vout = Vbe1 +RCT

RPT

.VT . ln (N) +RCT

RPT

.VT . ln

(1 +

ΔIsIs

)(5.109)

This equation takes the same form as equation 5.105 and the same conclusions made

on equation 5.105 can be drawn. Furthermore, the term ΔIs

Isof the BJT is typically smaller

then the ΔII

of PMOS transistor [Sansen 06]. Hence, it will have a less pronounced effect.

5.3.7.4 Effect of resistor mismatch

If the resistor RPT is made up of a unit resistor Runit, the resistor RCT should, ideally,

be made up of the same unit resistor Runit. Hence, if the desired RCT

RPTratio is X then ,

ideally, RCT = X.Runit. However, due to mismatch the resistor RCT will be made up of

the mismatched unit resistor Runit + ΔRunit. The output bandgap voltage with resistor

mismatch will, thus, be given by:

Vout = Vbe1 +X.VT . ln (N) +X.ΔRunit

Runit.VT . ln (N) (5.110)

Where the ideal bandgap voltage is given by:

Vout = Vbe1 +X.VT . ln (N) (5.111)

Hence, resistor mismatch adds a PTAT error term in the same manner that BJT and

PMOS-mirror mismatch do. Since resistor matching can be done to an accuracy of 1% (or

even 0.1% with careful matching) [Gupta 07], it can be concluded that resistor mismatch

has negligible effect.


Figure 5.30: Bandgap with mismatch in resistors


5.4 Bandgap Reference Voltage Implementation

In the following sections, three different implementations of the bandgap circuit will be

presented and discussed, and their simulation results will be shown. The first circuit is the

direct implemenation of the CMOS-compatible bandgap circuit. However, modifications

were needed to achieve the low-noise target in the low-frequency range (plagued by 1/f

noise). The second circuit exploits the use of Bipolar transistors to achieve a low flicker

noise performance (recall that the technology at hand is a SiGe BiCMOS technology). In

the third circuit, a new higher-order temperature compensation circuit is presented.

5.4.1 Conventional Bandgap Reference: circuit 1

The schematic of the first circuit implementation is shown figure 5.31. The circuit operates

from a 2.4V supply, consuming 585μA. The estimated area of this circuit is 570μm×570μm.

5.4.1.1 Circuit 1: Bipolar transistor choice

Vertical (substrate) PNP transistors are used for the reasons discussed in section 5.3.1.

The ratio N = 8 is used to allow a symmetric common-centroid layout of the Bipolars as

shown in figure 5.32 [Mok 04]. Moreover, increasing N doesn’t help much in increasing the

slope of the PTAT voltage since it appears inside the argument of a logarithmic function.

Thus, N has to be increased by a very large amount to achieve a significant change. This

makes N = 8 a favorable choice

5.4.1.2 Circuit 1: Opamp choice and biasing

To achieve a high loop gain without compromising noise, the noise- (and power-) efficient

telescopic Opamp is used. It is a single-stage Opamp that can be easily compensated by its

load capacitance [Razavi 01]. To have the Opamp’s PSR close to one (which is required for

high overall rejection), the input pair uses NMOS transistors with a PMOS current-mirror

load (refer to section 5.3.5).

5.4. Bandgap Reference Voltage Implementation 131

Figu

re5.31:

Sch

ematic

forcircu

it1

(startup

not

show

n)


Figure 5.32: Common-Centroid Layout of BJT’s with 1:8 ratio

5.4.1.2.1 Noise Considerations in Opamp Design As discussed in section 5.3.6.1,

the Opamp’s input-referred noise voltage is effectively multiplied by the factor 1 + RCT

RPT

which is equal to about 9 for this specific implementation. For the telescopic Opamp

shown in figure 5.31, the total input-referred thermal noise power spectral density (in

V 2/Hz) can be given as:

v2nop th ≈ 8

3.

kT

gmMnt1,2

∗ 2 +8

3.kT.gmMpt1,2

gm2Mnt1,2

∗ 2 (5.112)

And the total input-referred flicker noise power spectral density can be given as [Sansen 06]:

v2nop f ≈ K

(W.L)Mnt1,2 .Cox.f∗ 2 +

K

(W.L)Mpt1,2 .Cox.f.gm2

Mpt1,2

gm2Mnt1,2

∗ 2 (5.113)

To decrease the Opamp’s noise, the following measures are taken:

• A large current is allocated to the Opamp (large enough to make the Opamp a non-

dominant noise source). This allows achieving a high transconductance in the input

pair (gmMnt1,2). This, in turn, reduces the overall input-referred noise voltage of the


Opamp. For thermal noise, a high gmMnt1,2 will reduce the contribution of both the

NMOS and the PMOS transistors to the opamp’s input-referred noise. For flicker

noise, however, it only reduces the contribution of the PMOS transistors

• The WL

ration of the input pair is increased to increase gmMnt1,2. To achieve the

maximum possible gm for a fixed current, the transistors should be operated in the

subthreshold (weak-inversion) region [Vittoz 03]). However, doing so at the chosen

current level would result in large sizing for the NMOS pair, which would,in turn,

result in large gate capacitance. This would cause stability problems when chopping

is used (refer to section 5.4.1.9.4). Hence, the transistors are sized to operate on the

verge of the weak-inversion region (i.e. still operating in saturation but with very

small overdrive voltage Veff)

• The transconductance of the PMOS current-mirror transistors (Mpt1 & Mpt2) was

minimized to reduce their contribution to the Opamp’s input-referred noise. This

has two other advantages: it reduces their contribution to the Opamp’s input-offset

voltage and it decreases the mismatch between them [Sansen 06]

• The W.L product of the PMOS transistors (Mpt1 & Mpt2) and the NMOS transistors

(Mnt1 & Mnt2) is increased to lower flicker noise. This has the added advantage of

reducing the mismatch [Hastings 00] and, hence, the Opamp’s input-offset voltage

5.4.1.2.2 Self-Bias Loop for the Opamp To obtain the Opamp’s tail current, vari-

ous techniques can be used. Two reasonable techniques are:

1. Using a separate, simple current-generation circuit (such as a constant-gm circuit)

to provide the tail current for the Opamp as shown in figure 5.33(a). This, however,

adds extra area and power-consumption. Besides, constant-gm circuits exhibit large

variations in current across process corners (since Iconstgm ∝ 1R2 ) [Razavi 01]

2. Another possible option - which is more area-efficient - is to use a simple resistor

tied to the supply (Vdd) on one end and to a diode connected NMOS transistor on

the other end as shown in 5.33(b). This, however, makes the current prone to the


process variations of the NMOS transistor and the resistor as well as to the supply

(Vdd) variations

Large variations in the Opamp’s tail current can be troublesome as they may disrupt

the designed DC operating points of the Opamp transistors, with some transistors going

into the linear region. This, in turn, causes a large reduction in the Opamp’s gain.

(a) Constant-gm biasing (b) Resistor biasing

Figure 5.33: Possible solutions for biasing the Opamp

Another possible option - which provides a more controlled currrent - is to use the

current generated by the bandgap core itself. An illustration of this idea is shown in figure

5.34. The current in transistors Mp1&Mp2 is mirrored by the PMOS transistor Mpsb. This

current is mirrored back to the Opamp’s tail current source providing the necessary tail

current. Noting that the bandgap core’s current is PTAT (≈ VT . ln (N)RPT

), the Opamp’s bias

current will also be PTAT.

While this solution is attractive - saving area and reducing susceptibility to process

variations - it might impose a stability issue. This can be observed by refering to figure

5.34. It can be seen that the self-bias loop is actually a positive feedback loop. To avoid

instability, the loop gain of the self-bias loop should be well below unity over all the

frequency range. To gain understanding of the self-bias loop, qualitative analysis of the

loop is performed at DC and at very high frequencies (based on the discussion in [Perry 07]):


Figure 5.34: Self-bias for the Opamp in circuit 1

• At DC, the small signal current imnt0 is divided evenly between the two input tran-

sistors (Mnt1 & Mnt2). The PMOS load mirrors the current in Mnt1, so that the total

small signal current in the Opamp’s output branch sums to zero. This makes the

gain from the Opamp stage zero and, hence, the overall positive feedback gain will

be very small (ideally zero)

• At high frrequencies, the capacitor CM (which represents the parasitic capacitance

at the diode connection) becomes a short circuit. Thus, it shunts the current imnt0

2

in the diode-connected branch to ground. Thus, the current in the output branch is

not cancelled anymore and the gain increases. The presence of a large capacitor at

the output can help reduce this gain so that it never reaches unity

Simulation of the self-bias loop gain is shown in figure 5.35. The loop gain is well below

unity over the whole frequency range, which ensures that the loop is stable.


Figure 5.35: Self-bias Loop Gain

5.4.1.2.3 Bias of the cascode transistors The circuit shown in figure 5.36 is used

to bias the PMOS cascode transistors [Gray 01]. Transistor Mpct is matched to transistors

Mpt3&Mpt4. Thus, transistors Mpct, Mpt3 and Mpt4 have the same current density (i.e. the

same I

W/Lratio) and, hence, the same overdrive voltage Veff . The source-drain voltage

Vsd lin of Mplin is given by:

Vsd lin = Vdd − (Vcp + Veff + Vthp) (5.114)

The source-gate voltage Vsg of Mlinp is given by:

Vsg = Vdd − Vcp (5.115)

Hence, for Mplin, Vsd < Vsg − Vth and it operates in the linear region. By adjusting theWL

ratio of Mlinp, its Vsd lin can be adjusted as desired. This will be the same as Vsd of

transistors(Mpt1&Mpt2)


Figure 5.36: Bias of the PMOS cascodes

To bias the NMOS cascode transistor, the circuit shown in figure 5.37 is used. Transistor

Mnct is matched to transistors Mnt3&Mnt4 and has the same current density, and hence the

same overdrive voltage Veff . With the arrangement shown in figure 5.37, the voltage at

the drain of the input NMOS transistor will be equal to VbeB (the Vbe of the bipolar used

for cascode biasing). Hence, the drain and gate voltage of input NMOS transistor will be

very close ensuring that it does not enter thr linear region with process variations.

It is worth noting that the bias bipolar transistor can be selected from the dummy

transistors that surround the bipolar transistor area Q1 and Q2 (for best matching per-

formance, dummy devices are used in layout to assure that all transistors ”see” the same

surroundings [Hastings 00]). This is illustrated in figure 5.38.

5.4.1.3 Circuit 1: PMOS current-mirror and resistors

Since minimum supply voltage is 2.4 V and the bandgap voltage is in the range of 1.2 V,

the Vsd on each of the PMOS current mirrors will be more than 1.2 V. This is a fairly large

value which always cascodes to be used comfortably. While troublesome in their biasing,

cascodes provide the advantage of decreasing the systematic current mismatch between the

two transistors (Mp1&Mp2) as it equalizes the Vsd of both transistors. Besides, cascoding

improves the current mirror output impedance which helps in improving the circuit’s supply


Figure 5.37: Bias of the NMOS cascodes

Figure 5.38: Bandgap’s BJT’s with dummies


rejection. The additional RCT resistor in the Mp2 transistor’s current branch ensures an

even better matching of Vsd’s. The cascode transistors are biased by the same technique

that was used for the Opamp’s cascodes.

The resistors used are base poly resistors, which have the smallest process variation

and temperature drift in the used technology [aus 04b]. To achieve best matching, RPT

and RCT are made up of the same unit resistance [Hastings 00].

5.4.1.4 Circuit 1: Startup circuit

Bandgap circuits require startup circuitry to ensure they will operate as expected [Razavi 01].

The startup circuit used for circuit 1 is shown in figure 5.39. This startup circuit is adopted

from [Khan 03], with some modification. The operation of the circuit can be explained as

follows:

Figure 5.39: Startup circuit for circuit 1


• When the supply is powered on, the output voltage Vbg is initially zero. Hence,

transistor Mst1 is turned off and its output is pulled to Vdd by the pull-up resistor

Rst. This, in turn, means that transistor Mst2 is turned on, pulling the gates of the

PMOS transistors Mp1 and Mp2 to ground. This ensures that there will be current

flowing through the circuit in the startup phase, avoiding the zero solution

• When Vbg reaches its steady state value, Mst1 is turned on and its output is zero.

Thus, Mst2 is off, allowing the voltage at the gates of Mp1 and Mp2 to take its correct

value. In this case, the current dissipated by the startup circuit is that flowing in Rst.

Hence, Rst is made large to dissipate a small current. For this specific implementation,

the steady state current in Rst is around 10μA

5.4.1.5 Circuit 1: DC performance

Figure 5.40: Circuit 1: Output voltage versus Temperature

Figure 5.40 shows the output bandgap voltage Vbg versus temperature. With a 1st


order compensation, the circuit achieves a total variation across temperature of 3.9mV,

corresponding to a temperature coefficient (tempco) of approximately 20ppm/◦C.

5.4.1.6 Circuit 1: Supply rejection

The PSR (i.e. vout

vdd) of the circuit at the node Vbg is shown in figure 5.41. The guidelines

presented in section 5.3.5 were taken to achieve an acceptable performance (specifically the

use of cascodes to increase PMOS output impedance and the use of a compensation capac-

itor that is tied to Vdd). Nevertheless, the PSR performance degrades at high frequencies

due to the presence of a zero in the PSR transfer function. To improve rejection at high

frequencies, a simple R-C filter is added following Vbg [Gupta 07] [Wang 06]. Care is taken

to ensure that this filter doesn’t degrade the noise or stability of the circuit.

Figure 5.41: Circuit 1: Supply Rejection


5.4.1.7 Circuit 1: Loop Stability

Circuit 1 achieves a phase margin of 77◦ and a gain margin of 16dB. To achieve this

performance, a compensation capacitor of 40pF is inserted between the Opamp’s output

node and Vdd. The capacitor is implemented by using a PMOS transistor as a capacitor.

It is to be noted that the added R-C filter doesn’t degrade stability. In fact, it can help

improve stability. To illustrate this, consider figure 5.42 which shows the small signal model

of the output branch. The voltage vbg can be expressed as:

vbg = iout.Req

(Rf + 1

sCf

)Req +Rf + 1

sCf

(5.116)

Where Req is the equivalent AC resistance seen into the drain of the PMOS transistor.

Figure 5.42: Effect of filter on stability

Equation 5.116 can be rearanged to take the form:

vbg = iout.Req(1 + sCfRf )

1 + sCf (Rf +Req)(5.117)


Hence, the filter adds a zero and a pole. If Rf >> Req, the zero and pole frequency will

be close and hence cancel each other. Noting that any load capacitance would be added

in parallel to Cf , it can be seen that the filter can help improve the circuit’s stability

performance in the presence of capacitive loading. The gain and phase response of the

circuit are shown in figure 5.43.

5.4.1.8 Circuit 1: Noise Performance

Figure 5.44 shows the output noise power spectral density of output bandgap voltage. It

can be noted that:

• The circuit achieves a noise power spectral density of 2.5nV/√Hz at 400 KHz (after

the output filter).

• The noise power spectral density in the low frequency range (1mHz - 100Hz) is much

higher. The total integrated noise in the 1mHz - 100Hz range is 6μV approximately,

which is about 6 times the higher than the required value of 0.9μV

Table 5.4 shows the major noise contributors in the 1mHz - 100Hz range (obtained

using Spectre R© circuit simulator). Clearly, the flicker noise of the Opamp transistors is

the major contributor to noise in this range of interest. Hence, it is of great value if the

Opamp’s flicker noise can be reduced, which will be discussed in the following sections.

Transistor Noise Type Noise contribution %

Mnt1 flicker 43

Mnt2 flicker 43

Mpt1 flicker 5

Mpt2 flicker 5

Table 5.4: Major Noise Contributors in Circuit 1


(a) Gain

(b) Phase

Figure 5.43: Gain and Phase Response for Circuit 1


Figure 5.44: Circuit 1: Noise PSD


5.4.1.9 Circuit 1: Using a Chopped Opamp

As shown in the previous section, the Opamp’s flicker noise is the major source of noise in

the low frequency range of interest. One possible solution to reduce the Opamp’s flicker

noise is to use chopping around the Opamp. This has the added advantage of reducing the

effect of the Opamp’s input-offset voltage [Sanduleanu 98] [Lian-xi 05] [Jiang 05].

To understand the effect of chopping, consider figure 5.45. The amplifier’s input signal

is multiplied by a square wave with frequency fchop, modulating the input signal into

a higher frequency. Hence, the amplifier effectively ”sees” the input signal modulated

on a carrier. On the other hand, the amplifier’s flicker noise (& offset) reside in lower

frequencies. This can be regarded as a form of frequency-division multiplexing between

the input signal and the amplifier’s low frequency noise components. At the amplifier’s

output, the amplified input signal is de-chopped (i.e. demodulated) by the same square

wave, whereas the amplified low frequency noise is modulated into a higher frequency. A

filter can then be used to get rid of the unwanted noise in the higher frequency band.

Figure 5.45: Illustrating chopping

5.4.1.9.1 Choosing the chopping frequency To choose the proper chopping fre-

quency, two factors have to be taken into consideration:

1. The input signal is modulated onto the chopper frequency before getting amplifica-

tion. Hence, the input signal is effectively present at the chopping frequency. Thus,


care must be taken that the chopping frequency lies within the system’s flat-gain

region. Two cases can be differentiated in this regard:

Figure 5.46: Chopped noise spectrum

(a) If the Opamp is operated in open-loop (which is not our case), the chopping

frequency must be less than the Opamp’s dominant pole frequency (if the max-

imum Opamp gain is to be exploited)

(b) If the Opamp is operated in a closed-loop (which is our case), the chopping

frequency must lie within the bandwidth of the closed loop or, alternatively,

within the unity gain frequency of the system’s open loop gain

2. The flicker noise is modulated onto the chopper frequency. Hence, if the flicker noise

is to be totally eliminated, the chopping frequency must be high enough to ensure

that the flicker noise tail doesn’t appear in the bandwidth of interest(as shown in

figure 5.46). This can be formally expressed as:

fchop − fcorner > fBW (5.118)

Where:

fchop is the chopping frequency

fcorner is the flicker noise corner

fBW is the desired bandwidth


Since the system’s clock is 409.6kHz, using a chopping frequency of 409.6kHz or its

dividends is possible. This is further discussed in the following section (section 5.4.1.9.2).

5.4.1.9.2 Effect of Chopped Offset on SNR The Opamp’s input offset will cause

the generation of a square wave at the chopping frequency. The amplitude of this square

wave can be shown to be equal to Vos ∗(1 + RCT

RPT

). Monte-Carlo simulations show that

the 3σ equivalent offset at the Opamp’s input is about 0.6mV (figure 5.47).Thus, the

reference voltage to the ΣΔ Force-Feedback loop will be a constant DC voltage with a

super-imposed square wave (representing the chopped offset voltage). Since the feedback

voltage is the multiplication of the reference voltage and the ΣΔ output bit-stream, the

presence of a square wave component may cause the ΣΔ out-of-band noise to fold into the

in-band region. To assess the effect of this ”spur” on the system’s performance, two cases

are considered: fchop = 409.6kHz (i.e. fchop = ΣΔ Clock frequency) and fchop = 204.8kHz

(i.e. fchop = 12ΣΔ Clock frequency)

Figure 5.47: Monte-Carlo Simulation results for Offset

The output of the bandgap with a chopping clock is shown in figure 5.48. As expected,

the output is the dc bandgap value (1.2V ) with a square-wave super-imposed with an


amplitude of 20mVpp (corresponding to Vos ∗ RCT

RPT)3. Simulations are made on the ΣΔ

Forcre Feedback system using an ideal reference (i.e. with no chopping) and the reference

chopped at 409.6kHz, and 204.8kHz (and not filtered). The output spectra for the three

cases are shown in figure 5.49

Figure 5.48: Output bandgap with chopping (unfiltered)

Choosing a chopping frequency equal to the ΣΔ clock frequency has no effect on the

output SNR. This can be qualtitatively explained by the fact that, for each ΣΔ clock

cycle, the chopped bandgap alternates between Vbg + Δv and Vbg − Δv, averaging to Vbg

over each cycle. Hence, the ΣΔ loop effectively ”sees” a DC voltage and is insensitive

to the super-imposed square wave. On the other hand, choosing a chopping frequency

equal to half of the ΣΔ clock frequency leads to a severe degradation in SNR (as can

be observed in figure 5.49). With a frequency equal to half the ΣΔ clock frequency, the

chopping square wave will have a spur in the frequency domain at fs

2, coinciding with

the point that has the highest out-of-band noise in the ΣΔ output spectrum. Since the

reference voltage is effectively multiplied by the output bit-stream to form the feedback

force, the presence of this spur leads to down-conversion of large out-of-band noise back

to DC causing severe SNR degradation. Following the same line of reasoning, choosing a

smaller chopping frequency might cause a similar noise folding effect, as the out-of-band

3Vos is set to 1mV in this simulation


noise is high over a relatively wide frequency range. Using a very low chopping frequency

will violate the condition of equation 5.118, making it ineffective in reducing flicker noise.

Hence, choosing fchop = fs is the best choice for preserving the SNR.

Figure 5.49: Effect of chopping on ΣΔ Output

The above simulations are performed using NRZ pulse shape. For a 50% RZ pulse

shape, the chopping frequency should be increased to 2 × fs i.e. 819.2kHz.

5.4.1.9.3 Chopping configurations Two configurations are possible for implemen-

tation of the chopping solution. The two configurations are shown in figure 5.50.

• The configuration shown in figure 5.50(a) [Sanduleanu 98] has a set of switches at

the input of the Opamp that chop the input signal to the chopping frequency fchop.

The de-chopping (demodulation) is performed by switches in series with the Opamp’s

cascode transistors. The de-chopping effectively inverts the Opamp’s output polarity

whenever the input is inverted, so that the feedback remains negative throughout the

chopping operation. It is to be noted that the de-chopping switches are connected

to the sources of the cascode transistors. Hence, they see a low impedance ( 1gm

)


(a) Configuration of [Sanduleanu 98] (b) Configuration of [Lian-xi 05] [Jiang 05]

Figure 5.50: Chopping Configurations

with a well-defined potential. This is an advantage for the switch. On the other

hand, having the switch in series with the Opamp’s cascode transistors may impose

a limitation specially if a large current is used in the Opamp. The switch’s IR drop

must be low enough in order not to affect the DC operating point of the Opamp’s

transistors

• The configuration shown in figure 5.50(b) [Lian-xi 05] [Jiang 05] is similar to the first

one when it comes to the input chopping switches. However, the output chopping

switched are not placed in series with the Opamp’s transistor. Hence, they do not

affect the Opamp’s DC operating point

Due to the low noise, and large current used in the Opamp, the second configuration

(figure 5.50(b)) is used.

5.4.1.9.4 Effect of switches on Stability In the chosen chopping configuration (fig-

ure 5.50(b)), there will always be a switch in series with the Opamp’s input pair. Since


the Opamp’s input pair has a large size (for offset and flicker noise reduction), the input

pair’s gate capacitance is high. The switch and the gate capacitance represent a series R-C

section and, hence, add a pole to the open loop gain. If the switch resistance is high, this

pole can be low enough to harm the stability (i.e. reduce phase and gain margins) of the

loop. Hence, care has to be taken in switch sizing.

(a) Filter directly after Opamp (b) Filter at final output

Figure 5.51: Post-chopping filtering options

5.4.1.9.5 Filtering the Chopped reference The offset and flicker noise are mod-

ulated onto the high frequency chopping signal. The effect of offset is more pronounced

as it is a larger signal. A filter is, thus, needed to remove this high frequency noise. An

important thing to consider is where to place this filter. Two options are viable:

1. The filter can be placed at the Opamp’s output (directly after de-chopping) as shown

in figure 5.51(a). This is a common practice. However, for the chopped-bandgap it

will impose a problem. The Opamp in the chopped-bandgap circuit is placed inside

a feedback loop. In absence of the filter, the feedback adjusts the amplitude of the


modulated offset such that, after it is demodulated by the Opamp’s input choppers,

it cancels the Opamp’s input offset (the input to the Opamp has to be very small

or othersiwse the Opamp will saturate). The filter at the Opamp’s output opens

the feedack path, preventing this cancellation. The Opamp’s input offset may, thus,

cause saturation of the Opamp’s output

2. The filter can be placed at the output of the feedback loop as shown in figure 5.51(b).

This overcomes the problem of opening the feedback path of the offset signal and,

hence, allows better performance. This option is adopted in this work

Figure 5.52: Noise on the bandgap (after filter)

5.4.1.9.6 Noise Performance of the Chopped bandgap Figure 5.52 shows the

output noise of the bandgap reference with and without chopped Opamp (simulations per-

formed using SpectreRF R©). The low-frequency noise power spectral density has decreased

significantly from the un-chopped case. The total integrated noise voltage in the 1mHz -


100 Hz region is 0.97μV . The dominant noise source in this region is the bipolar transistor.

It is to be noted that after chopping the Opamp, the dominant flicker noise sources will

be the PMOS mirrors and the Bipolars. By design, the PMOS current mirrors are made

non-dominant. Hence, the dominant flicker noise source will be the bipolar transistors

(which is the minimum limit that this circuit can reach)

5.4.1.10 Circuit 1: Trimming for Temperature Coefficient

Process variations will change the parabolic characteristics of the bandgap voltage from the

one designed at typical conditions. Hence, provisions must be made to enable the trimming

of the reference back to the ideal characteristics to achieve the minimum possible variation

of bandgap voltage across temperature. If 1st order temperature compensation is used,

there will be a single voltage value that achieves the best performance across temepera-

ture (the so-called ”magic voltage” Vmagic) [Rincon-Mora 06] [Gupta 07] [Pease 90]. The

trimming process can, thus, be simply done by a single-point trimming for the value of the

bandgap voltage to reach Vmagic. A detailed method for obtaining the value of Vmagic for a

1st-order compensated bandgap reference can be found in [Rincon-Mora 06].

Trimming can be done by changing the PTAT voltage. This, in turn, can be done by

several methods:

1. Changing the value of RCT using a digital word [Gupta 07]. In this case, RCT would

be composed of a fixed part and a trimmable part as shown in figure 5.53. The

trimmable part can be implemented as shown in figure 5.53; the digital word controls

MOS switches that shunt the resistors. This approach will impose a problem if a

relatively high trimming resolution is needed. A high trimming resoluton translates

to a small value for the trim resistor. This, in turn, means that an even smaller

resistance is needed for the MOS switch. For low-noise operation, RCT would be

small and a high resolution would translate to a prohibitively small value for the

MOS on-resistance

2. Changing the value of RCT using laser-trimming. Laser trimming can be used to

change the dimensions of the resistor RCT and, hence, its value. High accuracy can


Figure 5.53: Digital trimming of RCT (3-bit example)

Figure 5.54: Trimming by changing PMOS mirror ratio


be achieved by this method. The problem with laser-trimming, however, is its high

cost [Gupta 07]

3. Changing the current-mirroring ratio of the PMOS mirror. Instead of a 1:1 ratio, a

ratio of 1:1+ΔM can be used. This can be done by dividing transistors Mp1 and Mp2

into a number of fingers (Nfing). With no trimming, the number of fingers of Mp1 is

equal to that of Mp2 and both are equal to Nfing (i.e. Nmp1 = Nmp2 = Nfing). To

trim, extra fingers Ntrim are connected in parallel to either Mp1 orMp2. Fingers added

to Mp2 will increase the PTAT voltage, whereas adding fingers to Mp1 decreases the

PTAT voltage. The voltage Vout in figure 5.54 can be expressed as:

Vout = Vbe1 +RCT

RPT.VT . ln

(N.Nmp2

Nmp1

)(5.119)

This is basically the same as equation 5.14 but replacing M byNmp2

Nmp1. The above

equation can be further expanded into:

Vout = Vbe1 +RCT

RPT

.VT .

(ln (N) + ln

(Nmp2

Nmp1

))(5.120)

Hence, if fingers are added to Mp2 then Nmp2 = Nfing + Ntrim. Hence, Vout can be

expressed as:

Vout = Vbe1 + RCT

RPT.VT .

(ln (N) + ln

(Nfing+Ntrim

Nfing

))= Vbe1 + RCT

RPT.VT .

(ln (N) + ln

(1 + Ntrim

Nfing

)) (5.121)

Since Ntrim

Nfingwill be typically smaller than one, ln

(1 + Ntrim

Nfing

)can be approximated to

Ntrim

Nfing. With this approximation, Vout would be expressed as4:

Vout = Vbe1 +RCT

RPT.VT .

(ln (N) +

Ntrim

Nfing

)(5.122)

4based on the assumption that: Nmp2 = Nfing + Ntrim and Nmp1 = Nfing. If Nmp1 = Nfing + Ntrim

and Nmp2 = Nfing, a negative sign should be added to Ntrim

Nfing


To see why this can achieve a high resolution, consider the case of Ntrim

Nfing= 1

10. If

N = 8, ln (N) will be almost equal to 2. Hence, the relative increase in the PTAT

voltage will be approximately 5%. If RCT trimming is used, then with an RCT of

5KΩ, achieving a 5% change in PTAT voltage would require adding a resistance of

250Ω in series. This, in turn, means that the on resistance of all the switches in series

with the 250Ω must be significantly less than 250Ω e.g. 25Ω which is an impractical

value

Based on the above discussion, the 3rd option was chosen. With Nfing = 40, simulations

show that the maximum required value for Ntrim is 16. A similar technique was adopted for

trimming in [Perry 07]. Figure 5.55 shows the trimmed and untrimmed bandgap voltage

for the corner with worst variation across temperature (fastest CMOS, smallest resistors,

lowest-β BJT). The untrimmed bandgap voltages varies by 52mV in this corner; this

variation decreases to 2.74mV after trimming.

(a) Without Trimming (b) With Trimming

Figure 5.55: Worst Corner DC performance


5.4.2 BiCMOS Bandgap Reference: Circuit 2

As shown in section 5.4.1.8, flicker noise of the Opamp is the major limitation for achieving

the desired low-noise performance in the low frequency 1mHz-100Hz frequency range. In

circuit 1, the high Opamp flicker noise is due to the use of CMOS transistors which have

inherently high flicker noise (since they are surface devices). Bipolar devices, on the other

hand, are bulk devices and thus have lower flicker noise. Hence, using npn transistors

for the Opamp’s input pair is an attractive option that may allow low-noise performance

without resorting to chopping for flicker noise reduction. An added advantage of bipolars

is their high transconductance, which would help decrease the noise effect of other MOS

devices in the Opamp (as noise contributions of all other devices would be divided by g2m

of the input pair).

The circuit implementation of the bandgap reference with BiCMOS Opamp is shown

in figure 5.56. The circuit dissipates 1mA from a 3V supply. The estimated area of circuit

2 is 740μm× 740μm.

5.4.2.1 Circuit 2: Voltage Headroom

A direct approach for using bipolar input pairs is to simply replace the NMOS transistor

with npn transistors in the circuit of figure 5.31. This, however, is not a viable solution due

to headroom limitations. To understand this limitation consider figure 5.57 which shows

the suggested connection. An npn bipolar input pair is used with an NMOS current source.

This connection will clearly limit the headroom available for the NMOS current source.

The input to each of the npn transistors is the Vbe voltage of the pnp transistor which

would be in the order of 0.6V-0.7V. Similarly, the Vbe of the npn input pair is in the same

order. This means that the tail NMOS current source will have a very limited (near-zero)

headroom which would not be sufficient for operating it in the saturation region (which is

the most favorable region for operation of MOS current sources [Sansen 06]).

To overcome this headroom limitation, two bipolar transistors are connected in series

as shown in figure 5.56 [Razavi 01]. This would allow the tail NMOS current source a

headroom of one Vbe. As an added advantage, the shown connection allows one to obtain an

output voltage equal to double the bandgap voltage (i.e. 2.4V instead of the 1.2V of circuit

1). The 2.4V output can be taken from the Vbg2 terminal. Furthermore, the conventional


Figu

re5.56:

Sch

ematic

forcircu

it2


Figure 5.57: Headroom limitation for direct npn connection

1.2V bandgap can also be obtained from the same circuit by taking the output from Vbg1.

5.4.2.2 Circuit 2: Expressions of Vbg2 and Vbg1

Refering to the circuit of figure 5.56, the voltage V1 can be expressed as:

V1 = Vbe1 + Vbe3 (5.123)

Similarly Vx will be expressed as:

Vx = Vbe2 + Vbe4 (5.124)

By virtue of feedback, and assuming an ideal Opamp, V2 will be equal to V1. Thus, the

current I can be expressed as:

I = V2−Vx

RPT

= (Vbe1+Vbe3)−(Vbe2+Vbe4)RPT

(5.125)

If transistor Q1 and Q2 are matched with an area ratio of N and equal currents I, and

transistor Q3 and Q4 are matched with an area ratio of N and equal currents I ′, then:

Vbe1 − Vbe2 = Vbe3 − Vbe4 = VT . ln (N) (5.126)


Hence, the voltage Vbg2 can be expressed as:

Vbg2 = Vbe1 + Vbe3 + 2.VT .RCT

RPT. ln (N) (5.127)

Due to the exponential Ic − Vbe characteristics of bipolar transistors, Vbe1 and Vbe3 will

be almost equal even for different currents I and I ′. Hence, the approximation Vbe1 ≈Vbe3 = Vbe can be used allowing equation 5.127 to be expressed as:

Vbg2 ≈ 2.Vbe + 2.VT .RCT

RPT. ln (N) = 2.

(Vbe + VT .

RCT

RPT. ln (N)

)= 2.Vbg (5.128)

Where Vbg is the conventional 1.2V bandgap voltage.

On the other hand, the voltage Vbg1 can be expressed as:

Vbg1 = Vbe4 + 2.VT .RCT2

RPT

. ln (N) (5.129)

Thus, Vbg1 is no more than the conventional bandgap voltage. The factor 2 in the above

equation means that the ratio RCT2

RPTwill be half the conventional value (which reduces the

effect of the Opamp’s input offset on Vbg1 [Razavi 01])

5.4.2.3 Circuit 2: BiCMOS Opamp

The use of a bipolar input pair in circuit 2 leads to the achievement of a high gain, even

without the use of cascode transistors. This can be attributed to the large transconductance

of bipolar transistors compared to their MOS counterparts. Hence, the Opamp used for

circuit 2 consists of a simple bipolar input pair with a PMOS current-mirror load. This

simple circuit allows achieving a loop gain of 67dB without cascoding.

5.4.2.3.1 Opamp headroom considerations It is to be noted that, due to the low

noise requirements, the transconductance of transistors Mp1 through Mp4 is decreased.

This, in turn, means that their overdrive voltage Veff is high leading to a high value for

their source-to-gate voltage Vsg. Consequently, the Opamp’s output voltage will be low.

Care has to be taken in the DC biasing to ensure that the bipolar input pair transistors

operate in their forward-active region i.e. the voltage at the Opamp output cannot be


arbitrarily low or otherwise the bipolar input pair would get out of the active region. With

a base voltage of roughly 1.4V, the collector voltage of the bipolar pair should not decrease

below 1.4V. This limits the flexibility of adjusting the Veff of the PMOS mirrors. Likewise,

the PMOS load of the Opamp has to have a relatively small overdrive Veff in order not to

get the bipolar pair out of the forward-active region. This requirement is against the noise

considerations which favors decreasing the overdrive of the PMOS loads.

Figure 5.58: Output Noise versus Opamp tail current

5.4.2.3.2 Opamp tail current The current needed by the Opamp is determined by

noise considerations. At low currents, the transconductance of the input pair is low. As

a result, the flicker noise of the PMOS mirror load will dominate the input-referred flicker

noise of the Opamp. At large current, the flicker noise of the bipolar input pair increases

(the input-referred flicker noise of the bipolar transistor is proportional to its base current

[aus 04a]). Hence, an optimum value exists for the bias current that achieves the minimum

input referred flicker noise. Figure 5.58, shows the output noise on Vbg2 versus the Opamp’s


bias current. The above mentioned effect can be clearly seen.

5.4.2.4 Choosing I ′

Another important noise consideration is the choice of the current I ′. The current I ′ is

used to bias transistors Q3 and Q4. From a DC point of view, it is tempting to decrease

the current I ′ as Vbe is a relatively weak function of I ′. This, however, is not favored from

the noise point of view. Decreasing I ′ leads to increasing the resistance seen into Q3 and

Q4 ( 1gmQ3,4

). This, in turn, increases the output noise voltage on the collectors of Q3 and

Q4, leading to an increase in the output noise voltage on Vbg2. Hence, if the current I ′

is decreased transistors Q3 and Q4 can easily become the dominant flicker noise sources.

Simulations show that setting I ′ = I is a good choice to avoid this situation and decrease

the overall flicker noise.


Figure 5.59 shows the output bandgap voltage Vbg2. The peak-to-peak variation in volt-

age across the -40◦C-125◦C temperature range is 7mV , corresponding to a temperature

coefficient of approximately 18ppm/◦C.


Figure 5.60 shows PSR of circuit 2 (on the 2.4V reference). An output filter is used to

improve the high frequency rejection as was done in circuit 1.


Figure 5.61 shows the output noise psd of the reference voltage Vbg2. The use of bipolars

in the Opamp allows the achievement of low flicker-noise without resorting to chopping.

The circuit achieves a total integrated noise voltage of 1μV in the frequency range 1mHz

- 100Hz.


Figure 5.59: Output bandgap voltage Vbg2 versus temperature

Figure 5.60: PSR of Vbg2


Figure 5.61: Noise PSD of Vbg2


5.4.3 Higher Order Compensated Bandgap: Circuit 3

Circuits 1 and 2 use 1st order compensation to get a temperature-independent bandgap

reference. 1st order compensation cancels only the linear component of the temperature de-

pedent Vbe (T ), leaving higher order temperature dependent components uncompensated.

This limits the minimum achieveable variation of the bandgap voltage across tempera-

ture. To achieve better performance (smaller variation with temperature), higher order

temperature compensation is needed.

5.4.3.1 Circuit 3: Basic Concept

The temperature dependent equation of the Bipolar’s Vbe voltage can be expressed as

[Meijer 82]:

Vbe (T ) =

(Vg0 + (η −m) .

k.Tr

q

)− λ.T + (η −m) .

k

q.

(T − Tr − T. ln

(T

Tr

))(5.130)

Where:

Vg0 is the extrapolated bandgap voltage of Silicon at 0 Kelvin

λ is a constant that represents the slope of the linear component of Vbe (T )

Tr is the reference temperature

η is a process constant

m is the temperature exponent of the collector current Ic5

A first order temperature compensation scheme cancels the linear term only (λ.T ),

leaving the higher order non-linearities. It is to be noted that, for first order compensation,

the non-linear terms vanish at T = Tr. This explains why the parabolic curve (of a 1st

order compensated reference)is flat at T = Tr. The curve is parabolic because the non-

linear term (η −m) .kq.(T − Tr − T. ln

(TTr

))can be approximated by Taylor expansion

as −12. (η −m) .k.Tr

q. (T−Tr)2

Tr

To cancel the higher order non-linear term totally, two approaches are possible [Hol-

man 94]:

5It is assumed that Ic ∝ T m. For a PTAT Ic, m=1. For a constant Ic, m=0


1. Setting m = η i.e. biasing the bipolar transistor (responsible for generating Vbe) with

a current Ic ∝ T η. Since η is a process constant whose value is around 4, this means

that a PTAT 4 current would be needed. Such a current is very hard to generate in

practice, making this approach impractical.

2. Using the scaled difference of two Vbe voltages, one biased with a constant current

and one biased with a PTAT current, to generate a more linear voltage Vbe lin. To

illustrate how this can be done, consider the Vbe of a bipolar transistor biased with a

PTAT current. Substituting into equation 5.130 with m=1, the Vbe of this transistor

(Vbem1) can be expressed as:

Vbem1(T ) =

(Vg0 + (η − 1) .

kTr

q

)−λ.T+(η − 1) .

k

q.

(T − Tr − T ln

(T

Tr

))(5.131)

Similarly the Vbe of a bipolar transistor biased biased with a constant current Vbem0

can be expressed as:

Vbem0(T ) =

(Vg0 + η.

kTr

q

)− λ.T + η.

k

q.

(T − Tr − T ln

(T

Tr

))(5.132)

A linear Vbe can now be obtained that is free of the higher order non-linearity. This

can be done by setting:

Vbe lin(T ) = η.Vbem1 − (η − 1) .Vbem0= Vg0−λ.T (5.133)

This is a very interesting result as it allows the total elimination of the non-linear

terms unlike the other temperature compensation techniques that just minimize this

term [Gunawan 93] [Malcovati 01] [Song 83] [Lee 94] [Rincon-Mora 98] [Leung 03].

The linear temperature variation of Vbe lin can easily be compensated by a PTAT

voltage (in the same manner used for 1st-order compensated bandgaps) to obtain a

bandgap voltage with very low temeprature variation.

The 2nd approach in the above discussion will be dubbed ”The Zero-TC technique”

hereafter.


5.4.3.1.1 Previous Implementation A compact implementation of the Zero-TC tech-

nique is presented in [Meijer 82]. The circuit is shown in figure 5.62. The current I1 is a

PTAT current and is equal to VPTAT

R0. Hence, the voltage Vx can be expressed as:

Vx = I1.R1 + 4.Vbem1 = VPTAT .R1

R0+ 4.Vbem1 (5.134)

Figure 5.62: Higher Order compensated bandgap of [Meijer 82]

The Vbe of the transistors carrying the current I1 is named Vbem1 because these tran-

sistors are biased by the PTAT current I1. The current I2 is simply equal toVref

R2. Since

Vref is the temperature-independent voltage, the current I2 will be similarly constant with

temperature i.e. the bipolars biased with I2 have Vbe = Vbem0. Hence, the voltage Vref can

be expressed as:

Vref = Vx − 3Vbem0 = VPTAT .R1

R0+ 4.Vbem1 − 3Vbem0 (5.135)


With η = 4, the voltage 4.Vbem1 − 3Vbem0 is actually the the linearized Vbe voltage

(Vbe lin) i.e. 4.Vbem1 − 3Vbem0 = η.Vbem1 − (η − 1) .Vbem0 = Vbe lin = Vg0 − λ.T . This allows

equation 5.135 to be re-expressed as:

Vref = Vg0−λ.T+VPTAT .R1

R0(5.136)

By adjusting VPTAT .R1

R0to cancel the linear term −λ.T, a very high performance (very

low temperature drift) reference can be obtained.

While this circuit is compact and elegant, it has three major drawbacks:

1. It needs a high supply voltage. With 4 bipolar transistors in series, a supply voltage

of at least 2.8V would be needed for the bipolars only. An even higher supply would

be needed to accomodate the PTAT current source biasing those bipolars, as well as

the PTAT voltage V1 (refer to figure 5.62)

2. It relies on npn transistors that are not normally available as a standard option in

today’s CMOS technologies

3. The factors η and η − 1 are obtained by the cascading of Vbe’s. This means that if η

is non integer - as is the practical case [Holman 94] - the perfect cancellation point

cannot be achieved (not even conceptually)

These drawbacks suggest that a different implementation is needed for the same com-

pensation technique if it is to be implemented in current CMOS technologies.

5.4.3.1.2 Suggested Implementation: A current-mode approach The previous

implementation of the Zero-TC technique is a voltage-mode implementation, which makes

it less flexible when it comes to scaling of the supply voltage. For low voltage opera-

tion, current-mode approaches are preferred [Banba 99]. In the context of the Zero-TC

technique, this can be done as shown, conceptually, in figure 5.63(a). A current Ivbe lin is

generated that is proportional to the ideally compensated Vbe lin voltage, i.e.:

Ivbe lin =Vbe lin

Rvbe

(5.137)


(a) GeneratingVbe s

(b) Generating Vref

Figure 5.63: Current mode approach for Zero-TC

This current is dumped in the resistor Rref to generate the desired Vbe s - which is a

scaled version of the ideally compensated Vbe lin. Hence:

Vbe s =Rref

Rvbe.Vbe lin (5.138)

To cancel the linear term of the scaled voltage Vbe s, a PTAT current IPT can be dumped

into the same resistor Rref as shown in figure 5.63(b). If the current IPT = VPTAT

RPT, then

the reference voltage Vref in figure 5.63(b) can be expressed as:

Vref = Ivbe lin.Rref + IPT .Rref

=Rref

Rvbe.Vbe lin +

Rref

RPT.VPTAT

(5.139)

This equation can, more conveniently, be re-arranged in the form:

Vref =Rref

Rvbe.

(Vbe lin +

Rvbe

RPT.VPTAT

)(5.140)

The expression between brackets is no more than the compensated reference voltage

of equation 5.136. The current mode approach allowed this voltage to be scaled by the

factorRref

Rvbe, thus allowing for arbitrary choice for the value of Vref . Hence, Rvbe

RPTshould be


adjusted to cancel the linear temperature variation term (−λ.T ) of Vbe lin andRref

Rvbecan be

used to scale the reference as desired. This form would allow a low-supply operation, if the

generation of Ivbe lin does not mandate a high supply voltage. Note that even forRref

Rvbe= 1,

lower supply can be used as there is no need for cascading of Vbe’s.

Figure 5.64: Conceptual generation of Ivbe lin

Generation of Ivbe lin can be conceptually done as shown in figure 5.64. A current

Ivbem0 = (η−1).Vbem0

Rvbeis subtracted from a current Ivbem1 = η.Vbem1

Rvbe. Hence, Ivbe lin can be

expressed as:

Ivbe lin = Ivbem1 − Ivbem0

= ηVbem1

Rvbe− (η−1)Vbem0

Rvbe

= Vbe lin

Rvbe

(5.141)

Hence, the problem of generating the current Ivbe lin translates into the problem of

generating the two currents Ivbem1 and Ivbem0. The circuits shown in figures 5.65(a) and

5.65(b) can be used for this purpose. Feedback in both circuits ensures that the positive

and negative Opamp terminals track each other. Hence, the input voltage (either Vbem0

or Vbem1) is applied - through feedback - to the resistor Rvbe generating a currentVbem0,1

Rvbe.

Ivbem1 is a ”source” current. Hence, Ivbem1 is generated by simply mirroring the current

in the PMOS transistor with a ratio of 1 : η. This allows η to take any arbitrary value,

that can also be a fraction. On the other hand, Ivbem0 is a ”sink” current. Hence, Ivbem0 is

implemented by mirroring Vbem0

Rvbeand dumping it into a diode connected NMOS transistor.


The current in the NMOS is then mirrored by a ratio of 1 : (η − 1), hence forming the

”sink” current source. Again, 1 : (η − 1) is a mirroring ratio that can take any arbitrary

value, in principle.

(a) Ivbem0 generation (b) Ivbem1 generation

Figure 5.65: Generating Ivbem0 and Ivbem1

Now, it remains to implement the voltages Vbem0 and Vbem1. This can be easily imple-

mented by the circuit shown in figure 5.66. This circuit is a modified version of the circuit

in [Banba 99] and [Malcovati 01]. The current IPTi in transistors Q1 and Q2 is a PTAT

current given by:

IPTi =VT . ln (N)

RPTi(5.142)

Hence, each of Q1 and Q2 is biased with a PTAT current. Any of them can be used

as the source of Vbem1. To get Vbem0, the current Iconst is dumped into the diode-connected

transistor Q3. Iconst is given by:

Iconst =Vbem1

RCTi+VT . ln (N)

RPTi(5.143)

Hence, an Iconst with a 1st order temperature compensated behavior can be obtained

by adjusting the RCTi to RPTi ratio. Hence, the Vbem0 voltage can be obtained from Q3.

Finally, the compensating current IPT (which is a PTAT current) can be easily imple-

mented by the circuit of figure 5.67.


Figure 5.66: Generating Vbem0 and Vbem1

Figure 5.67: Generating the PTAT compensation current IPT


Based on the above discussion, the full circuit implementation of the suggested reference

is shown in figure 5.68. The PTAT compensation circuit that generates IPT is shown

separately in figure 5.69. The Opamp used is shown in figure 5.70. The bias current i ota

for all Opamps is mirrored from the constant-current Iconst generation circuit. The ratioRref

Rvbeis chosen to be unity. All current mirrors are cascoded for best performance. To

summarize, the circuit blocks used for implementing the reference are:

1. The constant current Iconst generating circuit shown in figure 5.66. This circuit

provides both Vbem0 and Vbem1

2. The Ivbem1 generating circuit shown in figure 5.65(b)

3. The Ivbem0 generating circuit shown in figure 5.65(a)

4. The PTAT compensation circuit shown in figure 5.67

To achieve the best temperature coefficient, simulations show that a very high reso-

lution is needed for the resistor RPT (the resistor that controls the slope of the PTAT

compensation current IPT ). The resolution needed is impractically high. To solve this

problem, a value was chosen for RPT that allows it to be matched to Rvbe. To get the

desired resolution, the technique described in section 5.4.1.10 is used, where Nfing = 400

and Ntrim = 10. The circuit dissipates 1.8mA from a 3V supply. The circuit’s estimated

area is 1200μm× 1200μm.


Figu

re5.68:

Sch

ematic

forcircu

it3


Figure 5.69: Schematic of PTAT compensation circuit used in circuit 3


Figure 5.70: Schematic for Opamp used in circuit 3



Figure 5.71(a) shows the output DC voltage of circuit 3 versus temperature. The circuit

is optimized for smallest variation across temperature with η = 6.4. Furthermore, the

PTAT compensation strategy discussed in the previous section was used. The circuit

achieves a peak-to-peak variation of 100μV across the temperature range -40◦C-125◦C,

which corresponds to a temperature coefficient of 0.55ppm/◦C. This is a 30 times smaller

variation than the previous two circuits. For comparison, the bandgap voltages of circuits

1 and 3 are shown on the same graph in figure 5.71(b) (both voltages scaled to have almost

equal values at the middle of the temperature range).

(a) Higher-Order compensation output (b) Higher-order versus 1st order compensation

Figure 5.71: DC performance for higher-order compensation versus temperature

To further assess the performance of this circuit, it is simulated at two corners (corre-

sponding to maximum and minimum resistance value) and its dc performance is compared

to that of the 1st order compensated circuit (circuit 1). With no trimming, the higher-order

compensated circuit (circuit 3) has better performance in both corners than its correspond-

ing 1st order compensated counterpart (circuit 1).

Figure 5.72 shows the DC performance of circuit 1 and circuit 3 for the corner corre-

sponding to the minimum resistor value. Both circuits deviate from their performance in


the typical resistor corner. Nevertheless, the higher order compensated circuit achieves a

smaller variation across temperature: its peak-to-peak variation is only 7mV (correspond-

ing to a tempco of 38ppm/◦C), as opposed to a 36mV peak-to-peak variation for 1st order

compensation (corresponding to a tempco of 188ppm/◦C)).

(a) Higher-Order compensation (b) First-order compensation

Figure 5.72: Higher-order and first-order compensation for smallest resistance corner

Figure 5.73 shows the DC performance of circuit 1 and circuit 3 for the corner corre-

sponding to the maximum resistance value. The higher order compensated circuit achieves

a peak-to-peak variation of only 6mV (corresponding to a tempco of 33ppm/◦C), as op-

posed to a 48mV peak-to-peak variation for 1st order compensation (corresponding to a

tempco of 256ppm/◦C)).


Figure 5.74 shows the PSR of circuit 3. The use of cascoded current mirrors together with

the relatively small value used for Rref (which was done for noise considerations) allow

achieving large rejection. A filter is also added following the reference voltage to filter-out

high frequency supply variations, allowing high rejection at higher frequencies.


(a) Higher-Order compensation (b) First-order compensation

Figure 5.73: Higher-order and first-order compensation for largest resistance corner

Figure 5.74: PSR of Circuit 3



Figure 5.75: Noise PSD of circuit 3

Figure 5.75 shows the output noise PSD for circuit 3. Circuit 3 has significantly higher

noise than circuits 1 and 2. The major noise contributors are the current mirrors that

constitute the η and η−1 ratios. This can be attributed to their large currents and, hence,

large gm which increases both thermal and flicker noise components. The circuit achieves

a total integrated noise voltage of 11μV in the frequency range 1mHz-100Hz. Decreasing

the resistance Rref , in general, decreases the output noise.

This can be explained by writing the expressions of the output thermal and flicker noise

voltages due to the η and η − 1 currenr mirrors. These can be given by:

v2thermal = 8

3.k.T.gm.R2

ref

v2flicker = K.gm2

W.L.Cox.f.R2

ref

(5.144)

It is to be noted that the transconductance gm is proportional to the square root of

the dc current flowing in the transistor. If this transistor represents the η or η− 1 current


mirrors, then the current flowing in it would be proportional to 1Rvbe

. The ratio of Rref to

Rvbe is constant for a specific reference value. For this specific implementation, Rref = Rvbe.

It can, thus, be concluded that: v2thermal ∝ R1.5

ref and v2flicker ∝ Rref . This, in turn, means

that decreasing the resistance Rref results in an improvement in the noise performance.

The higher noise associated with circuit 3 means that it wouldn’t achieve the same SNR

as the previous two circuits. It would achieve an SNR worse by about 20dB than circuit

1 and by about 26dB than circuit 2. Nevertheless, this is still a high performance (high

SNR) and is further complemented by the smaller temeprature drift.

5.4.3.5 Circuit 3: Comparison with other compensation techniques

Ref. Tempco Technology Supply Current

[Lee 94] 6.65ppm/◦C 1.5μm BiCMOS 5V 74μA

[Rincon-Mora 98]∗ 6.5ppm/◦C 2μm BiCMOS 1.1V 15μA

[Malcovati 01] 7.5ppm/◦C 0.8μm BiCMOS 1V 92μA

[Leung 03] 5.3ppm/◦C 0.6μm CMOS 2V 23μA

[Circuit 3]∗ 0.55ppm/◦C 0.35μm BiCMOS 3V 1.8mA∗ simulation results

Table 5.5: Comparison between circuit 3 and reported implementations

It is instructive to compare the different higher order temperature compensation tech-

niques. The comparison is shown in table 5.5. It can be seen that circuit 3 outperforms

the other circuits in terms of temperature coefficient. This observation has to be treated

with caution, however, since all the shown results are measurement results and not simu-

lation results like circuit 3 (except for [Rincon-Mora 98]). The higher power consumption

of circuit 3 can be attributed to the low noise spec needed; the proposed technique does

not essentially require a large current consumption.

All the techniques shown in table 5.5 rely on a resistor to achieve higher order com-

pensation. This means that, across process corners, there will be a need to trim a resistor

to achieve the optimal higher-order compensated behavior. This is not the case for the

proposed technique of circuit 3, which depends on the current mirroring factors η and η−1


to achieve higher-order compensation. As discussed in section 5.4.1.10, trimming a current

mirroring ratio is easier, and more efficient than trimming a resistor.

5.4.4 Performance Comparison

In the previous sections, three different implementations of the bandgap circuit were pre-

sented to achieve the reference voltage specs outlined in section 5.2. Table 5.6 summarizes

the key specifications of each design, as well as the equivalent SNR of the proposed ΣΔ

force-feedback acceleration sensing system when each reference is used.

Circuit Noise (1mHz-100Hz) SNR Tempco Area∗

1 1μV 118dB 20ppm/◦C 570μm× 570μm

2∗∗ 1μV 124dB 18ppm/◦C 740μm× 740μm

3 11μV 97dB 0.55ppm/◦C 1200μm× 1200μm∗ area is estimated∗∗ specifications presented for the 2.4V reference

Table 5.6: Performance Comparison of Circuits 1, 2, and 3

Circuit 1 is a pure CMOS circuit that achieves the required SNR performance. Although

Circuit 2 (which is BiCMOS) outperforms it in terms of noise, Circuit 2 is 70% larger in

area than Circuit 1. Thus, the use of chopping in pure CMOS circuits can allow for low

noise performance at relatively smaller areas than the BiCMOS counterparts.

Circuit 3 achieves the minimum temperature drift of the 3 circuits, thanks to higher

order temperature compensation. However, circuit 3 suffers from an order of magnitude

higher noise than circuits 1 and 2, as well as a significantly larger area (343% larger than

circuit 1 and 162% larger than circuit 2). The much lower temperature drift, however,

complements the larger noise and area.

Conclusions

In this work, analysis has been made to the effect of Jitter on ΣΔ Force-Feedback systems.

Analytical relations were derived for the effect of white jitter on SNR. Analytical relations

were verified versus simulation. It is shown that for high performance systems, jitter can

become a major performance limiter.

Analysis was also made to the effect of the reference noise on SNR. It was shown that

the reference, and reference noise, is effectively multiplied by the output bit-stream to form

the feedback force. As a consequence of this multiplication, the SNR for large input signals

will be independent on the input signal; it will only depende on the reference voltage - to

- reference voltage noise ratio. Hence, reference voltage noise can be challenging if high

performance is needed, specifically the low frequency 1/f noise.

After reviewing the various reference voltage technologies, bandgap technology is chosen

for its inherent compatibility with CMOS technology. Three bandgap circuit designs are

presented aiming at achieving low-noise and low-drift.

The 1st design is a conventional design that uses chopping to reduce the effect of Opamp

noise. Trimming of the bandgap for lowest temperature drift across corners is also pre-

sented.

The 2nd presented design uses npn-BJT’s to achieve low-flicker noise for the Opamp.

The circuit is capable of generating 2.4V and 1.2V references simultaneously.

In the 3rd design, a new higher-order temperature compensation scheme is presented;

it is a current-mode implementation of a previously reported circuit. This new implemen-

tation, however, allows greater flexibility in the design, giving room for optimization and

allowing lower supplies.

184

Future Work

Future work that complements this work includes:

• Performing the layout of the proposed circuits, and fabrication to test their real

performance on Silicon

• Implementation of the voltage buffer following the bandgap circuit

• Completing the feedback DAC, by adding the necessary switches

185

Appendix A

MEMS acceleration system DA-IC

model

The DA-IC model of the MEMS acceleration sensing system is shown in figure 3.13. The

MEMS element is modeled as a second order system with a voltage-to-force conversion

block that converts the input voltage to force (recall that the force is proportional to

the square of the input voltage). The output of the MEMS element is a displacement

that is converted to capacitance using a displacement to capacitance conversion block

(capacitaance is inversely proportional to displacement). Figure A.1 shows the block di-

agram of the second order system and the associated voltage-to-force and displacement-

to-capacitance conversion blocks. Figure A.2 shows the block diagram of the second order

system.

The electronic filter is implemented by the spice function ”FNZ”, as shown below

.subckt Hz in out fs=409600 a=1/3 b=1/5 c=1 d=5 e=0.85

* Define the H(z) function

* Note that eldo adds implicit sample and hold

FNZ11 in out freq=fs d {a*(b+c)-2*d-e*d} {d-a*c-e*a*(b+c)+2*d*e} {e*(a*c-d)}

, 1 -2 1

.ends Hz

186

MEMS acceleration system DA-IC model 187

Figure A.1: DA-IC model of the MEMS element

Figure A.2: DA-IC model of the second order system (force-to-displacement conversion)

Appendix B

Opamp Behavioral model

The Opamp model is shown in figure B.1. The Opamp has its gain (Aop) and PSR (Gop) as

variable parameters. It consists of a voltage-controlled current source that represents the

transconductance gm of the Opamp’s input pair and a load resistor Ro that represents the

Opamp’s output impedance. Hence, the Opamp’s gain is gm.Ro. To represent the Opamp’s

Gop, another voltage controlled current source is added in parallel (and its control voltage is

the supply Vdd). This current source is active only in AC analysis and is implemented using

VerilogA behavioral modeling language. The Opamp’s Gop0 is, thus, given by gmvdd.Ro

(where gmvdd is the transconductance of the supply’s voltage-controlled current source).

Figure B.1: Opamp Behavioral Model

The VerilogA model of the supply-controlled transconductor is shown below.

188

Opamp Behavioral model 189

// VerilogA for supply-controlled transconductor

‘include "constants.vams"

‘include "disciplines.vams"

module vdd_gain(in, out, gnd);

input in, gnd;

output out;

electrical in, out, gnd;

parameter real gm_vdd = 0;

real k;

analog

begin

if ( analysis("ac") )

k = 1.0;

else

k = 0.0;

I(gnd,out) <+ k*gm_vdd*V(in,gnd);

end

endmodule

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كلية الھندسة -جامعة عين شمس

ھندسة االلكترونيات و االتصاالت قسم

ة للقوة في مجسات القصور الذاتى الكھروميكانيكية متناھية الصغر يالتغذية الرجع

رسالة

الھندسة الكھربية في الماجستير درجة للحصول على مقدمة

من مقدمة

محمد عادل البدرى الھندسة الكھربية بكالوريوس

) االتصاالتھندسة االلكترونيات و ( ٢٠٠٥ كلية الھندسة -جامعة عين شمس

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٢٠٠٩ -القاھرة

Force Feedback in MEMS Inertial Sensors

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