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Flip Chip on Laminate Reliability – Failure Mechanisms

The International Journal of Microcircuits and Electronic Packaging, Volume 23, Number1, First Quarter 2000 (ISSN 1063-1674)

© International Microelectronics And Packaging Society 53

Flip Chip on Laminate Reliability - FailureMechanismsMichael Roesch*, Robert W. Teichner*, and Rod Martens#

*Product Generation Solutions Technology CenterHewlett-Packard Company1501 Page Mill Road, MS 6U-APalo Alto, California 94304-1126Phone: 650-857-7490 ~6425Fax: 650-852-8082emails: [email protected], [email protected]

#Business Critical Computing DivisionHewlett-Packard Company3404 East Harmony Road, MS A5-6LFort Collins, Colorado 80528-9599Phone: 970-898-7709Fax: 970-898-2170email: [email protected]

Abstract

This paper investigates fundamental failure mechanisms in Flip Chip on laminate packages after thermal cycling. Parameters for theDesign of Experiments (DOE) were chip size (8mm, 16mm, 24mm), substrate CTE (glass-reinforced, non-woven aramid-reinforced),substrate thickness (0.38mm and 1.6mm) and solder ball composition (37/63 and 95/5 Pb/Sn). Underfill was not a variable in theexperiment. All Flip Chip assemblies were manufactured using similar processes and then stressed in a temperature cycle between–20°C and 110°C. The electrical resistance in the daisy chain of the assemblies was continuously monitored during the test.Failed assemblies showed distinct differences in their failure mechanisms. Failures were inspected using C-mode scanning acousticmicroscopy (CSAM) and a variety of delamination patterns were found. Cross sectioning and SEM analyses of failed assembliesrevealed different failure modes in the solder joints of the test parts, which could be correlated to the different adhesion failures. Therange of failure mechanisms found went from fast adhesion failures causing rapid cracking of multiple solder bumps to solder fatiguefailures in solder joints without any delamination in the chip/underfill interface present. One of the major findings of this work wasthat the cleaning of flux residue before underfill is key to improve the interfacial performance of the underfill and increase the life ofthe assemblies significantly. The impact of other design parameters like chip size and substrate properties was strong in the case ofdelamination driven failures while they had less of an impact in the case of solder fatigue failures without or very little delamination.

Key words:

Flip Chip, Reliability, Failure Analysis, Delamination, and Sol-der Fatigue.

1. Introduction

Flip Chip on laminate technology has been used in the low-density consumer market for many years. It is only recently thatelectrical performance requirements have sparked interest in FlipChip on laminate technology for the high I/O, high power, andlarge die sizes used in advanced computing systems such as work-stations, servers, and personal computers1,2,3. While the reliabil-ity for Flip Chip on ceramic packages is well understood, the

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introduction of laminate materials as substrates has placed evengreater importance on understanding the complex interactionsin packages with increased CTE mismatches. In this case, tem-perature changes caused by power cycling or climate control varia-tions induce thermomechanical strains that can ultimately leadto product failure.

For Flip Chip on laminate assemblies, a variety of failure modescan be observed2,3. Adhesion failures (delaminations) in the chip/underfill interface are commonly seen and have been reportedmany times. Failures in this interface are known to decrease theoverall reliability of the package by up to one order of magnitudeor more4,5. Thermomechanical fatigue of solder balls has alsobeen reported in many technical publications. In most of thesecases, only select parameter combination of materials have beenconsidered and experimentally tested. Variations in experimen-tal approaches have been mostly focused on a variety of differentunderfill materials in similar or identical parameter sets.

Finite Element modeling approaches to assess the reliabilityfor Flip Chip on laminate packages have also been reported. Mostof these analyses assume perfect adhesion between underfill andchip passivation and are based solely on solder fatigue to predictreliability. Gektin has applied a Coffin-Manson fatigue model tounderfilled Flip Chips and DCAs 4,6. Others, including Popelar7

and Schubert8,9, have employed a parametric based Finite Ele-ment modeling approach to estimate life assuming no underfilldelamination. Others have reported modeling approaches thatassume underfill delamination being the dominating failure mode.Wang10 has employed a fracture mechanics approach to charac-terize the interfacial fracture behavior of the underfill to die pas-sivation interface. Rzepka11 and Niu12 have examined the effectsunderfill delamination initiating from random defects inducedduring processing. Lau13 has investigated underfill imperfec-tions and their effect on package reliability.

This paper experimentally investigates the effects of chip size,substrate thickness, substrate CTE, and solder-bump composi-tion on the reliability of thermally cycled Flip Chip packages.Underfill was not a variable in the experiment. Test packageswere continuously electrically monitored and representative pack-ages were periodically examined for underfill delamination us-ing acoustic microscopy. Failed assemblies were analyzed usingspecial failure analysis techniques. A number of distinct failuremodes have been observed for specific parameter combinationsof the design of experiments. In this work, the authors will cat-egorize all of the observed failure modes, present SEM images ofactual failed solder joints, and correlate them to the respectivedesign parameter driving the failure.

2. Test Vehicle

A Flip Chip on laminate test vehicle composed of a bumpedtest die assembled onto an organic substrate was designed to en-compass all of the experimental parameters listed in Table 1.

Table 1. Experimental parameters.

Chip Size 8mm / 16mm 24mmBump composition 37/63 Pb/Sn 95/5 Pb/SnSubstrate CTE 9-13 ppm/°C 18-24 ppm/°CCore reinforcement Non-woven

aramidWoven glass

Substrate thickness 0.38 mm 1.6 mm

2.1. Test chips

The basic test chip design consisted of an 8mm daisy chaineddie stepped and repeated on the silicon wafer. Wafers werebumped with 37/63 Pb/Sn and 95/5 Pb/Sn solder bumps. Basedon the design, 8mm, 16mm, and 24mm Flip Chips were fabri-cated by dicing the wafers in 1x1, 2x2 and 3x3 chips.

2.2. Substrate

The construction of the substrates was done the simplest waypossible. The substrate core, which was reinforced according tothe experimental matrix, was built up with a non-reinforced ep-oxy microvialayer. The electrical wiring was done mainly on thesecond layer of the board. All connections to the Flip Chip weremade directly through via-in-pad locations connected to this sec-ond layer of the board, avoiding any need for soldermask andtherefore maximizing the height of the gap for the underfill tofill. There were no copper traces located directly under the die.Figure 1 is a schematic cross-section showing all four substratevariations. The Figure shows half of the cross section. The wir-ing pattern was mirrored on the backside of the boards. The via-in-pad locations consisted of 75µm vias and 140µm capture pads,leaving a 25µm annular ring around the via itself.

140µm Bump Pads

50 µm Epoxy 75µm Vias

Landing Padsplus Daisy Chainsplus Routing

0.5mm Core (Aramid or Glass)

0.1mm Prepreg (Aramid or Glass)

Thin Construction= 0.38mm(w/o Bumps)

0.25mm Core (Aramid or Glass)

Thick Construction= 1.6mm(w/o Bumps)

Figure 1. Schematic cross section of substrates.

For boards that would be assembled with 95/5 Pb/Sn chips, abumping process was developed to provide a flattened eutecticcap on the via-in-pad locations. Only this eutectic deposit wouldbe reflowed during the assembly of the 95/5 Pb/Sn chips andprovide the solder interconnect between the chip and the sub-




strate. Test boards that would be assembled with 37/63 Pb/Snchips were not bumped and the metal finish of these boards wasorganic coating (OCC).

The wiring pattern of the substrates is shown in Figure 2.This design could be used with all three different chip sizes. An8mm square chip was mounted on the upper left square of thispattern and monitored with the daisy chain shown. A 16mmchip was mounted on the four upper left squares, while a 24mmchip covered all nine squares of this design.

Figure 2. Wiring diagram of test substrate.

2.3. CTE of Substrates

The Coefficient of Thermal Expansion (CTE) was measuredusing Moiré interferometry14 in the x and y orientations. Theglass-reinforced boards exhibited a higher in-plane CTE thanthe aramid-reinforced boards. In addition, 0.38mm substratesshowed higher in-plane CTE values than 1.6mm substrates, whichis consistent with the higher resin to reinforcement ratios in theseconstructions. Table 2 shows the measured values for all sub-strates.

Table 2. CTE data for Daisy substrates.

Substratereinforcement / thickness

CTEx(ppm/C)

CTEy(ppm/C)

Non-woven, aramid fiber / 1.6mm 9 8Non-woven, aramid fiber / 0.38mm 13 12Woven, glass reinforced / 1.6mm 18 18Woven, glass reinforced / 0.38mm 24 25

2.4. Underfill

Underfill was not a variable in the experimental layout. Allassemblies were built using the same material, which was se-lected on the basis of flow, filler particle separation/settling, anddelamination after thermal cycling. The selected material showedthe best flow behavior with a very consistent flow front. Thematerial did not exhibit any voiding that was caused by the ma-terial itself and underfilled all chip sizes up to 24mm without

problems. It also exhibited the least filler segregation at the trail-ing edge, had the smallest filler particle size and did not showany filler settling after cure; all beneficial effects as described byDarbha15. Limited thermal cycling prior to the experiment showedno delaminations.

2.5. Assembly Process

All parts were assembled using standard Flip Chip placementequipment and a standard reflow profile for eutectic solder wasused. Before underfill, all assemblies were dried for one hour toremove excess moisture. Underfill flow was performed at 100°Cand then the parts were cured for one hour at 150°C.

It should be noted that the 95/5 Pb/Sn test assemblies used anaqueous flux that required a cleaning process after reflow andbefore underfill. All 37/63 Pb/Sn assemblies were assembledusing a commercially available no-clean flux system and wereunderfilled without a cleaning step.

3. Test Procedure

The total number of parameter combinations based on theDOE was 25. A specific combination of parameters will be re-ferred to as a “cell”. Each cell consisted of 32 Flip Chip assem-blies, 28 of which went into thermal cycling under continuouselectrical monitoring. Two assemblies were also thermallystressed but removed from the chamber at weekly intervals andinspected for delaminations using C-mode scanning acousticmicroscopy (CSAM). The last two assemblies from each cellwere not stressed and kept as backup samples. All boards wereinspected by CSAM prior to temperature cycling.

The temperature cycle was from -20 to 110°C. The assem-blies were kept at -20°C for five minutes, heated to 110°C in 12minutes, kept at 110°C for 20 minutes, and then cooled down to-20°C in 12 minutes. The complete cycle took 49 minutes. Eachpart was scanned a minimum of 60 times during every thermalcycle. For each thermal cycle, the cycle number, part number,maximum resistance R

max of the part, and the temperature T

Rmax

at which this maximum resistance occurred were recorded. Thefailure criterion for all parts was when the maximum resistanceR

max of the assembly deviated from the base line more than 5%.

This data point was used for statistical analysis and Weibull plots16.After the failed boards had been removed from the thermal

cycling chamber and the failure was confirmed and recorded, theboards went through a defined failure analysis process. All ofthe boards were first inspected using CSAM to determine if theunderfill had delaminated from the chip. The CSAM imageswere compared to the ones taken before the parts went into test.Some selected parts were then analyzed further to identify thefailure location. Then, the boards were cross-sectioned and SEMimages were taken of the failed bump locations. For all 25 cellswith different parameter combinations, a total of 6 generic delami-nation trends were found.




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3.1. Very Fast Area Delamination

Delaminations of this first type appeared very quickly duringthermal cycling. The delaminations initiated usually at one ormore corners of the chip and progressed as large areas very quicklyunder the die. The fillets showed corner cracks in all cases. Thisfailure mode was typically found during the first few hundredcycles.

The correlating bump failures were in almost all the caseshard opens in the daisy chain of the assemblies and they werealways located in a delaminated area. Cross sectioning usuallyshowed multiple cracked bumps in these areas. The cracks inthe bumps were located in the top third of the bump and were adirect continuation of the delamination between chip and under-fill. Figure 3 shows a typical delamination of this type and thecorresponding bump failure.

Figure 3. Fast delamination.

This failure mode was observed primarily in cells with eutec-tic chips (no-clean flux) on 0.38mm substrates. It was foundwith all chip sizes and both glass- and aramid-reinforced sub-strates.

3.2. Fast Line/Area Delaminations

Delaminations of this type appeared also fast during thermalcycling. The delaminations initiated in a line pattern under thechip. These lines combined quickly to larger areas usually at oneor more corners of the chip and then progressed under the die.The fillets usually showed corner cracks. This failure mode wastypically found during the first 3000 cycles of the affected boards.Line delaminations will be discussed in more detail in the nextsection.

Very similar to the first group of bump failures, the correlat-ing bump failures in this group were in almost all the cases hardopens in the daisy chain of the assemblies and they were alwayslocated in a delaminated area. Cross sectioning usually showedmultiple cracked bumps. The cracks in the bumps were mostlylocated in the top third of the bump and were a direct continua-tion of the delamination between the chip and the underfill. Inboards that failed later in this group some bumps were found thatshowed signs of solder fatigue, but the dominating failure modewere cracks in the upper portion of the bumps. Figure 4 and

Figure 5 show two typical delaminations of this type and thecorresponding typical bump failures, respectively.

Figure 4. Fast line/area delamination.

Figure 5. Fast line/area delamination.

This failure mode was observed primarily in cells with 24mmeutectic chips (no-clean flux) on 1.6mm glass-reinforced sub-strates.

3.3. Slow Area Delaminations

Delaminations of this type appeared and progressed slowlyduring thermal cycling. Very similar to the first type, these delami-nations initiated usually at one or more corners of the chip andprogressed as areas under the die but the speed of the delamina-tions was much slower. This failure mode was usually foundbetween 2000 and 8000 cycles.

The correlating bump failures were mixed. In some of thecases, hard opens in the daisy chain of the assemblies were foundbut most of them showed an increase of the initial resistance onlyand were still conductive. Cross sections of the located failedbumps showed cracks in the upper third portion of the bumps butat the same time many of the failed bumps also exhibited signs ofsolder fatigue in the bottom half. The cracks in the upper sectionof the bump were always in the area of the delamination betweenchip and underfill. In some cases, failed bumps were located innon-delaminated areas showing only solder fatigue. For boardsin this category, it can be concluded that two competing failuremodes were present. In some cases, the delamination progressedfast enough to initiate cracks in the top portion of the bumps andcause the failure. In other cases, the delamination was progress-ing slower and bumps failed by fatigue in the bottom portion ofthe bump in non-delaminated areas. Figure 6 shows a typical




delamination of this type and the corresponding bump failure.The failed bump is located in the delaminated area and showsboth solder fatigue on the bottom and cracking caused by thedelamination on the top.

Figure 6. Slow area delamination.

This failure mode was observed primarily in cells with 16mmor 24mm 95/5 Pb/Sn chips (cleaned) on 0.38mm aramid-rein-forced substrates. It was also observed on some 1.6mm substrates.

3.4. Slow Line Delaminations

Delaminations of this type appeared and progressed very slowlyduring thermal cycling. Very similar to the second type, thesedelaminations progressed usually as lines across the chips. Butthe speed of the delaminations was very slow. This failure modewas usually found between 2000 and 14000 cycles.

The correlating bump failures in this group showed usuallyan increase of the initial resistance and were still conductive.Cross sections of the located failed bumps showed solder fatigueas the dominant failure mode. Very fine hairline cracks alonggrain boundaries were found in bumps that were located as thehigh resistance spots in the chain. In many of these cases, sur-rounding bumps also showed signs of solder fatigue but the bumpswith the worst damage were consistently the ones that had beenlocated with the failure analysis techniques. The failed bumpswere located in all areas of the chips and no direct correlation tothe delaminated regions could be found. It appears that in thisgroup of boards, the delaminations progressed too slow to causethe failures. Solder fatigue was the sole failure mode. Figure 7shows a typical delamination of this type and the correspondingbump failure.

Figure 7. Slow line delamination.

This failure mode was observed primarily in cells with eutec-tic chips (no-clean flux) on 1.6mm substrates. It was found with8mm and 16mm chips on glass-reinforced substrates.

3.5. Slow Random Delaminations

Delaminations of this type appeared and progressed very slowlyduring thermal cycling. Compared to the cases discussed above,these delaminations appeared in an erratic fashion under the dieand had another characteristic look to them. This failure modewas usually found between 2000 and 14000 cycles.

Very similar to other slow delaminations, the correlating bumpfailures in this group showed usually an increase of the initialresistance and were still conductive. Cross sections of the lo-cated failed bumps showed again solder fatigue as the dominantfailure mode. Very fine hairline cracks were found in bumps thatwere located as the high resistance spots in the chain. In a lot ofthe cases surrounding bumps also showed signs of solder fatiguebut the bumps with the worst damage were consistently the onesthat had been located with the failure analysis techniques. Thefailed bumps were located in all areas of the chips and no directcorrelation to the delaminated regions could be found. Similarto other slow delaminating cases, the delaminations in this caseprogressed too slowly to cause the failures. Solder fatigue wasthe sole failure mode.

Figure 8 shows a typical delamination of this type and a cor-responding bump failure, which was one of the high resistancespots in the chain. A likely explanation for the characteristiclook of these delaminations is cracks in the epoxy microvia layer.All failed assemblies, which exhibited this failure type, did showcrazing of the epoxy microvia layer that extended under the chiparea.

Figure 8. Slow random delamination.

This failure mode was found predominantly in cells with 8mmor 16mm 95/5 Pb/Sn chips assembled on 1.6mm aramid-rein-forced substrates.

3.6. Failed Boards without Delaminations

Boards in this category failed without any delaminations be-tween underfill and chip. This case was usually found between3000 and 14000 cycles.

The correlating bump failures in this group showed an in-crease of the initial resistance and were still conductive. Cross




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sections of the located failed bumps showed solder fatigue as thefailure mode. Very fine hairline cracks were found in bumps thatwere located as the high resistance spots in the chain. In a lot ofthe cases, surrounding bumps also showed signs of solder fatiguebut the bumps with the worst damage were consistently the onesthat had been located with the failure analysis techniques. Thefailed bumps could be located in all areas of the chip but werepredominantly found around the perimeter of the die. Figure 9and Figure 10 show two typical failed boards of this type and thecorresponding failed bumps.

Figure 9 shows a 95/5 Pb/Sn solder ball fatigued in the eutec-tic zone at the bottom. Figure 10 shows a fatigued 37/63 Pb/Snsolder ball with fatigue damage in the center of the bump.

Figure 9. Board without delamination.

Figure 10. Board without delamination.

This failure mode was observed primarily in cells with 1.6mmaramid-reinforced substrates. It was predominately found with95/5 Pb/Sn chips, but some eutectic cells showed similar fail-ures.

3.7. Verification of Delamination ProgressionUsing Control Boards

As mentioned above, two boards for each cell were cycledwith the rest of the boards but not continuously electrically moni-tored. These boards were removed from the thermal cycling cham-ber in regular intervals and inspected for delaminations usingCSAM. In all cases, the results for the CSAM control boardswere consistent with the delamination patterns found within thecorrelating cells. The daisy chain resistance values for the con-trol boards were measured each time when they were removedfrom the thermal cycling chamber and their final failures also

corresponded with the overall trend for the cell. The delamina-tion sequences that were recorded for these control boards were asignificant contribution to the differentiation of the discussed fail-ure trends.

Figure 11 shows one example of a delamination sequence fora control board. This board falls into the category with very fastprogressing area delaminations. After 600 cycles, more than80% of the chip area was delaminated and the daisy chain wasopen.

240 cycles 395 cycles 600 cycles

Figure 11. Delamination sequence for very fast areadelamination.

Figure 12 shows another example of a delamination sequencefor a control board. This board falls into the category with slowlyprogressing line delaminations. The delaminations developedover 6200 cycles. The board was removed from the CSAM con-trol group with an increased resistance in the daisy chain.



Figure 12. Delamination sequence for slow linedelamination.

Due to space limitations, the complete sequence or additionalcontrol cases cannot be shown; however, delamination sequencesfor all cells have been recorded and did correlate in all cases withthe failure analysis results for the respective cells.




3.8. Relationship of Glass Reinforcementand Line Delamination

One observation made during the CSAM inspections was thedelamination pattern that progressed in lines between the chipand the underfill. It was recognized that this effect could only beseen for assemblies with FR-4 substrates. A hypothesis wasformed that the woven glass reinforcement of the FR-4 had asignificant influence on this pattern. To prove this theory, oneboard was analyzed. The fillet on the side of the chip was me-chanically removed and the board was placed into a plasma cham-ber. The oxygen plasma removed the rest of the underfill and thetop layers of epoxy resin covering the glass reinforcement.

Figure 13 shows images of the analysis process for this part.The CSAM image of the board shows the delamination progres-sion in lines. The photographs illustrate the location of theplasma-etched substrate and show magnifications of the exposedglass reinforcement of the FR-4 material around the lower rightcorner of the Flip Chip.

Figure 13. Delamination analysis.

It was found that the number of delaminated lines under chipcorresponded exactly with the number of horizontal glass bundlesin the reinforcement. A further indication for the influence ofthe woven glass reinforcement on the properties of the laminatewas found during the measurement of the material properties ofthe FR-4 substrates. The Moiré analysis of the FR-4 laminaterevealed localized CTE differences in the xy-plane of the mate-rial. These CTE differences are caused by the woven glass rein-forcement and different resins to glass ratios in the material.Figure 14 shows the Moiré image of the x-plane of a FR-4 sub-strate. One fringe in the image represents a displacement of0.4µm. The fact that there are always two fringes close togetherand the next two are spaced further apart illustrates the localCTE differences in the material.

This analysis showed that the woven glass reinforcement ofthe FR-4 boards causing local CTE differences in the laminatematerial has a significant influence on the appearance of thedelamination pattern under a Flip Chip assembly. However, itcannot be concluded that the glass reinforcement is the ultimatecause for the delamination. A laminate with random glass rein-forcement but a comparable CTE might also cause delamina-

tions in a Flip Chip assembly. The only difference might be thatthose delaminations have a different appearance.

Figure 14. Moiré fringe pattern of FR-4 in x-plane.

4. Conclusion

1. Delamination driven solder bump failures are in almost allcases hard opens in the daisy chain with multiple cracked bumps.The cracks are located in the top third of the bumps.

2. Solder fatigue failures are high resistance spots in the daisychains. Failed bumps exhibit hairline cracks along grain bound-aries in the solder.

3. For 95/5 Pb/Sn bumps assembled in eutectic caps, the sol-der fatigue cracks are always located in the eutectic bottom por-tion of the bumps. Delamination driven cracks are located at thetop.

4. 37/63 Pb/Sn assemblies (no-clean flux) on 0.38mm boardsdelaminated rapidly in the chip/underfill interface. This trendwas strongly impacted by larger chip sizes and increased sub-strate CTE.

5. 95/5 Pb/Sn assemblies (cleaned) on 0.38mm boards delami-nated significantly slower. The influence of substrate CTE andchip size is minimized.

6. 37/63 Pb/Sn assemblies (no-clean flux) on 1.6mm boardsdelaminated slower. 95/5 Pb/Sn assemblies on the same boardsexhibit almost no delamination driven failures. The major fail-ure mode is solder fatigue.

7. Substrate CTE and chip size play an important role in thecase of delamination driven failures. In the case of solder fatiguefailures, their influence is less of a factor.

8. Cleaning of flux residue is crucial to avoid adhesion drivenfailures.

In order to successfully implement a reliable Flip Chip pack-aging solution, it is desirable to ensure solder fatigue as the lim-iting mechanical failure mechanism. Doing so enables the pack-aging engineer to design to specific reliability standards, as sol-der fatigue is a known and predicable failure mechanism. It wasshown in this paper that underfill delamination as a failure modeleads to unpredictable and early failures while parts withoutdelamination showed the preferred failure mode of solder fatigue.Additionally, it was shown that it is necessary to consider thepackage as a system rather than focusing on a single design pa-rameter to drive the desired failure mode.




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Acknowledgments

The authors would like to thank Judy Gates, Helmut Kroenerand Robert M. Lawson for management support. Additionally,the researchers acknowledge all the members of the Flip Chipteam - Meng Chow, Mark Brillhart, Melanie Merton, AndyUchida, Paul Myer, Mike Ries, Matthew Heydinger and GeorgeMargaritis – for their contributions and Jeff Riebling for his sup-port in data analysis. Additionally, the authors would like toacknowledge the substrate team: Gunther Boehm, Sylvia Ehrler,Alexander Ippich, Roland Kohler, Dieter Porsche, JuergenRoemhild, Markus Siewerth, Hilmar Spieth, Walter Wolf andAndrea Zielinski.

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About the authors

Michael Roesch received his Engi-neering Diploma in Polymer-chemistryin 1994 from Reutlingen University ofTechnology and Business Administra-tion in Germany. He started his careerwith Hewlett-Packard as Research &Development Engineer in the PrintedCircuit Board facility in Boeblingen,Germany. His work there was focusedon aramid reinforced laminates,microvia processing and multilayer

lamination. In 1995, he transferred to Hewlett-Packard in PaloAlto, CA as Manufacturing Development Engineer, where hehas been involved in various projects around electronic assem-bly. He led an underfill qualification and Flip Chip reliabilityprogram and was also involved in a wide variety of internal tech-nical projects. Michael has represented HP in the SEMATECHtechnical advisory board on underfill adhesion between 1996 and1998. He is currently a Reliability Scientist with the Hewlett-Packard Product Generation Technology Center.

Robert W. Teichner is a DevelopmentEngineer for Hewlett Packard in theProduct Generation Solutions Technol-ogy Center. He has been with Hewlett-Packard for 38 years and has has devel-oped products in Microwave,Optotelectronic Displays, Optocouplers,Optoisolators, and Fiberoptics mostly inassembly of components. He holds 6HP Patents in these fields. He had pre-viously been on the staff of William

Shockley’s semiconductor company. Earlier, he had been in-volved in the development of new materials for offset lithogra-phy. Mr. Teichner has an M.S. in Chemistry (Harvard 1937) anda B.S. in Chemical Engineering (Polytechnic Inst. Of B’kly’n1934).

Rod Martens received the Ph.D. inMechanical Engineering from the Uni-versity of Maryland in 1996. He hasbeen employed by the Business CriticalComputing Division of Hewlett-PackardCompany for 4 years, responsible forqualification of high reliablity compo-nents for enterprise servers. His researchinterests include connector/socket reli-ability and Flip Chip packaging.

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