fitipower integrated technology lnc. Preliminary...

1 FP6797-Preliminary 0.2-2008

FP6797fitipower integrated technology lnc. Preliminary

Bias Power Supply for TV and Monitor TFT LCD Panels

Pin Assignments TP Package (TSSOP-28<Exposed Pad>)

Figure 1. Pin Assignment of FP6797

Ordering Information

Description The FP6797 offers a compact power supply solution to provide all four voltages required by thin-film transistor (TFT) LCD panel. With its high current capabilities, the device is ideal for large screen monitor panels and LCD TV applications.

The FP6797 consists of a boost converter to provide the source voltage VS and a step-down converter to provide the logic voltage for the system. A positive and a negative charge pump drivers provide adjustable regulated output voltages VGH and VGL to bias the TFT-LCD. Both step-up and step-down converters, as well as the charge-pump drivers, operate with a fixed switching frequency of 500 KHz or 750 KHz, selectable by the FREQ pin. The FP6797 includes adjustable power-on sequencing.

The FP6797 includes safety features like over-voltage protection and short-circuit protection, as well as thermal shutdown. Additionally, the device incorporates a gate drive signal to control an isolation MOSFET switch in series with VS or VGH. The FP6797 comes in a miniature 28-pin TSSOP package with exposed pad.

Features 8V to 14V Input Voltage Range VS Output Voltage Range up to 19 V 1% Accurate Step-up Converter with 2.8A

Switch Current 1.5% Accurate 2.3A Step-down Converter 500KHz/750KHz Fixed Switching Frequency

Selection Negative Charge Pump Driver for VGL Positive Charge Pump Driver for VGH Adjustable Sequencing for VGL, VGH Gate Drive Signal to Drive External MOSFET Internal and Adjustable Soft Start Short Circuit Protection Over Voltage Protection Over Temperature Protection TSSOP-28 Exposed Pad Package

Applications TFT LCD Displays for Monitor and LCD TV

FP6797

P: Pb Free with Commercial Standard (RoHS Compliant) G:Green

TR: Tape / Reel Blank: Tube

Package Type TP: TSSOP-28(Exposed Pad)



Typical Application Circuit

VGL-5V/50mA

VIN 12V

VIN2

SUPP

FP6797

LX1

OS

FB1

LX1

8

20 1

5

4

3

VIN1

EN1

22

16

FBP 14

EXT

GND

27

23

D2

FBN13

REF24

PGND6

PGND7

SS28

DLY125

12

21

BOOT 17

LX2 18

NC 19

FB2 15

COMP 2

DLY2 26

DRVP 10

DRVN11

9 EN2

L1 10µF

FREQ

VIN2

CB31µF

CIN2*22µF

CB11µF

C4 0.47µF

D3

R3 620KΩ

R4 150KΩ

CREF 220nF

C2 0.47µF

CD1 10nF

CSS 22nF

D1 SL22

R1 825KΩ

R2 56KΩ

CF1 22PF C1

3*22µF

CB2 470nF

C5 0.47µF

D4

D5

Vs 18V/1.3A

VGH 32V/50mA

R5 560KΩ

R6 22KΩ

C3 0.47µF

CBOOST 100nF

L2 15µF

D6 SL22 R7

2KΩ

R8 1.2KΩ

C5 2*22µF

Vlogic 3.3V/2.3A CLOMP

22nF

CD2 10nF

Figure 2. Typical Application Circuit of FP6797



Functional Pin Description Pin Name Pin Function

1 FB1 Feedback pin of the step-up converter generating VSOURCE (VS)

2 COMP The external compensation pin for the step-up converter. A small capacitor is connected to this pin. If required, a resistor is connected to this pin.

3 OS Output sense pin. The pin is connected to the output of step-up converter and can not be connected to any other voltage rail. Connect a 470-nF capacitor from OS pin to GND to avoid noise coupling into this pin.

4, 5 LX1 Switching pin of the step-up converter generating VSOURCE (VS)

6, 7 PGND Power ground

8 SUPP The supply pin for positive charge pump driver. It can be connected to the input voltage VIN or the output of the step-up converter VS

9 EN2 EN2 is the enable pin of the step-up converter and the positive charge pump. When EN2 is pulled high, the step-up converter and positive charge pump start up after the step down converter is within regulation and a delay time set by DLY2 has passed by. This pin must be terminated and not be left floating. A logic high enables the device and a logic low disables the device

10 DRVP Drive pin of the positive charge pump

11 DRVN Drive pin of the negative charge pump

12 FREQ Frequency selection pin. A logic high set the oscillator frequency = 750KHz and a logic low set the oscillator frequency = 500KHz

13 FBN Feedback pin of the negative charge pump

14 FBP Feedback pin of the positive charge pump

15 FB2 Feedback pin of the step-down converter

16 EN1 EN1 is the enable pin of the step-down converter and the negative charge pump. When EN1 is pulled high, the step down converter starts up, and after a delay time set by DLY1, the negative charge pump comes up. This pin must be terminated and not be left floating. A logic high enables the device and a logic low disables the device

17 BOOT Bootstrap pin. A capacitor is needed to drive the N-channel MOSFET’s gate above the supply voltage. It is connected between LX2 and BOOT pin to form a floating supply across the N-channel MOSFET

18 LX2 Switching pin of the step-down converter

19 NC No connected

20, 21 VIN2 Power input voltage pin for the step-down converter

22 VIN1 Analog input voltage pin. This is the input for the analog circuits of the device and should be connected with a bypass capacitor for good filtering

23 GND Analog ground

24 REF Reference pin. Typically 1.213V.

25 DLY1 Connect a capacitor between this pin and ground to set the delay time between step-down converter and negative charge pump during start-up

26 DLY2 Connect a capacitor between this pin and ground to set the delay time between step-down converter to step-up converter and positive charge pump during start-up

27 EXT The gate drive pin which can be used to control an external MOSFET switch to provide input to output isolation of VS or VGH. EXT is an open-drain output and is latched low when the output voltage of step-up converter is regulated (92% of FB1). EXT is changed to high impedance when EN2 or input voltage (VIN1) is cycled low.

28 SS Connect a capacitor to this pin to set the step-up converter internal soft-start time. Typically 22nF



Block Diagram

Soft Start

500KHZ/750KHZOscillator

Control Logic

BiasVref=1.213V

Thermal Shutdown

GND

SS

COMP

OS

PGND

PGND

SUPP

VrefOS

SUPP

FB

Error Amplifer

VIN2

OvervoltageComparator

DRVP

FBP

BOOT

LX2

NC

Regulator5V

Slope Compensation

FB2

VIN1 FREQ

Current Limitand

Soft Start

BTSS

LX1 LX1

Q2

OS

Vref

Comparator

Vref1.154V

Vref 1.213V

Soft Start

NegativeCharge PumpVIN1

Control Logic

Vref

Compensationand

Soft Start

DRVN

VrefTDLY1

FBN

DLY1

VrefTDLY2

DLY2

EXT

ClockLogic

0.9VClock/2

Clock

0.6VClock/4

Clock Select During Short Circuit and Soft Start REFVref

1.213V

EN1 EN2

GM Amplifier

ReferenceoutputPower-on

SequencingControl

TDLY1

TDLY2

BTSS

PR2

OSC

ControlLogicPR2

osc

PR2PR1

Current Limit

ControlLogic

PR1

Slope Compensation

Figure 3. Block Diagram of FP6797



Absolute Maximum Ratings VIN1, VIN2, EN1, EN2, FREQ to GND ------------------------------------------------------------- -0.3V to 16.5V

FB1, FB2, FBP, FBN, REF, SS, DLY1, DLY2, COMP to GND ----------------------------- -0.3V to 6V

LX1 to PGND ------------------------------------------------------------------------------------------ -0.3V to 25V

LX2 to PGND ------------------------------------------------------------------------------------------ -0.3V to 20V

BOOT to GND ----------------------------------------------------------------------------------------- VLX2 + 5V

OS, EXT, SUPP to GND ---------------------------------------------------------------------------- -0.3V to 25V

DRVN, DRVP to PGND ----------------------------------------------------------------------------- -0.3V to (SUPP+0.3V)

PGND to GND ----------------------------------------------------------------------------------------- ± 0.3V

Maximum Junction Temperature (TJ) ------------------------------------------------------------ + 150

Storage Temperature (TSTG) ------------------------------------------------------------------------ -65 to + 150

Power Dissipation @ TA=70, TSSOP-28 (PD) ---------------------------------------------- 1.38W

Package Thermal Resistance, TSSOP-28 (θJA) ----------------------------------------------- 40 /W

Lead Temperature (Soldering, 10sec.) ---------------------------------------------------------- + 260

ESD Susceptibility (HBM Mode)------------------------------------------------------------------- 2KV

ESD Susceptibility (MM Mode)--------------------------------------------------------------------- 100V

Note：Stresses beyond those listed under “Absolute Maximum Ratings" may cause permanent damage to the device.

Recommended Operating Conditions

Supply Voltage (VIN) --------------------------------------------------------------------------------- 8V to 14V

Output Voltage of Main Boost Converter (VS) -------------------------------------------------- 19V

Output Voltage of Buck Converter (VLOGIC) ----------------------------------------------------- 1.8V to 5V

Operation Temperature Range -------------------------------------------------------------------- - 40°C to + 85°C



Electrical Characteristics (VIN=12V, VSUPP= VIN, VEN1= VEN2= VIN, VS=15V, VLOGIC=3.3V, TA= 25 ºC, unless otherwise specified)

Parameter Symbol Conditions Min Typ. Max Unit

Input Voltage Range VIN 8 14 V

Under-Voltage Lockout Threshold VUVLO VIN falling 6 6.4 V

Bias Current

Bias Current into VIN1 IVIN1 0.2 2 mA

Bias Current into VIN2 IVIN2 0.2 0.5 mA

Bias Current into SUPP IVIN2 0.2 2 mA

Shut Down Current into VIN1 ISD,VIN1 EN1=EN2=0V 0.1 2 µA

Shut Down Current into VIN2 ISD,VIN2 EN1=EN2=0V 0.1 2 µA

Shut Down Current into SUPP ISD,VIN1 EN1=EN2=0V 0.1 4 µA

Reference

Reference Voltage VREF 1.201 1.213 1.225 V

Enable

EN1, EN2 High Level Input Voltage VENH 2

EN1, EN2 Low Level Input Voltage VENL 0.3

FREQ High Level Input Voltage VFREQH 2

FREQ Low Level Input Voltage VFREQL 0.3

V

Input Leakage Current II EN1=EN2=FREQ=0V or VIN 0.01 0.1 µA

Delay and Soft Start Setting

Delay 1 Charge Current IDLY1 3.3 4.8 6.2

Delay 2 Charge Current IDLY2 3.3 4.8 6.2

Soft Start Charge Current ISS

VTHRESHOLD = 1.213V

5 9 12

µA

Oscillator

FREQ=High 600 750 900 Oscillator Frequency fOSC

FREQ=Low 400 500 600 KHz

Step-up Converter

Output Voltage Range VS 19 V

Feedback Voltage VFB1 1.135 1.146 1.157 V

Feedback Input Leakage Current IFB1 10 100 nA

NMOS On-Resistance ILX=500mA 100 mΩ

PMOS On-Resistance RDS(ON)

ILX=200mA 10 Ω

Maximum PMOS Peak Switch Current 1 A



Electrical Characteristics (Continued) Parameter Symbol Conditions Min Typ. Max Unit

NMOS Current Limit ILIM 2.8 3.5 A

LX1 Switch Leakage Current ILEAK VLX1=15V 1 10 µA

Over-Voltage Protection Threshold VOVP VOUT rising 19.5 20 21.5 V

Line Regulation 10.6V < VIN < 11.6V at 1mA 0.0008 %/V

Load Regulation 0.03 %/A

Thermal Shutdown Temperature rising 155 ºC

Thermal Shutdown Hysteresis 20 ºC

Step-down Converter

Output Voltage Range VLOGIC 1.8 5 V

Feedback Voltage VFB2 1.195 1.213 1.231 V

Feedback Input Leakage Current IFB2 10 100 nA

NMOS On-Resistance RDS(ON) ILX2=500mA 175 mΩ

NMOS Current Limit ILIM 2.5 3.2 A

LX2 Switch Leakage Current ILEAK VLX2=0V 1 10 µA

Line Regulation 10.6V < VIN < 11.6V at 1mA 0.0018 %/V

Load Regulation 0.037 %/A

Negative Charge Pump

Output Voltage Range VGL -2 V

Feedback Voltage VFBN -36 0 36 mV

Feedback Input Leakage Current IFBN 10 100 nA

PMOS On-Resistance RDS(ON) IOUT = 20mA 4.4 Ω

IDRVN = 50mA 130 mV Current Sink Voltage Drop VDROPN

IDRVN = 100mA 270 mV

Positive Charge Pump

Feedback Voltage VFBP 1.187 1.213 1.238 V

Feedback Input Leakage Current IFBP 10 100 nA

NMOS On-Resistance RDS(ON) IOUT = 20mA 1.1 Ω

IDRVP = 50mA 400 mV Current Source Voltage Drop VDROPP

IDRVP = 100mA 850 mV

Gate Drive (EXT)

Gate Drive Threshold VEXT VFB1 rising 88% VS 92% VS 96% VS V

Gate Drive Output Low Voltage VEXTL Sink 500µA 0.3 V

Gate Drive Output Leakage Current IEXTL VEXT = 20V 0.05 1 µA



Typical Performance Curves

0.0 0.5 1.0 1.5 2.00

10

20

30

40

50

60

70

80

90

100

Effic

ienc

y (%

)

Output Current (A)

VIN/VO=12V/15VL=15uHFREQ=0V

0.0 0.5 1.0 1.5 2.00

10

20

30

40

50

60

70

80

90

100

Effic

ienc

y (%

)Output Current (A)

VI=12V

VO=3.3V

L=15uH

Figure 4. Boost Converter Efficiency vs. Output Current Figure 5. Step Down Converter Efficiency vs. Output Current

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90640

650

660

670

680

690

700

710

720

Switc

hing

freq

uenc

y (k

Hz)

Temperature (deg)

Figure 6. Switching Frequency vs. Temperature Figure 7. Boost Converter Soft-Start

Figure 8. PWM Operation Boost Converter Continuous

Mode: Light Load Figure 9. PWM Operation Boost Converter Continuous

Mode: Heavy Load

VIN=12VVS=15V/1.2A CSS=22nF

VIN=12V VS=15V/10mA

VIN=12VVS=15V/1.5A

CH4: ILX1

CH2: VLX1

CH3: VS

CH4: ILX1

CH2: VLX1

CH3: VS

CH4: ILX1

CH2: VLX1

CH3: VS



Typical Performance Curves (Continued)

Figure 10. Boost Converter Load Transient Response Figure 11. Step Down Converter Soft-Start

Figure 12. Step Down Converter PWM Operation Discontinuous Mode

Figure13. Step Down Converter PWM Operation Continuous Mode

Figure 14. Step Down Converter Load Transient Response Figure 15. Power-Up Sequence EN2 Connected To VIN

VIN=12V, VS=15V, CO=3x22uF CCOMP=4.7nF, CF1=22pF, L=6.8uH, FREQ=H IOUT =200mA to 1.4A

VIN=12V VO=3.3V/1.5A

VIN=12V VO=3.3V/45mA

VIN=12V, VLOGIC=3.3VCO=22uFx2, FREQ=H IOUT =100mA to 1.3A

CH4: IOUT

CH1: VS

CH1: VLOGIC

CH4: ILX2

CH2:VLX2

CH3: VLOGIC

CH4: ILX2

CH2:VLX2

CH3: VLOGIC

CH4: IOUT

CH1: VLOGIC

CH4: VGH

CH2: VGL

CH3: VS

VIN=12V VO=3.3V/1.2A CH3: VLOGIC

CH4: ILX2

CH2:VLX2



Typical Performance Curves (Continued)

Figure 16. Power-Up Sequence EN2 Enabled Separately

CH1: VLOGIC

CH4: VGH

CH2: EN2

CH3: VS



Application Information Operation The FP6797 is a multiple-output DC-DC converter IC which is designed primarily for use in thin-film transistor (TFT) liquid crystal display (LCD) applications. It features two PWM converters: one is step-up converter operating with a selectable switching frequency of 500KHz or 750KHz and uses internal N-MOS to provide maximum efficiency. The output voltage of the step-up converter can be set from VIN to 19V with external resistive divider. The other is step down converter using internal N-MOS to provide the logic voltage for system. A pair of charge-pump regulators independently regulates a positive output VGH and a negative output VGL for TFT gate-high and gate-low supplies. FP6797 also consists of a precision 1.213V reference, logic shutdown, current-limited, soft-start, power-up sequencing and thermal shutdown.

Step Up Converter The step up converter operates in fast transient response, current-mode PWM. Figure 3 shows block diagram of FP6797. On the rising edge of the internal clock, the control and driver logic block sets internal flip-flop when the output voltage is too low, which turns on the N-MOS. The external inductor current ramps up linearly, storing energy in a magnetic filed. Once peak current of inductor over trans-conductance output level, the N-MOS turns off, the flip-flop resets, and external schottky diode turns on. This forces the current through the inductor to ramp back down, transferring the energy stored in the magnetic field to the output capacitor and load. To add higher flexibility to the selection of external component values, the device uses external loop compensation

Negative Charge-Pump Regulator (VGL) Negative Charge-Pump Regulator inverts the supply voltage (VIN1) and provides a regulated negative output voltage to power the row driver in the LCD panel. During the first half-cycle, the P-channel MOSFET turns on and flying capacitor C4 charges to VIN1 minus a diode drop. During the second half-cycle, the P-channel MOSFET turns off, and the current source turns on, level shifting C4. This connects C4 in parallel with the reservoir capacitor C2. If the voltage across C2 minus a diode drop is lower than the voltage across C4, charge flows from C4 to C2 until the diode turns off. The amount of charge transferred to the output is controlled by the variable N-channel on-resistance and a resistive voltage-divider from the VGL output to GND with the center tap connected to FBN.

Positive Charge-Pump Regulator (VGH)

Positive Charge-Pump Regulator also inverts the supply voltage (VS) and provides a regulated positive output voltage to power the row driver in the LCD panel. During the first half-cycle, the N-channel MOSFET turns on and flying capacitor C5 charges to VS minus a diode drop. During the second half-cycle, the N-channel MOSFET turns off, and the current source turns on, level shifting C4 by VSUPP volts. This connects C5 in series with the reservoir capacitor C3. If the voltage across C3 plus a diode drop is lower than the level shifted flying capacitor voltage (VS+VSUPP), charge flows from C5 to C3 until the diode turns off. The amount of charge transferred to the output is controlled by the variable N-channel on-resistance and a resistive voltage-divider from the VGH output to GND with the center tap connected to FBP.

Power-Up Sequencing

The step-down regulator starts up when the FP6797’s input voltage (VIN1) is above its under-voltage lockout (UVLO) threshold and EN1 is logic-high. Once the step-down regulator reaches regulation, the negative charge pump delay block are enabled. A 4.8μA current source at DLY1 charges CD1 linearly. The negative charge-pump regulator soft-starts when VDLY1 reaches VREF. The step-up regulator and positive charge-pump startup sequence begin when the step-down regulator reaches regulation and EN2 is logic-high. A 4.8μA current source at DLY2 charges CD2 linearly when VDLY2 reaches VREF. For non-delayed startups, capacitors can be omitted from DLY1, DLY2.

Delay Time Setting A capacitor from DLY1, DLY2 pin to GND modulates delay time. Select CDLY1,2 using the following equation:

V.uA.TC DELAY,DLY 2131

8421 ×=

where TDELAY is setting delay time



Application Information (Continued)

Frequency Selection The FP6797’s frequency can be user selected to operate at either 500kHz or 750KHz. Connect FREQ to GND for 500kHz operation. For a 750KHz switching frequency, connect FREQ to VIN. This allows the use of small, minimum-height external components while maintaining low output noise.

Current Limit Protection The FP6797 provides cycle-by-cycle over-current protection. Current limit is accomplished by sensing voltage drop across the drain to source of power switch. If the current sense amplifier output voltage is larger than current-limited threshold level (typ. 1.0V), it will be immediately turned off power MOS. The current-limit feature protects over current fault at the output.

Thermal Overload Protection Thermal-overload protection limits total power dissipation in the FP6797. When the junction temperature exceeds Tj= +155°C, a thermal sensor activates the thermal protection, which shuts down the IC, allowing the IC to cool. Once the device cools down by 20 , IC will automatically recover normal operation. For continuous operation, do not exceed the absolute maximum junction temperature rating of Tj=150 .

Short Circuit Protection (Step Down Converter) The FP6797 protects output short circuit by switching frequency fold-back. The oscillator frequency of FP6797 is reduced to about 1/2 and 1/4 of switching frequency when the feedback voltage is under 0.9V and 0.6V. This frequency fold-back allows the inductor current has more time to decay to prevent potential runaway condition to occur. The oscillator frequency will progressively increase to normal frequency as feedback voltage rises gradually from 0.6V back to regulated level.

Over Voltage Protection (Step Up Converter) The over-voltage function monitors the output voltage by OS pin to protection the converter against the FB1 pin short to ground with a sense resistor. This will cause N-MOS to switch with a maximum duty cycle and come out output over-voltage. This may cause the LX1 pin voltage to exceed its maximum voltage rating to damage built-in N-MOS. In the state, the OVP protection circuitry stops the internal N-MOS and clamp output voltage at 20V (typ). When VOUT falls below 17V (typ), IC will automatically recover normal operation.

Under Voltage Lockout

The under voltage lockout (UVLO) circuit provides the save operation to keeps the device from turning on when VIN is smaller than typically 6.0V.

Soft-Start (Step Up Converter)

Soft-start allows a gradual increase of the internal current-limit level for the step-up converter during power-up to reduce input surge currents. As the internal constant current source charges the external soft-start capacitor, the peak N-MOS current is limited by the voltage on the capacitor.

Adjustable Step-up Converter Output Voltage

The output voltage of FP6797 ranges from VIN to 19.0V which is set by the external feedback resistor. It can be calculated as:

)RR(.VS 2

111461 +×=

Adjustable Gate-High Charge-pump Output Voltage

The Gate-high charge pump output voltage can be set by the external feedback resistor from VON to GND. A resistor network in the order of 22kΩ is recommended. It can be calculated as:

)RR(.VGH 6

512131 +×=

Adjustable Gate-Low Charge-pump Output Voltage

The Gate-low charge pump output voltage can be set by the external feedback resistor from VOFF to GND. A resistor network in the order of 150kΩ is recommended. It can be calculated as:

REFFBNGL VRR)

RR(VV ∗−+×=

43

431

where VFBN=0V, VREF =1.213V as specified.



OSCL

Oin

OSC

OinL fI

D)VV(L

fD

LVV

I×Δ

×−=⇒×

−=Δ


Positive and Negative Charge Pump The FP6797 contains two independent charge pump. The regulation of both the negative and positive charge pumps is generated by external diode-capacitor. The single stage of positive charge-pump is given by:

3OSCGH

5OSCGHDIODEDRVPP(ON)

DRVPN(ON)GHSUPPGH(MAX)

Cf1I

Cf1IV2)R

(R2IVV

××−

××−×+

+××−×≤ 2

where RDRVPN(ON) and RDRVPP(ON) resistance values depend on the VSUPP voltage levels, VDIODE is the forward-voltage drop of the charge-pump diode. The single stage of negative charge-pump is given by:

IN12OSC

GL4OSC

GLDIODE

DRVNP(ON)DRVNN(ON)GLGL(MAX)

VCf

1ICf

1IV2

)R(R2IV

−×

×−×

×−×

++××≥

where RDRVNN(ON) and RDRVNP(ON) resistance values depend on the VIN1 voltage levels, VDIODE is the forward-voltage drop of the charge-pump diode.

Applications Information (Step Up Converter) External components of boost converter can be designed by performing simple calculations. It need to follow regulation by the output voltage and the maximum load current, as well as maximum and minimum input voltages. Begin by selecting an inductor value. Once L is know, choose the diode and capacitors.

Inductor Selection A 4.7uH to 15uH is recommended for general used. The value of inductor depends on the operating frequency. Higher frequency allows smaller inductor and capacitor but increase internal switching loss. Two inductor parameters should be considered, current rating and DCR. The DCR of inductor affects the efficiency of the converter. The inductor with lowest DCR is chosen for highest efficiency. The inductor value can be calculated as:

DI

I

IIIMAIN

LAVG

LLAVGLpeak

−=

Δ+=

1

2

where: IL is the inductor peak-to-peak current ripple and is decided by:

OSC

inL f

DL

VI ×=Δ

D is the MOSFET turn on ratio and is decided by:

O

inO

VVV

D−

=

fOSC is the switching frequency. The inductor should be chosen to be able to handle this current and inductor saturation current rating should be greater than IPEAK.

Inductor Selection (Step Down Converter) Inductor selection depends on input voltage, output voltage, maximum current, switching frequency and availability of inductor values. The following buck circuit equations are useful in choosing the inductor values based on the application. Choose an inductor that does not saturate under the maximum rating load conditions. The magnitude of inductance is selected to maintain a peak to peak ripple current of 30% of the maximum load current.

The peak inductor current is given by:

D is the MOSFET turn on ratio where: IL is the inductor peak-to-peak current ripple and is decided by: fOSC is the switching frequency. The inductor should be chosen to be able to handle this current and inductor saturation current rating should be greater than IPEAK.

in

O

inLAVG

LLAVGLpeak

VV

D

DI

I

III

=

=

Δ+=

2




Capacitor Selection The FP6797 is permissible in using ceramic capacitor for TFT LCD panel application. The value of capacitor depends on acceptable voltage ripple.

The input capacitor can reduced peak current and noise at power source. It should have 22uF at least and can be increased for better input voltage filtering. Select the input capacitor to meet the input ripple current and voltage rating. When selecting an output capacitor, consider the output ripple voltage and the ripple current. The ESR of capacitor is a major factor to the output ripple. For best performance, a low ESR output capacitor is required. The ripple voltage is given by:

)**8

1(Cof

ESRIV LO +Δ=Δ

The common aluminum-electrolytic capacitors have high ESR and should be avoided. Ceramic capacitors have the lowest ESR in general. It uses 22uF ceramic output capacitors for the FP6797.

Diode Selection For diode selection, both forward voltage and diode capacitance need to be considered. The output diode should be rated to the output voltage and peak switch current. Schottky diodes, with their low forward voltage drop and fast reverse recovery, are the ideal choices for FP6797 applications. Make sure the diode’s peak current rating is at least IPK and its breakdown voltage exceeds VS.

Compensation (Step Up Converter) The step-up loop can be compensated by a bypass capacitor across the upper resistor of FB1 pin. The feed-forward capacitor can provide a good load transient response and a stable converter loop. The feed-forward capacitor sets a zero with upper resistor of FB1 pin in the control loop. The zero frequency is given by:

1121

RCf

FZ ××π×=

CF1 is the feed-forward capacitor.

Layout Consideration Careful printed circuit layout is extremely important to avoid causing parasitical capacitance and line inductance. The following layout guidelines are recommended to achieve optimum performance.

‧ Please the PWM converter diode and inductor close to the LX1.2 pin and no via.

‧ Please ceramic bypass capacitors near the VIN1,2 , SUPP and REF pin. The ground connection of the VIN bypass capacitor should be connected directly to the GND pin with a wide trace.

‧ Place Cout, C5 next to schottky diode as possible.

‧ Use wide traces and trace length is short as possible to the LX1,2 node.

‧ Using a bypass capacitor to GND to reduce noise coupling into OS pin.

‧ Keep the noise-sensitive feedback (FB1, FB2, FBP, and FBN) away from the switching node.

‧ Place the flying capacitors as close as possible to the DRVP and DRVN pin.

‧ The power ground (PGND) and signal ground (GND) pins should be connected at only one point.

‧ The exposed pad, on the underneath of the package, should be soldered to an equivalent area of metal on the PCB. This contact area should have multiple via connections to the back of the PCB as well as connections to intermediate PCB layers. if available, to maximize thermal dissipation away from the IC.



Outline Information TSSOP-28 Package (Unit: mm)

DIMENSION IN MILLIMETER SYMBOLS UNIT MIN NOM MAX

A --- --- 1.20

A1 0.00 --- 0.15

A2 0.80 1.00 1.05

b 0.19 --- 0.30

D 9.60 9.70 9.80

E1 4.30 4.40 4.50

E 6.40 BSC

e 0.65 BSC

L1 1.00 REF

L 0.45 0.60 0.75

S 0.20 --- ---

E2 --- 3.0 REF ---

D1 --- 5.33 REF ---

θ 0º --- 8º

Note 1：Followed from JEDEC MO-153-F.

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