First Results from CMOS-Integrated SPAD and SiPM - …sensl.com/downloads/irp/A_IEEE17_First...
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First Results from CMOS-Integrated SPAD and SiPM SensL Technologies Ltd., 6800 Airport Business Park, Cork, Ireland Salvatore Gnecchi, Stephen Bellis, Deborah Herbert, Carl Jackson SiPM with Integrated TDC (Q1 2018) ** www.sensl.com [email protected] +353 21 240 7110 (International) +1 650 641 3278 (North America) SPAD Array with CMOS Integration for a Scanning ToF System (Q1 2018) Time-of-Flight Positron Emission Tomography (ToF-PET) systems seek to optimize the coincidence resolving time (CRT) between a pair of radiation detection elements in order to provide superior image quality. The CRT is dependent on many factors, but in recent years the focus has been on maximizing the PDE (photon detection efficiency) of the Silicon Photomultipliers (SiPM). For the SiPM, the currently available PDE is close to its theoretical maximum and further development are unlikely to yield significant system level CRT improvements. SensL believe that future progress in the field of ToF-PET will be driven by improved system integration, incorporating active CMOS elements on the sensor chip to improve SiPM timing and signal routing. To provide the best system performance possible, SensL developed an integrated process using dedicated layers for the SPAD (single photon avalanche diode) and SiPM microcells. The process uses 0.35mm CMOS technology and has been used to create a number of test chips that feature integrated analog test circuits, with P-on-N SPAD and SiPM sensors. Here we present the initial testing of a 7x7 microcell SiPM sensor that includes an on-chip amplifier that was created using the new integrated process. The SiPM characterization of IV, PDE and pulse shape presented. Going forward, SensL plans to develop a range of products which benefit from CMOS integration. An example is a SPAD array designed for LiDAR ToF applications. An integrated time to digital converter (TDC) has also been designed using this process. Both are presented below. The Problem: • Further improvements in ToF-PET performance require improved system integration, with CMOS readout elements incorporated on-chip. • The best performing scintillators for ToF-PET emit in the blue portion of the spectrum. • PDE is the most important raw sensor parameter in ToF PET and therefore integration with CMOS must be carefully performed to maintain raw performance. SiPM with Amplifier Test Chip (Q4 2017) * Pandion is a new blue sensitive, SPAD array product developed by SensL. The product will be available in Q1 2018. • 100 x 400 SPAD array • 10 mm SPAD pixels • 21% Fill factor • Fill factor is dependant on pixel size. • Edoardo Charbon’s group at TUDelft, has designed a sensor that implements digitization of an analog SiPM’s fast output on chip. • The design comprises a comparator bank, time-to-digital converters (TDC), and electronics for interfacing with external electronics. • The TDC is a multipath, gated ring oscillator with a counter and phase detector, implemented in 0.35 μm CMOS technology. • Simulation results indicate a highly linear behavior, with an LSB equal to 64.49 ps and a DNL = +/-0.55 LSB and INL =+/-1 LSB. Abstract • SiPM composed of 7 x 7, 35 mm microcells • SiPM size is 300 mm x 300 mm • Cathode connected to bias • Anode is connected to an on-chip amplifier • The SiPM+amplifier chip is mounted on a test board with a wide-band amplifier (See block diagram below). The Solution: How to Get There: • SensL has developed an integrated CMOS plus SPAD process using dedicated layers for the SPAD and SiPM microcells. • This allows SensL to retain high blue sensitivity in line with C-Series and J-Series products. • The process can be used to implement a variety of analog and digital circuitry. • The new process has been used to create test chips containing single SPAD and SiPM sensors with an integrated amplifier circuitry proving functionality and high performance of the SPAD and SiPM sensors. • This technique can be extended to a SPAD array where every element is addressable, as in the Pandion project. • The next step is to incorporate digital components, such as a TDC, as per our collaboration with TUDelft. Each Pandion pixel is comprised of: • SPAD • Quenching transistor • 1 bit ADC / Comparator • SPAD reset • SPAD select • SPAD disable • Output buffer. The Pandion imager is intended to be used in a scanning system with the following operation: • Select column or columns (nearest neighbour) • Fire laser • Timestamp 100 signals with off- chip TDC • Repeat for next column. IV Plot • IV plot of the SiPM+amplifier • Wafer-level measurements of SiPM test die show a Vbr in-line with that of C-Series sensors (24.45 V) • Optical sensitivity verified through increase in light level current flow. SiPM Output • Output of the current buffer is AC coupled 50 Ω oscilloscope load • Dark response and single photoelectron spec- trum clearly seen • Signal PE amplitude ≈ 5 mV • SPE histogram peaks can be seen at 1, 2 and 3 p.e. Pulse Shape • Onset time (10 – 90%): 890 ps • Recovery time: 65 ns • Output connected to 50 Ω oscilloscope • In laboratory dark box • Averaging set to 1024 waveforms • Trigger level set to ≈ 8 p.e. Photon Detection Efficiency • The PDE is plotted as a function of overvoltage at 420 nm. • At Vbr +5 V, the PDE was found to be 38 %, which is in line with the PDE of our C-Series sensors (40 %). * This work was carried out with our industrial partner, GE Global Research. Test chip mounted on PCB Circuit schematic Single photoelectron response as measured on an oscilloscope ** This work is described in paper N-08-5 “Towards a fully digital state-of-the-art analog SiPM”, by A. Muntean et al., presented at this conference.
Transcript of First Results from CMOS-Integrated SPAD and SiPM - …sensl.com/downloads/irp/A_IEEE17_First...
First Results from CMOS-Integrated SPAD and SiPMSensL Technologies Ltd., 6800 Airport Business Park, Cork, Ireland
Salvatore Gnecchi, Stephen Bellis, Deborah Herbert, Carl Jackson
SiPM with Integrated TDC (Q1 2018) **
www.sensl.com
+353 21 240 7110 (International)
+1 650 641 3278 (North America)
SPAD Array with CMOS Integration for a Scanning ToF System (Q1 2018)
Time-of-Flight Positron Emission Tomography (ToF-PET) systems seek to optimize the coincidence resolving time (CRT) between a pair of radiation detection elements in order to provide superior image quality. The CRT is dependent on many factors, but in recent years the focus has been on maximizing the PDE (photon detection efficiency) of the Silicon Photomultipliers (SiPM). For the SiPM, the currently available PDE is close to its theoretical maximum and further development are unlikely to yield significant system level CRT improvements. SensL believe that future progress in the field of ToF-PET will be driven by improved system integration, incorporating active CMOS elements on the sensor chip to improve SiPM timing and signal routing.
To provide the best system performance possible, SensL developed an integrated process using dedicated layers for the SPAD (single photon avalanche diode) and SiPM microcells. The process uses 0.35mm CMOS technology and has been used to create a number of test chips that feature integrated analog test circuits, with P-on-N SPAD and SiPM sensors. Here we present the initial testing of a 7x7 microcell SiPM sensor that includes an on-chip amplifier that was created using the new integrated process. The SiPM characterization of IV, PDE and pulse shape presented.
Going forward, SensL plans to develop a range of products which benefit from CMOS integration. An example is a SPAD array designed for LiDAR ToF applications. An integrated time to digital converter (TDC) has also been designed using this process. Both are presented below.
The Problem:• Further improvements in ToF-PET performance require improved system integration, with CMOS
readout elements incorporated on-chip. • The best performing scintillators for ToF-PET emit in the blue portion of the spectrum.• PDE is the most important raw sensor parameter in ToF PET and therefore integration with CMOS
must be carefully performed to maintain raw performance.
SiPM with Amplifier Test Chip (Q4 2017) *
Pandion is a new blue sensitive, SPAD array product developed by SensL. The product will be available in Q1 2018.
• 100 x 400 SPAD array
• 10 mm SPAD pixels• 21% Fill factor• Fill factor is dependant on pixel size.
• Edoardo Charbon’s group at TUDelft, has designed a sensor that implements digitization of an analog SiPM’s fast output on chip.
• The design comprises a comparator bank, time-to-digital converters (TDC), and electronics for interfacing with external electronics.
• The TDC is a multipath, gated ring oscillator with a counter and phase detector, implemented in 0.35 μm CMOS technology.
• Simulation results indicate a highly linear behavior, with an LSB equal to 64.49 ps and a DNL = +/-0.55 LSB and INL =+/-1 LSB.
Abstract
• SiPM composed of 7 x 7, 35 mm microcells
• SiPM size is 300 mm x 300 mm
• Cathode connected to bias
• Anode is connected to an on-chip amplifier
• The SiPM+amplifier chip is mounted on a test board with a wide-band amplifier (See block diagram below).
The Solution:
How to Get There:
• SensL has developed an integrated CMOS plus SPAD process using dedicated layers for the SPAD and SiPM microcells.
• This allows SensL to retain high blue sensitivity in line with C-Series and J-Series products.• The process can be used to implement a variety of analog and digital circuitry.
• The new process has been used to create test chips containing single SPAD and SiPM sensors with an integrated amplifier circuitry proving functionality and high performance of the SPAD and SiPM sensors.
• This technique can be extended to a SPAD array where every element is addressable, as in the Pandion project.
• The next step is to incorporate digital components, such as a TDC, as per our collaboration with TUDelft.
Each Pandion pixel is comprised of:
• SPAD
• Quenching transistor
• 1 bit ADC / Comparator
• SPAD reset
• SPAD select
• SPAD disable
• Output buffer.
The Pandion imager is intended to be used in a scanning system with the following operation:
• Select column or columns (nearest neighbour)
• Fire laser• Timestamp 100 signals with off-
chip TDC• Repeat for next column.
IV Plot
• IV plot of the SiPM+amplifier
• Wafer-level measurements of SiPM test die show a Vbr in-line with that of C-Series sensors (24.45 V)
• Optical sensitivity verified through increase in light level current flow.
SiPM Output
• Output of the current buffer is AC coupled 50 Ω oscilloscope load
• Dark response and single photoelectron spec-trum clearly seen
• Signal PE amplitude ≈ 5 mV
• SPE histogram peaks can be seen at 1, 2 and 3 p.e.
Pulse Shape
• Onset time (10 – 90%): 890 ps
• Recovery time: 65 ns
• Output connected to 50 Ω oscilloscope
• In laboratory dark box
• Averaging set to 1024 waveforms
• Trigger level set to ≈ 8 p.e.
Photon Detection Efficiency
• The PDE is plotted as a function of overvoltage at 420 nm.
• At Vbr +5 V, the PDE was found to be 38 %, which is in line with the PDE of our C-Series sensors (40 %).
* This work was carried out with our industrial partner, GE Global Research.
Test chip mounted on PCB
Circuit schematic
Single photoelectron response as measured on an oscilloscope
** This work is described in paper N-08-5 “Towards a fully digital state-of-the-art analog SiPM”, by A. Muntean et al., presented at this conference.
