FinFET: a mature multigate MOS technology? A wideband transistor simulation and characterization...
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![Page 1: FinFET: a mature multigate MOS technology? A wideband transistor simulation and characterization approach J.-P. Raskin 1, T.M. Chung 1, D. Lederer 1, A.](https://reader035.fdocuments.in/reader035/viewer/2022062511/5519b8135503465b578b4888/html5/thumbnails/1.jpg)
FinFET: a mature multigate MOS technology?A wideband transistor simulation and
characterization approach
J.-P. Raskin1, T.M. Chung1, D. Lederer1, A. Dixit2, N. Collaert2,
T. Rudenko3, V. Kilchytska3, D. Flandre3
Université catholique de Louvain,1Microwave and 4Microelectronics Laboratories
Place du Levant, 3, B-1348 Louvain-la-Neuve, [email protected]
2IMEC, Kapeldreef, 75, B-3001 Leuven, Belgium
3ISP, Kiev
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Growing interest for MuG
• Strong limitations - Short Channel Effects - appearing for Single Gate MOS below 50 nm
• Many technological difficulties to satisfy the ITRS predictions, in terms of leakage current (IOFF), supply voltage, Early voltage, DIBL, cutoff frequency, etc.
• Multiple-gate MOSFETs (MuG) are considered as serious potential candidates
Planar MuG < > Non-planar MuG
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Planar MuG
• GAA: First planar DG MOS– Isotropic wet etching of BOX– good gate oxide-channel interfaces,
channel thickness controlled by highly selective wet etching
– Need: variable W/L >< GAA (W/L=1)
• Planar DG built by wafer bonding starting with SG MOS
– Gate stacks are not built at the same time (dissimetry)
– Misalignment of top and bottom gates
• Planar DG built by transfer of a thin Si film above a cavity
– Both gates are built simultaneously– Misalignment of top and bottom gates
GAA
[Colinge, SOI Conf. 90]
SON-GAA, ST-M, IEDM’03 DG, CEA-LETI, SOI Conf. 04
DG, UCL, SPIE 04
Self-aligned DG process, but no DG MOS yet
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Non-planar MuG
FinFET
FinFET, Triple gate
Omega gate, Pi-GateIMEC, SSE’04
Taiwan Semicon., IEDM’02
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RF analog factors of merit• Several good published articles investigated the intrinsic behavior
of MuG experimentally and through simulations: ION/IOFF, Subthreshold slope, Vth roll-off, DIBL.
• Analyses focused on RF analog performance – not limited to the channel behavior (impact of parasitics related to the 3-D structure)
Year Lmin / node
(nm)
tox (nm) gm/gds @ 5.Lmin Parasitic cap. (fF/µm)
fT (GHz)
2005 45 / 80 2.1 100 0.24 140
2006 37 / 70 1.9 100 0.24 170
2007 32 / 65 1.6 100 0.24 200
2009 25 / 50 1.4 100 0.24 280
2012 18 / 35 1.2 100 0.24 400
2015 12 / 25 1.0 100 0.24 700
ITRS
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Measured MuG
FinFET from IMEC
• Gate lengths L from 10 µm down to 50 nm
• Fin width Wfin from 10 µm down to 22 nm
• Fin height Hfin from 60 to 95 nm
• Fin spacing (Sfin) from 100 to 350 nm
• Nitrided gate oxide of 2 nm EOT
• NiSi salicide
Planar DG from UCL
• SiO2 gate oxide of 30 or 6 nm
• Si film of 87 nm
• BOX = 400 nm
• L from 20 down to 1 µm
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3-D Atlas simulations of SOI MOSFETs Multiple-Gate Devices in
static and dynamic regimes
Non-planar vs. planar MuG
• Single-, Double-, Triple-, and Pi-Gate MOS• L from 200 nm down to 25 nm• Hfin = 50 nm• Tsi = Wfin = 20 nm• Tox = 2 nm• Tbox = 150 nm• Channel doping = 1015 cm-3 (undoped)
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V th (V) S (mV/dec) DIBL (mV/V) L
(nm)
tSi
(nm)
Vds (V)
SG DG TG PG SG DG TG PG SG DG TG PG
0.05 0.32 0.35 - - 64.0 59.9 - - 200 20
1.00 0.28 0.36 - - 65.1 59.9 - - 47 11 - -
0.05 0.28 0.37 0.40 0.40 84.9 61.1 59.8 60.7 100 20
1.00 0.16 0.35 0.38 0.38 80.5 61.1 61.3 60.6 126 16 21 21
0.05 0.20 0.37 0.40 0.40 124.5 63.8 61.8 62.8 75 20
1.00 -0.095 0.34 0.38 0.38 110.1 64.4 62.7 63.1 395 32 21 26
0.05 0.045 0.35 0.39 0.40 198.5 77.3 75.3 74.2 50 20
1.00 -0.75 0.27 0.33 0.33 282.9 81.8 78.7 77.3 837 89 63 74
0.05 - - 0.32 0.33 - - 232.5 183.9 25 20
1.00 - - -0.35 -0.32 - - 445.4 365.3 - - 700 674
Static simulation results
- Roll-off Vth , degradation of S and DIBL for SG for Lg < 100 nm Solution: Reduce Si channel thickness (Vth control), but
technological problems in terms of uniformity and increase of Rs and Rd.
- Pi-gate present slightly better results, lower SCE
- At L = 25 nm, MuG with tSi = Wfin = 20 nm show degradation of their performance
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Gm/Id: efficiency to convert DC to AC
Intrinsic voltage gain = Gm/Gd = Gm/Id x Id/Gd
= Gm/Id x VEA
FinFETs Planar SOI SG and DG
Measurement results
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Volume inversion (VI)
1E+10
1E+12
1E+14
1E+16
1E+18
1E+20
0.0 0.3 0.5 0.8 1.0Vgs (V)
Ele
ctr
on
co
nc
en
tra
tio
n (
cm
-3)
0
200
400
600
800
1000
1200
Mo
bil
ity
(c
m2 V
-1s
ec-1
)
SurfaceCentre
Simulation results
• Clear interest for DG for channel length < 100 nm
• VI is not efficient at high Vgo
Undoped DG and SG - - - 100 nm DG MOSFET
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Early Voltage vs Wfin and L
FinFETs
Measurement results
L = 10 µm
VEA for FinFET in VI regime is 10 x higher than for FD SOI
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Intrinsic analog gain
Higher intrinsic gain for FinFET of around 20 dB compared to FD SOI MOS
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Dynamic analysis of MuGSimulation results
At low Vgo, the gmMuG/gmSG and CgsMuG/CgsSG ratios are > 1
At higher Vgo, no improvement on normalized gm for MuG over SG
Volume inversion in MuG only efficient at lower Vgo
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Miller capacitance Cgd
Cgs/Cgd: Ratio of Control capacitance of the channel to Parasitic feedback Miller capacitance.
MuG devices achieve a higher value of Cgs/Cgd as compared to SG devices
Measured Cgs/Cgd = 3
for 60 nm FinFET
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3-D parasitic capacitances
Higher parasitic capacitances: TG > DG > SG due to more complex 3-D interconnection Main part of the parasitic capacitance is related to fringing field between
gate-to-source and gate-to-drain through BOX
Normalized Cgs
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Cutoff frequency
- For long L, fT of SG slightly higher due to lower parasitic C compared to MuG
- At small L, SG device, very high SCE, leading to bad fT value
- Even MuG devices with L < 40 nm, degradation appears
- To follow up the ITRS, we have to reduce Wfin or tsi as well as EOT (high-k)
Vgo = 500 mV and Vds = 1 V
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FinFET: very promising technological solution at short term
Advantages: - higher technological maturity than planar DG- parasitic capacitances related to the 3-D FinFET structure are only slightly higher than for SG
Disadvantages: - reduced mobility for electrons (<110> cristalline orientation)- control of Wfin by etching + gate interface quality
- higher source/drain resistances
Conclusions – Maturity of FinFETs?
Rs, Rd → reduced gm → lower fT and fmax
Rg → reduced fmax
Short term technological challenges: gate interface quality, silicidation S/D orLow Schottky Barrier S/D contacts, integration density
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Acknowledgements
• UCL clean rooms team• Mr. P. Simon for RF measurements• Dr. Jurczak Malgorzata’s group, IMEC• SINANO