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FinFET technology for wide-channel devices with ultra-thin silicon body
V. Jovanović, T. Suligoj, P. Biljanović, L.K. Nanver*
University of Zagreb, Department of Electronics, Faculty of Electrical Engineering and Computing, Unska 3, Zagreb, Croatia; Tel: +385 (0)1 6129671 Fax: +385 (0)1 6129 E-mail: [email protected]
*ECTM-DIMES, Delft University of Technology, P.O. BOX 5053, 2600 GB Delft, The Netherlands
Abstract – Crystallographic silicon etching with TMAH is employed on (110) bulk silicon wafers for the etching of silicon fins with ultra-high aspect-ratio. Thin silicon-nitride spacers are used as the hard-mask and the etched fins are isolated from the substrate by the thick oxide layer. Silicon dioxide and n+-polysilicon form the gate-stack of the FinFETs. The height of the etched fins exceeds 1 μm and the height of the active region is between 300 nm and 600 nm. From the SEM analysis, the width of the fins is estimated in the range of 10 nm, giving the record-high aspect-ratio of the fin geometry. Both n- and p-channel devices are demonstrated and show low leakage and good subthreshold performance. Common to all devices with thin, fully-depleted body with the polysilicon gate, the threshold voltages require special adjustment to make them suitable for CMOS operation and the high-k/metal gate-stack with the possibility of work-function engineering is the optimum solution for the further investigation of these devices.
The scaling of CMOS devices is moving towards the physical limits that can be achieved with the standard bulk technology. The off-state current and standby power are increasing with shorter channel-lengths since it is becoming more difficult to keep the electrostatic integrity of devices – channel doping needs to be increased and the source and drain junctions need to become more shallower, but these trends are offset by the increased junction leakage and higher series resistances. Fully-depleted devices, double-gate devices in particular, offer significantly better electrostatic integrity and hence, better short-channel immunity. FinFETs are seen as the most likely candidate for the successor of the bulk CMOS from the 22 nm node onwards, because of its compatibility with the current CMOS technology. Many different ICs with FinFETs have already been demonstrated, ranging from digital logic, SRAM, DRAM to Flash memory [1-3]. Furthermore, due to their superior subthreshold performance and excellent current saturation they offer advantages for the high-gain analog applications and are steadily reaching better results in RF applications .
Vertical orientation of the FinFET’s conductive plane offers the possibility of increasing the channel-width with taller fins, while the area used on the silicon wafer remains the same . Moreover, the cut-off frequency fT and the maximum frequency of oscillations fmax can be improved in multi-fin devices when the same channel width is distributed over the smaller number of taller fins compared to the larger number of shorter ones . However, since device performance is strongly dependant on the channel thickness, i.e. fin-width, the etching process with very high anisotropy is required for the maximization of the fin-
height, as well as the appropriate hard-mask for this etching. Previous work has been done on the hard-mask for the fin-etching and the etching itself, with the best results obtained for the silicon-nitride hard-mask and crystallography-sensitive etching on (110) bulk silicon wafers [7,8] and initial results of devices fabricated in the tall-fin, i.e. wide-channel FinFET process have been reported in .
The processing of the fin-structures on bulk silicon wafers, isolated from the substrate is presented in the first part of Chapter II, followed by the description of the MOS devices processed on these structures. Chapter III gives the summary of the measured electrical characteristics of the processed devices and conclusions are listed in Chapter IV.
II. DEVICE FABRICATION A. Processing of tall fin-structures
The etching of tall fin-structures requires very high etching anisotropy to keep the fins narrow, which is required for the highly-scaled devices, while maximizing the fin-height. The previous experiments with silicon etching showed that the best results were achieved by the crystallographic etching using TMAH (25 %, 85°C) on silicon wafers with (110) surface orientation, where perfectly-vertical fins are formed on (111) planes exposed by TMAH [7,8]. The silicon-nitride spacer hard-mask, built around the sacrificial oxide island, was used for the fin-etching. However, the hard-mask formation for the devices was changed in order to make use of the TMAH etching and create almost perfectly vertical spacers, as explained in Fig. 1. With the new spacer-formation process
depositionWet chemical etching
of oxide TMAH etching
Si SiO2 SiNX Fig. 1. Silicon-nitride-spacer hard-mask formation for the etching of thin silicon fins. The oxide hard mask is aligned with the (111) planes on (110) bulk silicon wafers which are exposed by the short TMAH etch. After oxide removal, nitride layer is deposited and etched by RIE to form spacers.
the spacers are formed around the supporting silicon-hill and any residual oxide beneath the nitride spacer can be removed. This oxide can be removed during the HF-dip necessary before the fin-etching by TMAH and consequently cause the spacer lift-off.
The spacer-process shown in Fig. 1. was applied to the (110) bulk silicon wafers after the well-implantations and annealing steps. Additional oxide pad-regions were created from the LPCVD oxide layers (Fig. 2.) and they serve to mask the underlying regions during TMAH etching and create large pads suitable for the placement of the source and drain contacts. Figure 3. shows the approximately
1 μm tall and very narrow fin-structures with larger pad regions. As can be seen from Fig. 3.b the narrow fins remain mechanically stable over long distances, even without the supporting pads. However, the pad sides are neither rectangular nor vertical since TMAH reveals the crystal planes which are etched slowly – typically different (111) crystal planes. The characteristic planes that remain after the silicon etching limit the minimum distance between the gate and the source and drain pads.
The isolation of the etched fins was achieved by depositing thick LPCVD oxide layer, which is then densified and planarized using the chemical-mechanical polishing [8,10]. Silicon-dioxide etch-back by the buffered-HF (1:7) solution exposes the top part of the fin, later used for the active device region, as seen in Fig. 4. Using the scanning electron-microscope analysis of the fin cross-section (Fig. 4.b), the fin-width is estimated to be in the range of 10 nm, which can support the gate-lengths below 35 nm, whereas the height of the active part of the fin was varied between 300 nm and 600 nm. In the device run, the nitride-spacer hard-mask was removed before the steps for the fin-isolation. B. MOS devices on tall fins
The demonstration devices were processed to prove the concept of the FinFETs built on tall and narrow fin structures. Since the goal was to demonstrate the feasibility of the concept, the targeted gate-lengths of the devices were in the 0.5 μm range and the equivalent oxide thickness of the gate dielectric was aimed at 5 nm. The standard gate-stack with thermally-grown silicon-dioxide
Fig. 2. Hard-mask for silicon etching. Two sides of the thin nitride mask are aligned to (111) crystal planes and large oxide pad-regions are used to mask larger areas for source and drain contacting
Fig. 3. Tall fin-structures etched by TMAH (25 %, 85°C). Characteristic pattern of the exposed non-vertical crystal planes can be observed on the pad regions (a). Thin fins are mechanically stable over long distances, even without the supporting pads (b).
Fig. 4. Isolated fin-structures. Thick oxide layer is deposited by LPCVD, densified at 1050°C for 1 h, planarized by CMP and etched-back by buffered-HF (1:7) exposing the top part of the fins (a). The fin-width is below 20 nm, estimated from the cross-sectional view (b).
as the gate dielectric and LPCVD polysilicon as the gate material was used for the formation of the demonstration MOSFETs. Test runs with MOS capacitors formed by the same process as the gate-stack of the FinFETs were done in order to determine the correct furnace-oxidation parameters and the equivalent oxide thickness was extracted from the C-V measurements of the MOS capacitors. Figure 5.a shows the typical C-V measurements obtained for the capacitor, which exhibits no hysteresis effect indictating good oxide quality. Furthermore, the I-V measurements in Fig. 5.b show very low leakage currents through the gate-oxide, which is also proportional to the capacitor area, implying there are no local leakage points even for larger caapcitors. The oxidation temperature and time chosen for the demonstration FinFETs were 800°C and 16 min 30 s, respectively, while the undoped polysilicon was first deposited and later doped with phosphorous from the POCl3 source.
The patterning of the gate polysilicon requires extremely high selectivity to the underlying gate oxide, which is particularly demanding for the RIE recipes on very tall fins where the polysilicon is being removed in the vertical direction. Therefore, to prevent the damage to the gate oxide and possible removal of the silicon fins during the gate patterning, the etching was done using the highly-selective TMAH solution. The thermal oxide was grown on the polysilicon surface after the polysilicon doping and is used as the hard-mask for the gate etching. The results in Fig. 6. show the patterned polysilicon-gate running over
the thin fin which was protected from the TMAH by the gate oxide. The edges of the gate are rough due to the grain structure of the gate polysilicon that etches differently in TMAH, depending on the orientation of the grain crystal. Analysis of the SEM measurements was used to relate the final gate-length to the values designed in layout.
The implantations at tilt angle of 60° were used for the doping of the source and drain, followed by the additional implantations into the source and drain pads for the reduction of the series resistance. Because of the long fin-extensions between the channel region and the source and drain pads, series resistances can increase and high doping is required for these extensions to minimize the resistances. For this reason, the furnace annealing at 950°C for 20 min was done after the deposition of the isolation oxide, opening of the contact holes and final implantations into the contacts, in order to reliably activate the dopants. Since the gate-lengths of the processed devices are in the 0.5 μm range or longer, larger dopant diffusion caused by such an annealing step can be tolerated.
III. ELECTRICAL MEASUREMENTS OF DEVICES
The transfer and the output curves measured on the processed p-channel and n-channel devices are shown in Figs. 7. and 8., respectively, and extracted device parameters are summarized in Table I. Both the pFETs and nFETs exhibit almost ideal subthreshold performance, evident by the very low drain-induced barrier-lowering, (DIBL < 10 mV/V) and the inverse of the subthreshold slope which is close to the theoretical limit (S < 64 mV/dec), as can be observed in Figs. 7.a and 8.a. This is in accordance with the very thin, fully-depleted channel compared to the gate-length of 410 nm. Moreover, the measured leakage currents are low, indicating good quality of the gate-stack and the source and drain junctions. The low-DIBL figure can also be observed in the output characteristics in Figs. 7.b and 8.b which show excellent current saturation that transfers into large output resistances and makes these devices suitable for high-gain applications. The unexpected result is the larger output
-2 -1 0 10
Gate voltage, V
square, 100 x 100 μm2
square, 80 x 80 μm2
0.0 0.5 1.0 1.5 2.01E-9
Gate voltage, V
tOX = 3.8 nm tOX = 4.0 nm
Fig. 5. Properties of the MOS capacitors used for the development of the gate-stack. C-V measurements are used to extract the equivalent electrical thickness of the oxide (a). The leakage current in the I-V measurements comes from the direct tunneling and scales with the capacitor area, indicating there are no local leakage points (b).
Fig. 6. Patterning of the gate polysilicon by TMAH. Thermal oxide grown on the polysilicon surface is patterned first to create the hard-mask for the TMAH etching. Rough edges of the gate are caused by the polysilicon grain-structure since the etching is sensitive to the crystal orientation of the grains.
current of the pFETs compared to the nFETs, which needs closer examination. One reason for this anomaly lies in the slightly higher substrate doping of the n-channel devices, estimated at 2⋅1017 cm-3 from the simulation, whereas the p-channel transistors have the well doping of 3⋅1016 cm-3. Furthermore, the C-V measurements on the large devices processed in parallel with the FinFETs reveal that the nFETs suffer from the depletion of the gate polysilicon when devices are in the on-state, which reduces the gate capacitance and lowers the output current. From the output characteristics in Figs. 7.b and 8.b, the influence of the source and drain series resistance can also be observed, with devices with smaller distance between the gate and the source and drain pad regions exhibiting significantly larger output currents and higher slope of the characteristics in the linear region. Nevertheless, even with high series resistance, the output current per single fin of the measured devices is comparable to the best results achieved by the industry for the multi-gate FETs which also have significantly shorter gates [11-13].
The gate-stack and the substrate doping of the processed FinFETs were not optimized for the proper threshold voltage required for the CMOS integrated circuits and the final threshold values (nFET: Vth = -0.1 V,
pFET: Vth = -1.1 V) need further adjustments. This is particularly the case for the pFETs since they typically require p+-polysilicon gate. The adjustement of the threshold voltage is an issue with all fully-depleted MOSFETs and will most probably be taken care of by the workfunction engineering of the metal gate which is likely
-2.0 -1.5 -1.0 -0.5 0.010-13
-I D, μ
-I D, A
Lg = 410 nmVDS = -50 mV, -1 VVth = -1.1 VS = 63.3 mV/decDIBL = 5.8 mV/V
-2.5 -2.0 -1.5 -1.0 -0.5 0.00
-I D, μ
VGS = -1,...,-2.2 VΔVGS = -0.2 V
D = 0.8 μm D = 1.5 μm
Fig. 7. Transfer (a) and output (b) characteristics of the processed p-channel FinFETs with 410 nm long gates and 400 nm tall active part of the fin. Devices exhibit nearly-ideal subthreshold performance, low leakage currents and excellent current saturation. Series resistance increases with longer source/drain extensions and degrades device performance (b).
-1.0 -0.5 0.0 0.5 1.010-13
Lg = 410 nmVDS = 50 mV, 1 VVth = -0.1 VS = 62.4 mV/decDIBL = 7.4 mV/V
I D, μ
I D, A
0.0 0.5 1.0 1.5 2.0 2.50
I D, μ
VGS = -0.2,...,1 VΔVGS = 0.2 V
D = 0.5 μm D = 0.8 μm
Fig. 8. Transfer (a) and output (b) characteristics of the processed n-channel FinFETs with 410 nm long gates and 400 nm tall active part of the fin. Devices exhibit nearly-ideal subthreshold performance, low leakage currents and excellent current saturation, but the output current is lower compared to the pFETs due to the higher substrate doping and gate depletion effects.
ELECTRICAL PARAMETERS OF PROCESSED P- AND N-CHANNEL FINFETS
pFET nFET Gate length, nm 410 410 Channel width, nm ~ 2 × 400 ~ 2 × 400 Vth, V -1.1 -0.1 Ion, μA 40.4 17.6 Ioff, A < 5⋅10-13 < 4⋅10-13 gm,max, μA/V (⏐VDS⏐ = 1 V)
39.9 (VGS = -1.75 V)
15.6 (VGS = 0.40 V)
S, mV/dec 63.3 62.4 DIBL, mV/V (⏐ID⏐ = 10 nA) 5.8 7.4
rd, MΩ (⏐VDS⏐ = 1.75-2.5 V)
2.75 (VGS = -2.2 V)
1.72 (VGS = 1 V)
to replace the polysilicon as the gate material in the near future.
The concept of the wide-channel FinFET built on tall fin-structures with very high aspect-ratio has been proven by the demonstration MOS devices. High anisotropy of the silicon fin-etching was achieved by using the TMAH solution on silicon wafers with (110) surface orientation, which exposes vertical (111) planes. Devices are isolated from the substrate with the thick oxide layer formed by the deposition, planarization and etch-back. The gate-stack consists of approximately 5 nm thick thermal oxide layer and n+-polysilicon gate, which is later patterned by TMAH, followed by the source and drain formation, contacting, annealing and metalization steps. The measured devices exhibit nearly-perfect subthreshold performance, but the threshold voltage needs adjustment to reach the typical values demanded for the CMOS ICs. Output characteristics reveal the higher current of pFETs and this anomaly can be traced to the slightly higher substrate doping and the gate-depletion that can be observed for the nFETs. However, devices show great potential with very high output current per single fin, and can be further improved with the more advanced processing of the gate-stack and the source and drain regions, namely by reducing the gate-length, having shorter annealing times and selective epitaxy in the source and drain regions to reduce the series resistance.
The authors wish to thank DIMES ICP staff for the help during processing, in particular Silvana Milosavljević and Tom Scholtes for their overall assistance, Mario Laros for the RIE processing, Alex van den Bogaard for the furnace processing and John Slabbekoorn for the implantation setup. Special thanks go to Jaber Derakhsandeh for the CMP assistance, Francesco Sarubbi for the electrical measurements, and Henk van Zeijl and Yann Civale for the contributing discussions.
REFERENCES  Sung Hwan Kim, Hyun Jun Bae, Sung In Hong, Yong Lack
Choi, Eun Jung Yoon, Ho Ju Song, Chang Woo Oh, Yong-Seok Lee, Hong Cho, Dong-Won Kim, Donggun Park, Won-Seong Lee, “High performance Silicon-on-ONO (SOONO) cell array transistors (SCATs) for 512Mb DRAM cell array application”, Intl. Electron Device Meeting Tech. Digest, pp. 35-38, Dec. 2007.
 Satoshi Inaba, Hirohisa Kawasaki, Kimitoshi Okano, Takashi Izumida, Atsushi Yagishita, Akio Kaneko, Kazunari Ishimaru, Nobutoshi Aoki, Yoshiaki Toyoshima, “Direct evaluation of DC characteristics variability in FinFET
SRAM cell for 32 nm node and beyond”, Intl. Electron Device Meeting Tech. Digest, pp. 487-490, Dec. 2007.
 Tzu-Hsuan Hsu, Hang Ting Lue, Ya-Chin King, Jung-Yu Hsieh, Erh-Kun Lai, Kuang-Yeu Hsieh, Rich Liu, Chih-Yuan Lu, “A high-performance body-tied FinFET bandgap engineered SONOS (BE-SONOS) for NAND-type flash memory”, IEEE Electron Device Letters, vol. 28, no. 5, pp. 443-445, May 2007.
 Vaidy Subramanian, Bertrand Parvais, Jonathan Borremans, Abdelkarim Mercha, Dimitri Linten, Piet Wambacq, Josine Loo, Morin Dehan, Cedric Gustin, Nadine Collaert, Stefan Kubicek, Robert Lander, Jacob Hooker, Florence Cubaynes, Stephane Donnay, Malgorzata Jurczak, Guido Groeseneken, Willy Sansen, Stefaan Decoutere, “Planar bulk MOSFETs versus FinFETs: an analog/RF perspective”, IEEE Trans on. Electron Devices, vol. 53, no. 12, pp. 3071-3079, Dec. 2006.
 Stephen H. Tang, Leland Chang, Nick Lindert, Yang-Kyu Choi, Wen-Chin Lee, Xuejue Huang, Vivek Subramanian, Jeffrey Bokor, Tsu-Jae King, Chenming Hu, “FinFET—A Quasi-Planar Double-Gate MOSFET”, IEEE Intl. Solid-State Circuits Conference Tech. Digest, pp. 118 –119, Feb. 2001.
 Wen Wu, Mansun Chan, “Analysis of geometry-dependent parasitics in multifin double-gate FinFETs”, IEEE Trans. on Electron Devices, vol. 54, no. 4, pp. 692-698, April 2007.
 Vladimir Jovanović, Silvana Milosavljević, Lis K. Nanver, Tomislav Suligoj, “Application of spacer hard-masks for sub-100 nm wide silicon fin-etching”, Proc. Annual Workshop on Semiconductor Advances for Future Electronics and Sensors, Nov. 2006.
 Vladimir Jovanović, Silvana Milosavljević, Lis K. Nanver, Tomislav Suligoj, Petar Biljanović, “Sub-100 nm silicon-nitride hard-mask for high aspect-ratio silicon fins”, Proc. Intl. Convention MIPRO , May 2007.
 Vladimir Jovanović, Tomislav Suligoj, Lis K. Nanver, “Crystallographic Silicon-etching for Ultra-High Aspect-Ratio FinFET”, Trans. of 213th Electrochemical Society Meeting, May 2008.
 Tomislav Suligoj, Kang L. Wang, “A novel isolation of pillar-like structures by the chemical-mechanical polishing and etch-back process”, Electrochemical and Solid-State Letters, vol. 8, no. 5, pp. 125-127, May 2005.
 B. S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, R. Chau, “High performance fully-depleted tri-gate CMOS transistors”, IEEE Electron Device Lett., vol. 24, no. 4, pp. 263-265, April 2003.
 A. Kaneko, A. Yagishita, K. Yahashi, T. Kubota, M. Omura, K. Matsuo, I. Mizushima, K. Okano, H. Kawasaki, S. Inaba, T. Izumida, T. Kanemura, N. Aoki, K. Ishimaru, H. Ishiuchi, K. Suguro, K. Eguchi, Y. Tsunashima, “Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm FinFET with elevated source/drain extension”, Intl. Electron Device Meeting Tech. Digest, pp. 844-847, Dec. 2005.
 F. Cornu-Fruleux, J. Penaud, E. Dubois, P. Coronel, G. Larrieu, T. Skotnicki, “Spacer-first damascene-gate FinFET architecture featuring stringer-free integration”, IEEE Electron Device Letters, vol. 28, no. 6, pp. 523-526, June 2007.