w ,

F ET-based MMICs and MICs are almost invariably designed

around a fixed FET, usual- ly specified as a set of S- parameters or an equiva- lent circuit. Foundry users, for example, may select a FET from a foundry manual or from a software library contained in a commercial circuit simulator. MIC designers may use the equivalent circuit or S-parameters provided on the manufac- turer's specification sheet. How should the average FET be derived from mea- surements of devices from a process in which varia- tions in technology inescapably lead to varia- tions in microwave behaviour?

TECHNOLOGICAL MEAN The "Average FET" is intended to be representa- tive of the particular pro- cess and must be synthe- sized from the results of measurements on many (perhaps hundreds) of fabricated devices. The "Average FET" should rep- resent a technologically average device: that is, one with mean values for doping density, gate length, recess depth, con- tact resistance and so on, obtained in the fabrica- tion process. The electri- cal performance of this "Average FET" can then be considered "typical" of the process and used as a basis for circuit designs. The "Average FET" is inherently the result of a statistical procedure involving averaging from spreads in technological parameters.

The technological mean can be obtained by find- ing, for each FET in the sample used to establish the "Average FET", the set of technological parame- ters which gave rise to its measured electrical per- formance. The averaged

Finding the Average GaAs

MESFET Among the Spreads

FET-based M M I C s a n d M l C s a re u s u a l l y d e s i g n e d a r o u n d a f ixed FET which is i n t e n d e d t o be t y p i c a l o f t h e p rocess w h i c h i t represents. This article addresses the q u e s t i o n o f w h e t h e r the electrical characteristics o f a t e c h n o l o g i c a l l y m e a n device are the same as t h o s e o f devices obtained by averaging the electrical characteristics of several d i f ferent devices.

Single FETs with S-param. Element

Wr=5OOA

Co c 0.177 Cg d 0.0130 gmo 22.4 tgm 5.15 R d 5.89 Rg 0.678

R s 3.78 R i 17.0 Rds 1127 Lg 12.8

Cds 0.031 CGS 0.0011

Wr=100A

0.248 0.0079 21.8 5.49 1.54 0.678 3.78 5.57 705 13.2 0.028 0.0011

Average

0.21 0,0107 21.9 5.31 3.39 0.678 3.85 10.7 875 8.65 0.029 0.0011

Average

0,213 0.0105 22.1 5.32 3.72 0.678 3.78 11.3 916 13.0 0.0295 0.0011

pF pF mS ps ohm ohm ohm ohm ohm pH pF pF

Table 1: Equivalent circuit elements for two FETs with differing recess depths, and the two electrical mean FETs derived from these two FETs.

FET with S-param Element Eq. circuit

Wr=300A Average Average Fit

Cgc Cgd gmo tgm R~ Rg

Rs Ri Rds Lg

Cds CGS

0.200 0.0107 22.1 4.75 4.49 0.678 3.78 8.39 863 13.0 0.0299 0.0011

+5%

-1% +12% -25%

+2% +28% +1% -33% -3%

+7% -2%

+12% -17%

+35% +6%

-1%

0.199 0.0107 22.0 4.74 4.15 0.678 3.76 8.49 862 13.4 0.0298 0.0011

values for each technolog- ical parameter then define the technological mean "Average FET'.

ELECTRICAL MEAN Two methods are com- monly used in the GaAs industry to find an "Average FET" for circuit design. The first method is to find the average val- ues for each of the eight measures S-parameters (magnitude of $11, phase of $11... phase of $22 ) from the measured S-parame- ters of many FETs. An equivalent circuit may then be fitted to these averaged S-parameters. The second method is to fit equivalent circuits to each measured FET and then average the values for each equivalent circuit component (Cg c, Cg d and so on).

S-parameter averaging and equivalent circuit averaging give rise to "electrically-mean" devices, which are differ- ent from each other and different from the techno- logical mean that they are intended to represent.

COMPARE THE AVERAGE Using GaAsCode's FET forward modelling pro- gram (FETBase) and reverse modelling pro- gram (FETLink), the tech- nological mean "Average FET" can be compared with the two "electrical means". (The two pro- grams were described briefly in the April 1989 issue of Euro III-Vs Review. A simplified form of the physical FET model used is given in Ref. 1).

For this example, con- sider a hypothetical pro- cess which has very tight control over all process steps apart from the gate recess etch. The recess etching step yields a mean recess depth of

Table 2: Equivalent circuit elements and percentage errors for FETs considered in the text example.

¢1 F E A T U R E

L9

0

RcJ

CG$

II

< . i

I Cgd Rd

I

Ccjc

g r , ~ o

t g ~

R o

> Cds

i

l O

Figure 1: Equivaient circuit topology used for the example in the text.

, i i i

~.'.~

FaEa.E.CV ~.~

Figure 2a: St1 and $12 [br four FETs discussed in the text: technological mean FET (no symbols), 100ft and 500A recess-depth FETs (crosses and rectangle symbols) and element-averaged FET (diamond symbols).

300J~, but the recess dep th may vary between IOOA and 500A.

Using typical material and structural parameters for a 0.5~tm gate-length FET (for example, active layer thickness = O. 17~tm, doping density = 1.78 x 1023 m -3) the equ iva l en t

circuit e lements calculat- ed by FETBase for two devices with gate recess depths of 1OOA and 50OA, are shown in the first two columns of Table 1. The equivalent circuit topolo- gy is shown in Figure 1. CGS is the geometr ic gate- source capacitance arising

from the metal pads and gate strips, and is constant t h ro u g h o u t this example.

The electrical means can be calculated f rom these two devices. This corresponds to the practi- cal si tuation where a sam- ple of fabricated devices is selected from which the

J'l

Page 1 7 . "volume 3 • Number 6

i 11

average device is found (only two FETs in this illustrative example).

The S-parameter mean is found by calculating the S-parameters over a range of frequencies f rom the two equivalent cir- cuits. The S-parameters are then averaged at each f requency point, and the equivalent circuit is fitted to these averaged S- parameters for equivalent circuit e lements arising from the averaged S- parameters. See co lumn 3 of Table 1.

The equivalent circuit e lement averaging method , using the data of co lumns 1 and 2, results in the circuit e lements shown in co lumn 4 of Table 1. As can be seen, the two electrical means are different.

In contrast, the equiva- lent circuit calculated for the technological mean device, havin~g a recess depth of 300A, is shown in co lu m n 1 of Table 2. The percentage difference between these values and the electrical mean values are shown in co lumns 2 and 3 of Table 2 for the '%- parameter averaged" and "equivalent circuit ele- men t" averaged cases respectively. Blanks in the Table correspond to dis- crepancies of less than one percent. If ei ther elec- trical mean averaging m e th o d were valid, its resulting equivalent cir- cuit would be the same as the technological mean equivalent circuit.

The r ightmost Co lumn of Table 2 contains values for the equivalent circuit fitted by FETI,ink to the S- parameters of the techno- logical mean device. These S-parameters were calculated from the tech- nological mean device's equivalent circuit, shown in the first co lumn of Table 2. The close agree- men t between the two cir- cuits indicates that

i ,

FE A T UR E !

a . o

!io 1 . 0

o . a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

o , 4 . . . . . . . . . . . . . .

i . a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

o . c

Figure 2b: $21 and $22 for four FETs discussed in the text: technological mean FET (no symbols), IOOA and 500A recess-depth FETs (crosses aJ~d rectangle symbols) and element-averaged FET (diamond symbols).

FETLink introduces no significant errors into these calculations: the fit- ting routine is near enough exact. (The maxi- mum difference between the fitted phase and the phase of the input data is within 0.25 ° at any point across the full frequency range: between fitted and input magnitudes the dif- ference is less than 6x10 -4. The files of S-parameters input to the computer routines have magnitudes specified to three decimal places and phases round- ed to 0.1°).

The failure of the S- parameter averaging method is evident from the S-parameter plots in Figure 2. If S-parameter averaging were a valid procedure, the curves cor- responding to the techno- logical mean FET (curves without symbols) would lie midway between the 100A and 500A curves (curves with crosses and rectangle symbols respec- tively). The errors intro- duced by equivalent cir- cuit element averaging can also be seen by corn-

paring the element aver- aging curves (curves with diamond symbols) with those of the technological mean (curves without symbols).

CIRCUIT DESIGN CONSEQUENCES Attempting a circuit design based on an elec- trical mean FET, rather than the technological mean, may result in an MIC or MMIC design wholly inappropriate to the particular process.

In the example, the largest discrepancies between the technologi- cal mean and the electri- cal averages occur for R i, ~gm, Rd, Cgc and Lo. Errors in the first two of~these elements may markedly affect the likely power performance of large sig- nal circuits.

The often extreme changes in overall circuit S- parameters, arising from the use of different mean FETs with apparently small differences in S-parameters, can readily be investigated with a circuit simulator.

In the simple example given previously, some of the important FET ele- ments (for example, the intrinsic transconduc- tance) are almost the same for all three means. This is an artefact of the simple example in which only one technological parameter was varied; the transconductance is pri- marily a function of the active layer doping densi- ty, which was kept fixed. In general, for practical processes where all pro- cessing steps have inher- ent spreads, it cannot be inferred that the techno- logically-derived mean value for any component will be the same as either electrical mean value.

Processes tend to pro- duce devices which are physically near the tech- nological mean, that is, the technological mean "Average FET" represents the most likely outcome from a given FET fabrica- tion. As shown above, this "Average FET" is not the same as any electrical mean device.

To obtain reasonable

circuit yields, the circuit must be designed around the technological mean. The set of circuit elements comprising an electrical mean may only result from a combination of technological parameters that is statistically unlike- ly given the spreads in a particular process, or may even by physically impos- sible to realise in a single FET. Almost nothing can be done at the technologi- cal level which will change just a single equiv- alent circuit element or S- parameter component. Foundry operators have a primary responsibility to provide users with an "Average FET" which is likely to lead to reason- able circuit yields.

Once the technological mean device parameters have been ascertained, the effects of any process or bias changes can readi- ly be investigated using a physically-based FET model. With an electrical mean device, no such pre- dictions are possible. The effort of electrical mean FET averaging must be repeated for each process or bias change, with all the limitations of this procedure discussed in this article. •

Adrian Hill, John Bridge and Peter Ladbrooke

GaAsCode Ltd., St. John's Innovation Centre, Cowley Road,

Cambridge, CB4 4 W S .

REFERENCE 1. Ladbrooke, PH, "MMIC Design: GaAs FETs and HEMTs', Artech House, 1989.