AFullyMonolithic2.5GHzLCVoltageControlledOscillatorin0.35mCMOSTechnologybyRyan Lee BunchThesissubmittedtotheFacultyoftheVirginiaPolytechnicInstituteandStateUniversityinpartialfulllmentoftherequirementsforthedegreeofMASTEROFSCIENCEinElectricalEngineeringSanjayRaman,ChairCharlesW.BostianPeterM.AthanasApril26,2001Blacksburg,VirginiaKeywords: Oscillator,RFIC,integratedcircuit,nonlinear,inductor,VCO,CMOS,resonatorCopyright2001,RyanLeeBunchAFullyMonolithic2.5GHzLCVoltageControlledOscillatorin0.35mCMOSTechnologybyRyanLeeBunchCommitteeChairman:Dr. SanjayRamanBradleyDepartmentofElectricalandComputerEngineering(ABSTRACT)Theexplosivegrowthinwireless communications has ledtoanincreaseddemandforwirelessproductsthatarecheaper,smaller,andlowerpower. RecentlytherehasbeenanincreasedinterestinusingCMOS, atraditional digital andlowfrequencyanalog IC technology, to implement RF components such as mixers, voltage controlledoscillators(VCOs),andlownoiseampliers(LNAs). Futuremass-marketRFlinks,suchas BlueTooth, will require the potentiallylow-cost single-chipsolutions thatCMOS can provide. In order for such single-chip solutions to be realized, RF circuitsmust bedesignedthat canoperateinthepresenceof noisydigital circuitry. Thevoltagecontrolledoscillator(VCO), animportantbuildingblockforRFsystems, isparticularly sensitive when exposed to an electrically noisy environment. In addition,CMOSimplementationsof VCOshavebeenhamperedbythelackof high-qualityintegratedinductors.Thisthesisfocusesonthedesign ofafullyintegrated 2.5GHzLCCMOS VCO.Thecircuit is intendedas avehiclefor futuremixedRF/digital noisecharacterization.The circuit was implemented in a 0.35 m single poly, 4 metal, 3.3 V, CMOS processavailable through MOSIS. The oscillator uses a complementary negative transconduc-tancetopology. Thisoscillatorcircuitisanalyzedasanegative-resistanceoscillator.Monolithicinductorsaredesignedusingfull-waveelectromagneticeldsolversoft-ware. The design of an inversion-mode MOS (I-MOS) tuning varactor is presented,alongwithadiscussionoftheeectsofvaractornonlinearityonVCOperformance.I-MOSvaractorsareshowntohavesubstantiallyimprovedtuningrange(andtun-ingcurvelinearity)overconventionalMOSvaractors. PracticalissuespertainingtoCMOSVCOcircuitdesign, layout, andtestingarealsodiscussed. Thecharacter-izationof theVCOandtheintegratedpassivesispresented. TheVCOachievesabest-casephasenoiseof-106.7dBc/Hzat100kHzosetfromacenterfrequencyof2.73GHz. Thetuningrangeis425MHz(17%). Thecircuitconsumes9mAfroma3.3Vsupply. ThisrepresentsexcellentperformanceforCMOSoscillatordesignsreportedat this frequency. Finally, several recommendations for improvements inoscillatorperformanceandcharacterizationarediscussed.ThisworkwassupportedbytheNationalScienceFoundationundera00PECASEaward.iiiACKNOWLEDGEMENTSIwouldliketothankmyadvisor,Dr. SanjayRamanforgivingmetheopportunitytoconduct this research. His commitment toimprovingthe RFMicroelectronicsprogramatVirginiaTechwasinstrumentalinprovidingmetheresourcesneededtocompletethisresearch.IwouldliketothankDr. CharlesBostianandDr. PeterAthanasforservingonmyadvisorycommittee.IwouldalsoliketothankDr. WarrenStutzmanandtheAntennaGroupforgivingmeaccesstotheSonnetEMsoftwarewhichwasinstrumentalinthedesignprocess.I would like to thank George Studtmann and the people at M/A-COM in Roanoke fortheirdonationofHPworkstationsandfortheirhelpinprovidingcarriersubstratesfordieprobingandforpackagingsomeofthedie.I wouldliketothanktheECpEsystemadministratorJohnHarrisforall hishelpwithmymanycomputerandnetworkingproblems.It has been a pleasure working with the Graduate Research Assistants in the WirelessMicrosystems Lab. They provided both laughter and technical assistance, and helpedmakethecountlesshoursspentinthelabpassquickly.I would like to thank my family. My parents, Thomas and Carolyn Bunch, encouragedme to go to graduate school in the rst place. Without their love and support I wouldivnever have made it this far. My brother and sister in law, Tommy and Renee Bunch,providedmeahomeawayfromhomeinPulaski. Without their encouragement Iwouldnothavenishedgraduateschool.MostofallIwouldliketothanktheGoodLord,withhimallthingsarepossible.vTABLEOFCONTENTS1 Introduction 11.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 RecentworkonLCCMOSVCOs. . . . . . . . . . . . . . . . . . . . 41.3 OverviewofThesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 GMOscillatorTheory 82.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.2 GMOscillatorTopologies. . . . . . . . . . . . . . . . . . . . . . . . 102.3 AnalysisofTheComplementary GMOscillator . . . . . . . . . . . 182.4 FrequencyLimitationsof GMOscillators . . . . . . . . . . . . . . . 202.5 AdvantagesandDisadvantagesoftheComplementary GMOscillator 242.6 OscillatorPhaseNoise . . . . . . . . . . . . . . . . . . . . . . . . . . 263 InductorDesign 313.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.2 InductorGeometries . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.3 Lossesinspiralinductors. . . . . . . . . . . . . . . . . . . . . . . . . 353.4 InductorCircuitModels . . . . . . . . . . . . . . . . . . . . . . . . . 383.5 InductorSimulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423.6 Finalinductordesign . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 VaractorDesign 53vi4.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534.2 MOSvaractorstructures . . . . . . . . . . . . . . . . . . . . . . . . . 554.3 VaractorDesignandLayout . . . . . . . . . . . . . . . . . . . . . . . 594.4 Large-SignalEects. . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 OscillatorDesignandImplementation 735.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735.2 OscillatorDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745.3 OscillatorSimulations . . . . . . . . . . . . . . . . . . . . . . . . . . 815.4 TestChipLayout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 MeasuredResults 966.1 OnePortTestStructureMeasurements . . . . . . . . . . . . . . . . . 986.2 InductorMeasurement . . . . . . . . . . . . . . . . . . . . . . . . . . 1006.3 VaractorMeasurements . . . . . . . . . . . . . . . . . . . . . . . . . . 1026.4 NegativeResistanceCircuitMeasurements . . . . . . . . . . . . . . . 1056.5 OscillatorMeasurements . . . . . . . . . . . . . . . . . . . . . . . . . 1087 ConclusionsandFutureWork 1217.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217.2 FutureWork. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124ADerivationofNegativeResistanceofCrossCoupledFETs 130A.1 LowFrequencyModel . . . . . . . . . . . . . . . . . . . . . . . . . . 130A.2 HighFrequencyModel . . . . . . . . . . . . . . . . . . . . . . . . . . 132BSolutionofNonlinearDierentialOscillatorEquation 134CTSMC0.35m1P4MDeviceParametersExtractedbyMOSIS 139C.1 January2000MOSISParameters . . . . . . . . . . . . . . . . . . . . 139C.2 August2000MOSISparameters . . . . . . . . . . . . . . . . . . . . . 142viiLISTOFFIGURES1.1 NMOSftandfmaxversusfeaturesize[1]. . . . . . . . . . . . . . . . 32.1 FeedbackOscillatorModels . . . . . . . . . . . . . . . . . . . . . . . 92.2 SimpleNMOS GMoscillator. . . . . . . . . . . . . . . . . . . . . . 112.3 CrosscoupledNFETsandDCequivalentcircuit. (a)CrosscoupledNFETs. (b)SmallsignalmodelofcrosscoupledNFETs. . . . . . . . 122.4 PMOSandNMOS GMOscillators . . . . . . . . . . . . . . . . . . . 132.5 CMOS GMOscillator. . . . . . . . . . . . . . . . . . . . . . . . . . 142.6 Crosscoupledinverters . . . . . . . . . . . . . . . . . . . . . . . . . . 152.7 Inverterbiaspoint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.8 Piercecrystaloscillator. . . . . . . . . . . . . . . . . . . . . . . . . . 172.9 Thecomplementary GMoscillatorasaPierceoscillator. . . . . . . . 172.10 De-embeddednonlinearity. (a)Testcircuit. (b)I-Vcharacteristic. . . 182.11 Idealnonlinearoscillatorcircuit . . . . . . . . . . . . . . . . . . . . . 192.12 Cgdinparallelwithtankcircuit. . . . . . . . . . . . . . . . . . . . . . 212.13 Tankcircuitwithparasiticcapacitanceinparallel . . . . . . . . . . . 212.14 HighfrequencyMOSFETmodel. . . . . . . . . . . . . . . . . . . . . 232.15 AmplitudelimitingofNMOSandCMOSoscillators. (a)NMOSonlyoscillator. (b)Complementaryoscillator. (c)NMOSonlywaveforms.(d)Complementarywaveforms. . . . . . . . . . . . . . . . . . . . . . 252.16 Idealoscillatoroutputspectrum. . . . . . . . . . . . . . . . . . . . . 262.17 Phasenoiseinoscillatoroutputspectrum. . . . . . . . . . . . . . . . 272.18 Typicaloscillatorphasenoisespectrum. . . . . . . . . . . . . . . . . 28viii3.1 Spiralinductorgeometries . . . . . . . . . . . . . . . . . . . . . . . . 333.2 ParametersforEquation3.2.. . . . . . . . . . . . . . . . . . . . . . . 343.3 Electriceld(capacitive)losses. . . . . . . . . . . . . . . . . . . . . . 363.4 Magneticeld(inductive)losses. . . . . . . . . . . . . . . . . . . . . . 373.5 Eddycurrentsinthespiralwindings[2]. . . . . . . . . . . . . . . . . 383.6 Spiralinductorlumpedcircuitmodel. . . . . . . . . . . . . . . . . . . 393.7 equivalentcircuitforatwo-portnetwork.. . . . . . . . . . . . . . . 403.8 Twomethodsofreducing-network. . . . . . . . . . . . . . . . . . . 403.9 SimpleparallelRLinductormodel. . . . . . . . . . . . . . . . . . . . 443.10 CMOSprocesslayerstack-up. . . . . . . . . . . . . . . . . . . . . . . 453.11 SimpliedlayerdataforSonnetEMsimulations.. . . . . . . . . . . . 463.12 Designvariablesforsquarespiralinductor. . . . . . . . . . . . . . . . 473.13 Inductance (single-ended) versus frequency for a variety of dimensions(inm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483.14 Qualityfactor(single-ended)versusfrequencyforavarietyofdimen-sions(inm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483.15 Reqversusfrequencyforavarietyofdimensions(inm). . . . . . . . 493.16 Seriesconnectedtankcircuitinductoranddimensions. . . . . . . . . 503.17 Dualinductorqualityfactor(dierential)versusfrequency. . . . . . . 513.18 Dualinductorinductance(dierential)versusfrequency. . . . . . . . 513.19 DualinductorReqversusfrequency. . . . . . . . . . . . . . . . . . . . 524.1 PNjunctionvaractor . . . . . . . . . . . . . . . . . . . . . . . . . . . 544.2 MOScapacitorstructures . . . . . . . . . . . . . . . . . . . . . . . . 564.3 Seriesvaractorconnection . . . . . . . . . . . . . . . . . . . . . . . . 594.4 Varactorimplementationschematic. . . . . . . . . . . . . . . . . . . . 624.5 Varactorlayoutwithdetailedviewof gateandcontactarrangement.Contactsareshownassolidblacksquaresinthevariousregions. . . . 634.6 Circuitusedtomeasuretotaltankcircuitvaractorcapacitanceversustuningvoltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64ix4.7 Simulatedtotaltankcircuitvaractorcapacitanceversustuningvoltage 654.8 Varactortuningcharacteristic . . . . . . . . . . . . . . . . . . . . . . 674.9 VaractorC-Vtestcircuit . . . . . . . . . . . . . . . . . . . . . . . . . 674.10 Timedomaineectofnonlinearcapacitance . . . . . . . . . . . . . . 694.11 CAV Gvs. tuningvoltageforvariousamplitudes. . . . . . . . . . . . . 704.12 SimulatedMOScapacitorVCOtuningcurves . . . . . . . . . . . . . 725.1 StartingpointoftheVCOdesign. . . . . . . . . . . . . . . . . . . . . 755.2 Oscillatorwithtailcurrentcontrolanddevicesizes. . . . . . . . . . . 765.3 Varactormodel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775.4 CompleteunbueredVCOdesign(Oscillator#1). . . . . . . . . . . . 785.5 CompletebueredVCOdesign(Oscillator#2). . . . . . . . . . . . . 795.6 Completere-tunedVCOdesign(oscillator#3). . . . . . . . . . . . . 805.7 Simulatedoscillatorcircuit . . . . . . . . . . . . . . . . . . . . . . . . 825.8 Simulatedoscillatoroutputvoltages. . . . . . . . . . . . . . . . . . . 845.9 Simulatedoscillator tuningcharacteristic. Tuningrange: 590MHz(23%). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855.10 Probepadstructure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885.11 UnbueredOscillator(VCO#1). . . . . . . . . . . . . . . . . . . . . 895.12 Layoutof1 kresistor. . . . . . . . . . . . . . . . . . . . . . . . . . . 905.13 Inductorteststructure. . . . . . . . . . . . . . . . . . . . . . . . . . . 915.14 Varactorteststructure.. . . . . . . . . . . . . . . . . . . . . . . . . . 925.15 Activecircuitteststructure. . . . . . . . . . . . . . . . . . . . . . . . 935.16 Opencircuitbondpadteststructure. . . . . . . . . . . . . . . . . . . 935.17 Shortcircuitbondpadteststructure. . . . . . . . . . . . . . . . . . . 945.18 Completetestchip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956.1 FabricatedCMOStestchip. . . . . . . . . . . . . . . . . . . . . . . . 976.2 Carriersubstratewithprobescontactingthetestchip. . . . . . . . . 986.3 Dierentialsingleporttestsetup. . . . . . . . . . . . . . . . . . . . . 99x6.4 Bondpadsasashuntelement. . . . . . . . . . . . . . . . . . . . . . . 1006.5 Measureddierentialtankinductorinputimpedance. . . . . . . . . . 1016.6 Measureddierentialtankinductorqualityfactor. . . . . . . . . . . . 1016.7 Measureddierentialtankinductorinductance. . . . . . . . . . . . . 1026.8 Varactortestsetup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036.9 Measuredvaractorsmallsignalcapacitanceversustuningvoltage. . . 1046.10 De-embeddedvaractorQversusfrequency,VTUNE= 3.3 V ,Vg= 1.65. 1056.11 Negativeresistancemeasurementconguration. . . . . . . . . . . . . 1066.12 CircuitforEquation6.4. . . . . . . . . . . . . . . . . . . . . . . . . . 1086.13 I-Vcharacteristicmeasurementmethod. . . . . . . . . . . . . . . . . 1096.14 MeasuredI-Vcharacteristicofthenegativeresistancecircuit.. . . . . 1106.15 FabricatedCMOSVCOwithprobesincontact . . . . . . . . . . . . 1116.16 SidebandscreatedbylocalAMradiostations . . . . . . . . . . . . . 1126.17 100kHzsidebandscreatedbyrefreshrateofnearbycomputermonitor.1136.18 Single-endedoscillatormeasurementsetup. . . . . . . . . . . . . . . . 1136.19 OutputspectrumofVCOwhenbiasedwithbatteries . . . . . . . . . 1146.20 MeasuredunbueredVCO(VCO#1)tuningcurve. . . . . . . . . . . 1156.21 MeasuredretunedVCO(VCO#3)tuningcurve. . . . . . . . . . . . 1156.22 Unbuered(VCO#1)VCOphasenoiseversusfrequency. VTUNE=0 V . IBIAS= 10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186.23 Measuredphasenoiseversustuningvoltageforunbuered(VCO#1)VCO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196.24 Measuredsingle-endedoutput power of unbuered(VCO#1) VCOversustuningvoltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1207.1 PhasenoisemeasurementusingthePLLmethod. . . . . . . . . . . . 1257.2 Phasenoisemeasurementusingthedelaylinemethod. . . . . . . . . 1257.3 RFnegativeresistancemeasurementusingacirculator. . . . . . . . . 128A.1 CrosscoupledNFETsandDCequivalentcircuit. . . . . . . . . . . . 130xiA.2 Redrawncircuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131A.3 TestSource . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131A.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131A.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132B.1 TestcircuitandextractedI-Vcurve. . . . . . . . . . . . . . . . . . . 135B.2 RLCmodelof GMoscillator.. . . . . . . . . . . . . . . . . . . . . . 136B.3 Equivalentparallelresistanceversusoscillationamplitude. . . . . . . 138xiiLISTOFTABLES1.1 RecentlyreportedfullymonolithicLCCMOSVCOs. . . . . . . . . . 64.1 Sheetandcontactresistancesfora0.35mprocess . . . . . . . . . . 656.1 Negativeresistancefor27 resistor. . . . . . . . . . . . . . . . . . . 1076.2 Negativeresistancefor47 resistor. . . . . . . . . . . . . . . . . . . 1077.1 Comparison of this work and reported fully monolithic LC CMOS VCOs.123xiiiChapter1Introduction1.1 BackgroundTheexplosivegrowthinwireless communications has ledtoanincreaseddemandforwirelessproductsthatarecheaper,smaller,andrequirelowerpower. Unlikethecomputer industry, whereperformancehas nearlydoubledannuallysincethemid1960s1, improvementsinRFandanalogcircuitshavebeenmuchslower. Amajorreason for the rapid advancement of digital performance has been that improvementsindevicetechnologyspecicallytheeverdecreasingminimumfeaturesizeofCom-plementary Metal-Oxide-Semiconductor (CMOS) technologyhas translated directlyintoperformancegains. Ontheotherhand, radiofrequency(RF)componentshavetypically been fabricated in technologies such as Gallium Arsenide (GaAs) and SiliconBipolar, which yield better RF performance. These traditional RF processes have notbeneted from improvements in device technology as quickly as their digital brethren.RecentlytherehasbeenanincreasedinterestinusingCMOS, atraditional digital1TheoftenquotedMooreslawpostulatesthatdigitaldevicetechnologyshouldapproximatelydouble in density and speed every 18 months.1andlowfrequencyanalogICtechnology,toimplementRFcomponentssuchasmix-ers,voltagecontroloscillators(VCOs),andlownoiseampliers(LNAs)[3],[4]. Thereasoningbehindthisresearchmovementisobviousdigital CMOScircuitscanbefabricated in extremely high volume on eight or twelve inch wafers at a relatively lowcost per die. If suitable RF performance can be achieved in CMOS then wireless prod-ucts could benet from the same economy of scale that has propelled the PC industryfrom20MHz80386processorsto1.5GHzPentiumsduringthelast10years2. Thepotential forhigherlevelsofintegrationinCMOSistremendous. Ifdigital andRFfunctionality can be combined on a single CMOS die, then the total cost of designingawirelessproductcouldalsobereduced.CMOShasnotbeenaverygoodtechnologyforRFdesignsforanumberofreasons[5]. Whileonecouldarguethatsub-micronPMOSandNMOSdevicesthemselveshavereasonableRFcharacteristics (highftandfmax, Fig. 1.1), thelowresistiv-itysiliconsubstratesusedinCMOScreateanumberof problemsfor RFcircuits.RecentgenerationsofCMOStechnologyhaveutilizedathinlayerofepitaxial,highresistivitysiliconfortheactivelayer, grownonthicklowresistivitybulkwaferstopreventlatch-up3. Thislowresistivitysubstratemakesitdiculttoisolateportionsofthecircuitfromeachother. Lowresistivitysubstratesalsocompromisethequal-ityof integratedpassives, particularlyintegratedinductors. Thep+substrateof atypical digital CMOSprocess mayhavearesistivityas lowas 0.01 cm. Theselossysubstratescombinedwithlowqualityaluminuminterconnectshavelimitedthequalityfactor(Q)of inductorsonsilicontolessthan5. Thebulkconductivityofaluminumisapproximately3.54 107S/mwhichisfairlyhigh; howeverwhenalu-2ItisthebeliefoftheauthorthatMooreslawisaself-fulllingprophecy. Fiercecompetitionandconsumerdemandhasforcedcompaniestosinkbillionsofdollarsintodigital semiconductorresearch, which has resulted in consistent improvements in the technology. Had a similar amount ofresearch energy been devoted to an alternate technology it is likely that a similar gains would havebeen realized.3Latch-up is a device failure that may occur in CMOS circuits when short pulses turn on a par-asitic silicon controlled rectier that exists across the substrate between devices. This phenomenonis discussed in [6].2Figure 1.1: NMOSft andfmax versus feature size [1].minumisdepositedasathinlmitsconductivityismuchlowerthanthis. Copperandgoldmetalizationsdonotsuerfromlargedeviationsbetweentheirbulkandthinlmconductivities. ThetradeosbetweenCMOS, SiliconBipolar, GaAs, andothertechnologiesforRFICapplicationsarediscussedatlengthin[5].While the on-chip passive elements are likely to improve with lower resistivity copperinterconnects,andhighresistivitysubstratesmaybeutilizedifcircuitsarecarefullylaidouttopreventlatch-up, isolationwill likelyremainanimportantissue. IfhighdensitydigitalVLSIandRFcircuitsaretocoexistinthesameICenvironmentthentheRFcircuitswill havetotoleratenoisegeneratedbythedigital circuitry. Thisdigital noiseis typicallylargesincethedigital circuitrywill havelargeamplitudeswings (rail to rail in most logic circuits). It will most likely be strongest at harmonics(nfclk)andsub-harmonics(fclkn)ofthedigital clockfrequencies. Muchofthisnoisearisesfromthecurrentsthatarenecessarytochargetheinputcapacitancesof thevariousCMOSlogicgates.One circuit that may be noticeably degraded by the presence of digital switching noiseisthevoltagecontrolledoscillator(VCO). VCOsarecritical componentsforsignal3generationandfrequencyselection(i.e. thelocal oscillator)inRFtransceivers. Inaddition,lowjitterVCOsareimportantforthegenerationofclocksignalsindigitalsystems(Jitterisessential thetimedomainexpressionof phasenoise.). VCOsareverysensitivetonoisebecausetheyarefreerunning, autonomous, systems4. Anynoise coupled into the oscillator circuit can be amplitude or frequency modulated andappear onthenoiseskirts of theoscillator, compromisingits spectral purity. ForthisreasontheVCOisanexcellentcircuittouseasatestvehicleforinvestigatingtheeectsofnoisecouplinginmixeddigital/RFcircuits. Theinvestigationofthesemixed-signal noise coupling issues was a primary motivation behind the design of theVCOpresentedinthis thesis. However, thedesignof aCMOSoscillator withanintegrated tank circuit is a signicant eort unto itself, and it is to that goal that thisthesiswillbedirected.1.2 RecentworkonLCCMOSVCOsInthissectionabriefoverviewofrecentlyreportedCMOSVCOswillbepresented.Manyofthedesignissuesandmethodspresentedintheseworkswillbediscussedindetailinlaterchapters.AnumberofLCCMOSVCOshavebeenreportedrecentlyintheliterature. Cran-inckxandSteyaert presentedaverycomplete treatment of VCOs basedonbothplanarspiral inductorsandbondwireinductorsin[7]. ThisworkalsoutilizedLee-sons equation[8] topredict the phase noise of these oscillators. In[9], Lee andHajimiri presented a comprehensive analysis of the phase noise of oscillators, which isapplicable to both ring and LC oscillators. Their phase noise model is the rst modeltocorrectlyaccountforthetime-variantnatureof oscillatorcircuits. Theydrawanumber of interestingconclusions that mayhelpdesigners reduceicker (1f) noise4Even when frequency or phase locked in a control loop, noise in the loop will still modulate theVCO output4upconversionthatisproblematicinCMOSVCOs. VoraandLarsonpresenteda2GHz VCO in [10], analyzing their design using both the linear methods of Leeson andthelineartime-variantmethodofHajimiriandLee. Herzeletal,presentedaCMOSVCO using MOS5varactor tuning and predicted its phase noise using linear methods[11]. Andreani andMattissonpresenteda2.4GHzVCOusingMOSvaractors in[12]aswellasadetailedanalysisoftheMOSvaractorqualityfactor. AndreanialsopresentsacomparisonofVCOtuningwithMOSvaractorsandjunctionvaractorsin[13].Table1.1summarizestheperformanceofvariousmonolithicLCCMOSVCOsthathavebeenrecentlyreported. Thegureof merit(FOM)inthistableresultsfromnormalizingthecenterfrequency,phasenoiseoset,andpowerconsumptionsothateachVCOcanbeobjectivelycompared. ThisFOMisdenedin[19]as:V COFOM= L(foffset) 20 log_foscfoffset_+ 10 log_Pdiss1 mW_, (1.1)where, L(foffset) is the phase noise at oset, foffset with a center frequency of fosc andan oscillator power consumption of Pdiss. The units of this FOM are the same as phasenoise: dBc/Hz. Lower (more negative) gures of merit represent better oscillator noiseperformance. ThisFOMdoesoverlooksomeotheroscillatorparameterswhichareimportantsuchasoutputpower, tuningrange, anddiearea. However, sincetheseparameters are not always reported in the literature it is dicult to present a completecomparison.1.3 OverviewofThesisThis thesis follows inchronological order the design, implementation, andnallytesting of the LC CMOS VCO circuit that is the focus of this work. Chapter 2 presents5MOSvaractorsareaCMOSalternativetopnjunctiondiodevaractorsthathavebeentradi-tionally used. Varactors will be discussed in Chapter 4.5Table1.1:RecentlyreportedfullymonolithicLCCMOSVCOs.ReferenceTech.foPhaseNoiseTuningRangepowerVoltageFOM(m)(GHz)(dBc/Hz)(MHz)(mW)(V)(dBc/Hz)Hajimiri[14]0.251.8-121@600kHz?61.5-182.8Craninckx[2]0.71.8-116@600kHz25061.5-177.8Vora[10]0.62-103@100kHz?22?-175.6Park[15]0.50.9-110@200kHz1266.63.3-174.9Herzel[11]0.251.9-100@100kHz250152.5-173.8Andreani[12]0.82.4-118@1MHz35022.52.5-172.1Razavi[16]0.61.8-100@500kHz1207.593.3-162.3Wong[17]0.352-87@100kHz?22.53-159.5Lam[18]0.352.6-110@5MHz320132.5-153.26athoroughanalysis of theCMOS GMoscillator. Chapter 3exploresthedesignof spiral inductors onalossyCMOSsubstrate. Chapter 4brieysurveys varioustopologies for varactors in CMOS and presents the design of a PMOS inversion modevaractor. Chapter5presentsthenalVCOdesignanditsimplementationina0.35msingle-poly, 4-metal, digital CMOSprocess. Chapter 6presents measurementresults for thefabricatedVCO. Chapter 7concludes thethesis bycomparingtheresultsofthisprojectwithotherfullyintegratedVCOsandsuggestinganumberofideasforfuturework.7Chapter2GMOscillatorTheoryInthischapterthetheoryofoperationofCMOSnegativetransconductance(GM)oscillatorswill bepresented. Thematerial presentedhereprovidesthebackgroundthatisnecessarytounderstandthetankcircuitandoscillatordesignsthatarepre-sentedinthefollowingchapters. Various GMtopologies arepresented, andthecomplementary GMtopology used in this thesis is discussed in detail. The comple-mentary GMoscillatoristreatedasbothananalogandadigitalcircuitprovidingauniquedesignperspective. Limitationsofthistopologyandthecalculationofitsphasenoiseisalsodiscussed.2.1 BackgroundAll LC oscillators can be represented as a simple feedback network as shown in Figure2.1(a). TheconditionsforoscillationtooccurareknownastheBarkhausencriteria.Theseconditionsrequirethatthegainaroundthefeedbackloopequalunityandthetotal phaseshiftaroundtheloopequal zeroorsomemultipleof 360. Whentheseconditionsaresatised,asignalattheinputofthegainstagewillbeampliedand8+G(s)H(s)VOUT(a)+GM(b)Figure 2.1: Feedback Oscillator Models. (a) Feedback Loop. (b) Transconductor.returned back to the input in phase resulting in a self-sustaining signal. This feedbackloopviewpointisveryuseful fortheanalysisofLCoscillatorsandhasbeenwidelyused to predict their behavior. This approach has been especially useful in describingtheoperationof traditional oscillators(basedonsingleactivedevices)suchastheColpitts,Hartley,andPierceoscillators.Analternate waytodescribe the operationof oscillators involves the concept ofnegativeresistance. Figure2.1(b)showsamodelofasimplenegativeresistanceLCoscillator. In this gure the active device is a simple transconductance (GM) amplierconnected in positive feedback to an LC tank circuit. It is straightforward to show thatthe tank circuit sees a negative resistance of -1GMlooking back into the transconductoroutput. Itcanbeshownthatif theBarkhausencriteriaaresatisedthisnegativeresistance will exactly cancel the equivalent parallel resistance of the tank circuit [20].This makes sense because the active device must add enough energy to the circuit tocancel the total losses of the tank circuitotherwise the circuit would simply behaveasanunderdampedsystem. Negativeresistanceoscillatorshavethepropertythattheycontinuetogenerateanegativeresistancewhenthetankcircuit is removed.Ontheotherhand, removingthetankcircuitfromafeedbackoscillatorbreaksthefeedback loop that creates the negative resistance and a negative resistance cannot be9measured [20]. Although both representations are equivalent,the negative resistanceviewpointwillbeutilizedfortheoscillatoranalysesofthisthesis.ItispossibletoimplementanoscillatorinCMOStechnologyusingsingleactivede-vicesintraditionaltopologiessuchastheHartleyorColpitts. Howevermostrecentimplementations of CMOS LC oscillators have utilized a dierential topology. Dier-ential topologies are advantageous in integrated circuits, since they are less susceptibletosupplynoisethatisoftenpresentinon-chippowerrails. Furthermore,manyinte-gratedRFsystemswouldbenetfromtheuseofadierential local oscillator(LO)sincetypicalintegratedmixersaredoubly-balancedGilbertCelltopologies. Inthesecase,theuseofadierentialoscillatoreliminatestheneedforsingle-endedtodier-ential conversion circuitry. The most popular dierential oscillator topologies are theGMoscillators, which utilize two cross-coupled transconductors (FETs) to produceanegativeresistancesimilartothetransconductorofFigure2.1(b).2.2 GMOscillatorTopologiesIn order to understand the operation of the complementary GMoscillator presentedinthisthesis,itishelpfultorstexamineitsNMOS-onlyandPMOS-onlycounter-parts. Figure2.2showsasimpleNMOS GMoscillatortopology. TheDCanalysisof this circuit is simple since the inductors may be replaced by short circuits. The DCbiaspointisdenedbyVGS=VDDandVDS=VDD. AssumingtheNMOSdevicestobelongchannel FETs (for conceptual purposes only, short channel devices areactuallyusedinthenal design), andneglectingthebodyeect, thedraincurrentcanbewrittenas:IDS=nCox2_WL_(VGSVth)2, (2.1)wherenisthesurfacemobilityof theelectronsintheNMOSchannel, Coxistheoxidecapacitanceperunitarea, andVthisthedevicethresholdvoltage. Thusthe10VddCGmGmL/2 L/2 L/2Figure 2.2: Simple NMOS GMoscillator.quiescentbiascurrentIDS(Q)iseasilycalculated. InordertodemonstratehowthiscircuitdevelopsanegativeresistancetheFETsarereplacedwiththeirsmall signalmodels(Fig. 2.3). Thisisalowfrequencyequivalentcircuitsincetheinputcapac-itanceoftheFEThasbeenignored(thissimplicationwill bejustiedlater). ThetransconductanceforaMOSFETisdenedas:GM=IDSVGSQpoint= nCox_WL_(VGSVth). (2.2)The input resistance seen looking into the cross coupled NMOS transistors can there-fore be shown to be -2GM(a full derivation of this negative resistance circuit is showninAppendixA). Inorderforthecircuitof Figure2.2tooscillate, themagnitudeof thisnegativeresistancemustbesmaller thantheparallel resistanceof thetankcircuit.2GM> Rp(2.3)The ratioof negative resistance,2GM, tothe equivalent parallel resistance, Rp, isreferredtoasthestartupsafetyfactor. Integratedoscillatorsareusuallydesignedwith a startup safety factor of at least 2. It should be noted that this excess negative11GmGmIBIASRTH= ?(a)+-V1+-V2GmV2GmV1RTh-2Gm=(b)Figure 2.3: CrosscoupledNFETsandDCequivalentcircuit. (a)CrosscoupledNFETs.(b) Small signal model of cross coupled NFETs.resistance does not result inanexponentiallygrowingoscillationamplitude sincenonlineareectsultimatelylimitthemaximumvoltageswing.Fourdierenttopologiesfor GMoscillatorsareshowninFigure2.4. Figure2.4(b)showsaPMOSimplementationthatissimilartotheNMOSoscillatoralreadydis-cussed[shownagaininFig. 2.4(a)]. Theanalysisof thiscircuitisnearlyidentical,except for polaritydierences. However, sincethemobilityof holes (p) is lowerthan electrons, and the magnitude of the threshold of PMOS devices (|Vth|) is usuallyhigher than NMOS devices,the PMOS devices will need to be roughly twice the sizeoftheNMOSdevices.Inthe simple NMOSoscillator the DCbias was set bythe supplyvoltage, sinceVGSandVDSwerebothequal toVDD; thus, byEquation2.2, thetransconductanceis denedsolelybythe size of the devices. This severelylimits the exibilityofthecircuitsincethenegativeresistanceiseectivelycontrolledbythepowersupplyvoltage. Varying the negative resistance will also vary the oscillation amplitude. Thisisanextremelyimportantfactsincethephasenoiseperformance(discussedinSec.12VddCGmGmL/2 L/2 L/2(a)VddL LCVdd Vdd Vdd Vdd Vdd(b)VddItailbiasL LCGmGm(c)VddItailL LCVdd Vdd Vdd Vdd Vddbias(d)Figure 2.4: PMOS and NMOS GMoscillators.13LCVddItailbiasGmpGmnGmpGmnFigure 2.5: CMOS GMOscillator2.6) of the oscillator depends directly on the oscillation amplitude. For these reasonsit is desirabletohaveameans of controllingthenegativeresistance; this maybeachievedbylimitingthesupplycurrent. Figures2.4(c)and2.4(d)showtheNMOSandPMOSversionsof thiscircuitwithaFETcurrentmirrorthatcanbeusedtocontrol thebias current, andthereforethenegativeresistanceof thecircuit. Thebiascurrentthatowsthroughthemirrordeviceisreferredtoasthetail current.Thevalueof thistail currentalsosetsthetotal powerdissipationof theoscillator.Havingameansofcontrollingthebiascurrentallowsthedesignertomakethebestcompromise between phase noise and power dissipation. However in some cases it maybeadvantageoustoeliminatethetailcurrentsourceentirelysinceitwillcontributedevicenoisetothecircuit.Thecomplementary GMoscillator circuit is theresult of usingbothPMOSandNMOScrosscoupledpairsinparalleltogeneratethenegativeresistance. Figure2.5shows a simple CMOS GMoscillator. Since the same bias current ows through both14Figure 2.6: Cross coupled invertersthePMOSandNMOSdevices,thenegativeresistancecanbetwiceaslargeforthesamepowerconsumption. ViewingthenegativeresistancesgeneratedbythePMOSand NMOS devices in the manner discussed above, the total negative resistance of thiscircuitistheparallel combinationofthetwoindividual cross-coupledFETcircuits.Thus,thenegativeresistanceisgivenby:Rnegative=2GMn +GMp. (2.4)Itturnsoutthattheleftandrightsidesofthiscomplementary GMoscillatorareidenticaltothestructureofaCMOSinverter. ThisprovidesaveryintuitivewaytounderstandtheoperationofthecomplementaryVCO. Figure2.6showsthiscircuitredrawnas apair of cross-coupledinverters shuntedwithatankcircuit1. At DCthe outputs of the inverters are shorted to their inputs through the inductor creatingnegativefeedbackwhichdrivestheinverterstowardtheirswitchingpoints(usuallynearVDD2). Atypical invertertransfercharacteristicisshowninFigure2.7. Inthiscircuit the output of the inverter is forced to be equal to its input. At this bias pointan inverter will operate as a high gain inverting linear amplier rather than as a digitalswitch. However, at the resonant frequency of the tank circuit the positive feedback ofthecrosscoupledinverterssatisesthenecessaryconditionsforoscillation. Itisalsoinstructive to note the similarity between this circuit and the Pierce crystal oscillator,1Digital designers will recognize these cross-coupled inverters as a latch. In digital systems thepositive feedback creates memory, which is the foundation of sequential logic. Here the idea is thesame but both the NMOS and PMOS devices operate in saturation.15Figure 2.7: Inverter bias point.whichhasoftenbeenusedtogenerateaccuratedigital clocksignals(Fig. 2.8). Inthe Pierce oscillator circuit the crystal acts as aninductance that resonates withthecapacitorsof thefeedback-network. Replacingthecrystal withaninductor,andcombiningtwoofthesecircuitsanti-parallel, yieldsthecircuitofFigure2.9(a).Combining the parallel inductors and capacitors of this circuit reduces it to the circuitofFigure2.9(b). Recall that, sincethecircuitofFigure2.6isdierential, thetankcircuitelementscanbesplitintogroundedsingleendedelementsbyexploitingthevirtual groundalongtheaxis of symmetryinthecircuit. Becauseof this virtualgroundthereisanequivalencebetweenthesingleendedcapacitorsinthecircuitofFigure2.9(b)andthedierentialtankcapacitanceofFigure2.6.16Figure 2.8: Pierce crystal oscillator.(a) Anti-parallel(b) Simplied CircuitFigure 2.9: The complementary GMoscillator as a Pierce oscillator.17VddItailbiasGmpGmnGmpGmnVTEST+ -(a) (b)Figure 2.10: De-embedded nonlinearity. (a) Test circuit. (b) I-V characteristic.2.3 AnalysisofTheComplementary GMOscilla-torWhilethepriordiscussiongivesaconceptual understandingoftheoperationofthecomplementary GMoscillator, analyzingitasanegativeresistancecircuitismoreuseful for design purposes. To help understand the operation of this circuit the entireactiveportionof thiscircuitcanbede-embeddedasasimplestaticnonlinearI-Vcharacteristic. This canonlybedoneinsimulationsince, inreality, thenegativeresistance will try to sink power into the DC source (However, if a positive resistanceis shuntedacross the negative resistance thenthe negative resistance canbe de-embeddedfromthe measurement of apositive resistance.). Figure 2.10(a) showsthetest circuit that was usedtode-embedtheI-VcharacteristicshowninFigure2.10(b). For dierential voltages near zero the I-V characteristic has a negative slope,andthusexhibitsanegativeresistance. ThenegativeresistanceregionextendsfromVDD2toVDD2, whichis3.3 V fortheworkinthisthesis. ThissimplenonlinearI-Vcurvecanbeusedtosimulatethe GMoscillator. Figure2.11showsasimplelossy18i=f(v)R L Cv+-iFigure 2.11: Ideal nonlinear oscillator circuittank circuit in parallel with a device having this nonlinear characteristic. This circuitcanbesimulateddirectlyinatraditional(e.g. SPICE)circuitsimulatorifasuitablenonlinear voltage controlled current source is available. However, since this is a simpleparallel circuit, the formulation of a dierential equation is straightforward. Standardcircuitanalysistechniquesyield:byKCLatthetopnode: 0 = f(v) +vR+iL +Cdvdttheinductorvoltageis: v= LdiLdtrearrangingtherstexpression: iL= f(v) vR CdvdtdierentiatingthisexpressiondiLdt= ddt f(v) 1Rdvdt Cd2vdt2thustheinductorvoltageis: v= L ddt f(v) LRdvdt LCd2vdt2rearrangingtheterms: LCd2vdt2+LRdvdt+L ddtf(v) +v= 0(2.5)This equation completely describes the oscillator, where i = f(v) is the de-embeddednonlinearity. ThecircuitinFigure2.11wassimulatedusingSpectre[21]andEqua-tion 2.5 was solved using Mathematica [22]. A derivation of the relationship betweenoscillatoramplitudeandtheparallelresistanceisincludedinAppendixB. Itisim-portant to note that this model represents the staticor DC nonlinearity of the circuit.Ideal capacitancescanbeaddedtothetankcircuittoaccountfortheparasiticsofthedevice; However, itshouldbenotedthattheparasiticcapacitancesof thetank19arealsononlinearthemselves2. Neverthelessthissimplede-embeddednonlinearI-Vcurvedoesanexcellentjobofpredictingthecircuitbehavior, andisextremelyfastsince computationally intensive BSIM3v33[23] MOSFET equations are not evaluatedwitheachiteration. Thesimulatorneedonlycomputethevalueofthefunction f(v)anditsderivativesforeachiteration.2.4 FrequencyLimitationsof GMOscillatorsIn the preceding analysis the parasitic resistances and capacitances of the MOSFETswereignored. Theparasiticcapacitancesof thegate-to-sourceregion, Cgs, andthegate-to-drain region, Cgd, can be represented as a single capacitor in parallel with thetank capacitance. Figure 2.12 illustrates how Cgd appears directly in parallel with thetankcircuit. Theotherparasiticcapacitorscanalsoberepresentedinparallel withthe tank if a virtual ground is assumed. The net eect of these capacitances togetherwill be to tune the oscillator to a lower frequency. This must be accounted for in thedesignifaspeciccenterfrequencyisdesired.Amore important eect of these parasitic capacitances is that theydecrease theoscillatortuningrange. Thisisbecausethesecapacitancesarexed, yettheycon-tributesignicantlytothetotal tankcapacitance, leavingonlyasmall portionofthis capacitance for frequency tuning. Figure 2.13 shows a representation of the tankcircuitwiththevaractorcapacitanceandtheparasiticcapacitanceinparallel. Theoscillationfrequencyisdeterminedbytheresonantfrequencyofthetankcircuit:fo=12_L(Cparasitic +Cvaractor)(2.6)AsCparasiticbecomeslargerelativetoCvaractortheoscillationfrequencybecomesless2Indeed, the voltage dependence of the MOS capacitance will be used later to design a varactorfor tuning the oscillator frequency3BSIM3 is a physics-based, accurate, scalable, robustic and predictive MOSFET SPICE modelfor circuit simulation and CMOS technology development.[23]20LCVddItailbiasGmpGmnGmpGmnFigure 2.12:Cgd in parallel with tank circuit.L ReqCvaractorCparasiticFigure 2.13: Tank circuit with parasitic capacitance in parallel21variable. The tuning range of an oscillator is often expressed as a ratio that is denedas:TuningRange =fmaxfminfcenter= 2 fmaxfminfmax +fmin(2.7)Wherefmax, fmin, andfcenterarethemaximum, minimum, andcenterfrequenciesrespectively. If the varactor can tune from Cminto Cmax, by combining Equations 2.6and2.7andfactoringoutthecommonterms,thetuningrangecanexpressedas:TuningRange = 2 1Cparasitic+Cmin1Cparasitic+Cmax1Cparasitic+Cmin+1Cparasitic+Cmax(2.8)ItcanbeshownthatthelargesttuningrangewillbeachievedwhenCparasiticisverysmall. Thisisaveryimportanttradeoin GMoscillatordesign. Increasingthedevice size will increase the negative resistance yielding a large amplitude oscillation,but larger devices will have correspondingly larger parasitic capacitances. This trade-obetweendevicesizeandtuningrangewilldominatethedesignoftheoscillator.ThediscussionofSection2.3alsoignoredtheimpactofgateresistance. Whilethegateresistanceof aproperlydesignedMOSFETcanbemadeverysmall byusingmultiplengers(i.e. devicesinparallel),itisimportanttounderstandthatitisthegate resistance that is responsible for the upper frequency limit of the GMcircuit4.IfthereisaresistanceinserieswiththegatecapacitanceofthecrosscoupledFETsthenthenegativeresistancewill havealowpass frequencycharacteristic. Figure2.14showsasimplesmall-signalMOSFETmodelwithgateresistance(Rg)andthegate-to-source capacitance (Cgs) added. Cgd is ignored since it can be lumped into thetank circuit. The input admittance of a cross coupled FET pair using this small-signalmodelisgivenby(derivedinAppendixA):YIN=12_Cgsj 11 +RgCgsj_. (2.9)4The highest oscillation frequency for anyactive device is dened asfmax, the unilateral powergain frequency. fmaxdepends on device size, whereasft, the unity current gain frequency is inde-pendent of device size [24].22+-RgCgsVgsGMVgsFigure 2.14: High frequency MOSFET model.TheinputadmittancecontainsapolecreatedbyRGandCGS, whichwill tendtoincrease the magnitude of the negative resistance at higher frequencies. In most casesthispolewillbewellabove10GHz,evenforapoorlydesignedFET.However,thiscanstillbeafactorsincethenegativeresistancewillbeginrollingoatfrequencieslowerthanthispolefrequency(recallthatapolerepresentsahalfpowerpoint, notasharptransitionfrequency). Inordertominimizetheeectofthishighfrequencyrollo, theFETsmustbelaidouttominimizeparasiticgateresistances. Thegateresistanceof aFETcanbereducedsignicantlybyusingmultiplengers. DetailsonhowthiscanbeachievedforthecircuitsinthisthesisarediscussedinChapter5. Becausethegateresistanceof aMOSFETcanbemadeverysmall, it canbeadvantageoustouseMOSdevicesratherthanBJTsin GMoscillators. Thehighfrequencylimit wouldbemuchlower for aBJTVCOsincethebaseresistanceofBJTsisquitelarge[7]. However, anumberof otherimportantfactorshavemademostBJToscillatordesignssuperiortothoseimplementedinCMOS.232.5 Advantages and Disadvantages of the Comple-mentary GMOscillatorOne important dierence between the complementary GMoscillator and its NMOS-only or PMOS-only counterparts is that in the complementary version, the dierentialvoltageswingislimitedtothesupplyvoltage. ThislimitationisnotpresentintheNMOS-onlyorPMOS-onlyversions. Figure2.15showstheoutputwaveformsofanNMOS-onlyandacomplementary GMoscillator. InbothcasestheQofthetankcircuit is assumed to be high so that the oscillation amplitude overdrives the FETs. Inthe case of the NMOS only circuit the AC voltage at the drain of the transistors swingsaboveVDD. InthecomplementarycircuitasimilarvoltageexcursionisimpossiblesincethePMOStransistorswouldbedrivenintocuto,shuttingothebiascurrentneeded by the NMOS devices. Recall from Section 2.3 that the negative resistance ofthe complementary oscillator extends from VDD2toVDD2; thus, in the complementaryoscillator, themaximumdierential oscillationamplitudeisapproximatelyequal toVDD. Therefore, the complementary oscillator is amplitude limited by both the supplyvoltage and the tail current source. On the other hand, the PMOS-only or NMOS-onlyversions are limited only by the bias current. Typically this is not a severe limitationforfullyintegratedCMOSVCOdesigns;since,forreasonablysizeddevices,thelowquality factor of the tank will likely limit the oscillation amplitude long before supplyvoltageheadroombecomesaconcern. Itshouldbenotedthatthedistortionseeninthe NMOS-only [Fig. 2.15(c)] waveform is typically not a problem since the output ofthe oscillator is typically limited to a square wave,either by logic or in the switchingstageofanintegratedmixer.One slight advantage of the complementary topology is its ease of implementation as apair of cross coupled inverters. For use in a digital system, the active part of the circuitcouldbeimplementedusingexistinginverterlayoutcells,althoughthisisnotlikely24VddCGmGmV+V-L/2 L/2(a)LCVddGmpGmnGmpGmnV+V-(b)(c) (d)Figure 2.15: Amplitude limiting of NMOS and CMOS oscillators. (a) NMOS only oscillator.(b) Complementary oscillator. (c) NMOS only waveforms. (d) Complementarywaveforms.25cFigure 2.16: Ideal oscillator output spectrumto result in an optimal design. In addition, the output voltages of the complementaryoscillatorarealreadyatlogiclevel(i.e. DClevel=VDD2withrail-to-railswings)andinterfacing to standard CMOS logic is straightforward. The complementary structurehas also been shown to be advantageous for minimizing the upconversion of 1/f noiseintonear-carrierphasenoise[9]. ThisishighlyimportantinCMOSoscillatordesignsinceMOStransistorstypicallyhaveamuchhigher1/fnoisecornerthandoBJTs.It is for these reasons, along with the elegant simplicity of the cross coupled structurepresented in Sections 2.2 and 2.3, that the complementary GMtopology was chosen.2.6 OscillatorPhaseNoiseThemostimportantcharacteristicofanRFoscillatorisitsfrequencystability. Anidealoscillatorwouldhaveafrequencyspectrumthatconsistsofaunitimpulsecen-teredattheoutputfrequency(Fig. 2.16). Inthetimedomain, suchanoscillatorwouldhaveanoutputvoltagewiththefollowingform:Vout(t) = Asin(0t +). (2.10)However,realoscillatorsareimplementedwithphysicaldeviceswithinherentnoise.Thisdevicenoisemanifestsitself inboththeamplitudeandphaseof theoscillator26Figure 2.17: Phase noise in oscillator output spectrumoutputsuchthattheoutputofapracticaloscillatoris:Vout(t) = A(t) sin(0t +(t)). (2.11)Since A(t) and (t) are now functions of time, the frequency spectrum of Vout will con-tain noise sidebands near the oscillation frequency. Most oscillators have an inherentnonlinear limiting mechanism that attenuates A(t). For example, the tail current andsupply voltage limiting discussed in Section 2.5 limit the amplitude in the NMOS andCMOS GMoscillators. InmanyRFsystemstheoutputof anoscillatorisampli-tudelimitedbeforeitisusedasaninput toamixer. WhenawaveformisamplitudelimitedsomeoftheAMnoise[A(t)]thatispresentisconvertedtophasenoise. Forthesereasons,onlyphasenoiseisusuallyconsidered.Phase noise is quantied by considering the noise power (relative to the carrier power)ina1 Hzbandwidthatanosetfromthecarrierfrequency(Fig. 2.17). Thesingle-sidedspectralnoisedensityisdenedby:L{} = 10 log_Noisepowerat(0 + )in1 HzBandwidthcarrierpower_, (2.12)27L()Noise Floor1f31f21/f3 Figure 2.18: Typical oscillator phase noise spectrumwheretheunitsaredecibelsbelowthecarrierperHertz(dBc/Hz). Thephasenoiseof a typical oscillator versus oset frequency, , is shown on a logarithmic frequencyscaleinFigure2.18.Thephasenoiseof oscillatorshasbeenstudiedwidelyintheliterature[8],[10],[25],[26]. Alineartimeinvariantmodel forphasenoisewaspresentedbyLeesonin[8]andwasexpandeduponin[7]. Thismodelpredictsthephasenoisetobe:L{} = 10 log_2FkTPs_1 +_02QL_2__1 +1/f3__, (2.13)where Fis the device excess noise factor, kis Boltzmans constant, Tis the absolutetemperature, Psistheaveragepowerdissipatedintheresonator, QListheloadedqualityfactorof theresonator, and1/f3 isthecornerfrequencybetweenthe1/f3and1/f2regions, showninFigure2.18[9]. Fand1/f3 areempirical parameterswhichareseldomknownduring theinitialdesignofanoscillator. Frepresents noisecontributed by the active devices in the oscillator. This equation can correctly modelall threeregionsof thetypical phasenoisecharacteristicshowninFigure2.18if Fand1/f3 areaccuratelyknown. Howeverthisisnotoftenthecaseforthecircuitdesigner, sinceFdoesnotincludenonlinearfrequencyconversioneects, and1/f328is typicallynot thesameas thedevice1/f noisecorner. Accuratepredictions ofphasenoiseusingLeesonsequationshavebeenlimitedtorelativelyhighQ,discreteoscillatordesigns. AkeyproblemwithLeesonsequationisthatthismodelassumesthatoscillatorsarelinear, time-invariant(LTI)systems, whichinpracticeisneverthecase[25].Amore accurate time domainmodel has beenproposedbyHajimiri andLee in[9]. Thismodelmoreaccuratelyaccountsforalltheprocessesinvolvedinconvertingdevice noise into phase noise. The linear time variant (LTV) phase noise model is abletoaccountfortheupconversionof 1/fdevicenoiseintolowosetphasenoise(i.e.1/f3, etc). The time variant model also more accurately models the noise folding thattranslatesnoiseatharmonicsoftheoscillationfrequencyintothephasenoiseskirtsof thefundamental frequency. TheLTVphasenoisemodel introducestheconceptoftheimpulsesensitivityfunction(ISF), (0), whichexpressesthephasechangeintroducedintoanoscillatorasafunctionofthetimeintheoscillationtheimpulseisintroduced. UsingthisapproachHajimiri andLeeshowthattheupconversionof1/fnoisecanbeminimizedbyminimizingtheDCcoecientC0of(0). Inthecaseof anLCoscillator, (0) depends onthesymmetry of thewaveform. Theconclusiondrawnin[9]isthatthecomplementary GMoscillatorcansuppresstheupconversionof 1/f noise, sinceit canbedesignedtocreateamoresymmetricaloutput waveform than non-complementary designs. Recall from Figure 2.15 that theNMOS-onlyoscillatorhasaquiteasymmetricwaveform.While the LTV phase noise model is generally believed to be the most accurate methodreported for determining the phase noise of an oscillator, it is not very straightforwardto implement in practice. The diculty lies in the calculation of (0),which mustbecalculatedandminimizedforeachnodeofthecircuit. Inaddition,accuratenoisemodelsforCMOSdevicesareoftenunavailabletoRFdesigners.To simplify matters in this work, phase noise is predicted using the simple expression29[7]:L{} =kTReff[1 +A]_0_2V2A/2, (2.14)where Reffis the equivalent series resistance, VAis the peak voltage amplitude acrossthetankcircuit, andAistheexcessnoisefactorwhichissetequal totheoscilla-torstartupsafetyfactor(theratioof equivalentparallel resistancetothenegativeresistance). ThereasonforsettingAequal tothestartupsafetyfactorisintuitive:ifA=0theactivedevicescontributenonoisetotheoscillator; ifA=1theactiveandpassivedevicescontributeequal amountsof noise. BysettingAequal tothestartupsafetyfactor, theactivedevicescontributeproportionallymoremorenoisethanthepassives. Reffisnotaphysicalresistancecomponent, butratherawayofrepresentingthetotal loadedqualityfactorof thetankcircuit. ThisexpressionisthereforeequivalenttoLeesonsbasicequations. Aderivationof thisexpressionisfound in [7]. This model enabled straightforward hand calculations of phase noise (inthe1f2region)duringthedesignphase.30Chapter3InductorDesign3.1 BackgroundAn important quantity in the characterization of resonant tank circuits is the qualityfactor(Q),whichisdenedas:Q = 2maximumenergystoredenergydissipatedpercycle. (3.1)The resonator Q will strongly inuence both the phase noise and the power consump-tionof anoscillator. TheinductorinanLCoscillatorisusuallythemostcriticalcircuitelementinthedesigntypically,theQoftheinductordominatesthetotalQof thetankcircuit. Inaddition, thetuningrangeof aVCOisstronglyaectedbytheself-resonantfrequency(fsr)ofaninductor. Theselfresonantfrequencyisthatfrequencyatwhichcapacitiveparasiticsresultinazeronetreactance; beyondthisfrequencytheinductorbecomescapacitive.Traditionally, inductorshavebeenincorporatedasdiscretecomponentslocatedo-chip (often as small surface mount parts). While o-chip inductors can have extremelygoodperformance, itisdesirabletoeliminateasmanydiscretecomponentsaspos-sible. Thisreducestheboard-level complexityandcomponentcount, whichinturn31leadstoadirectreductionincost. Asanalternativetoo-chipinductors,someRFintegratedcircuits haveutilizedbondingwires as hybridinductors [7],[27]. WhilebondingwirescanhavearelativelyhighQ(ontheorderof50),theycanalsosuerfromlargevariationsininductancevaluesincewirebondingisamechanicalprocessthatcannotbeastightlycontrolledasaphotolithographicprocesses.Monolithic inductors fabricated as simple planar spirals are now widely used on GaAssubstrates with Qs in the range of 10-20. The inductance of a monolithic inductor isdened solely by its geometry. Modern photolithographic processes provide extremelytight geometric tolerances. For this reasonmonolithic inductors have verysmallvariationsintheirperformance.UnlikestandardSi technologies, GaAsprocessesaremoreconducivetothefabrica-tionof monolithicinductorssincetheGaAssubstrateisanearlyperfectinsulator( =108 cm) andthemetalizationusedisoftenthickelectroplatedgold( =4.1 107S/m). Siliconsubstrateshavearesistivitythatvariesfrom10 100 cmfor Bipolar and BiCMOS to as low as 0.01 cm on some digital CMOS processes. Fur-thermore, the metalization has traditionally been aluminum which has a low thin-lmconductivity(althoughcopperhasappearedrecentlyasanalternativeinterconnectmetal [28],[29]). MonolithicinductorsarebecomingpopularforBiCMOStechnolo-gies,especially the newer SiGe processes which are tailored for RF design [30]. How-ever, theseprocessesarestill morecostlythanthestandarddigital CMOSprocess.Thedreamof manyRFICdesigners is tobeabletoleveragethesameeconomiesof scalethathavesupportedMooreslawfornearlytwoandahalf decadesfortherealization of RF systems. For this reason, much recent eort has been focused on theproblemoffabricatingRFinductorsinCMOSprocesses. Inthischaptermonolithicinductordesigninageneric1digitalCMOSprocessisexplored.1generic = low-resistivity substrate,single layer of poly, strict adherence to DRC rules, and noextra post-processing steps.32(a) (b) (c)Figure 3.1: Spiralinductorgeometries: (a)circularspiral. (b)octagonalspiral(c)squarespiral.3.2 InductorGeometriesThere are many ways to lay out a planar spiral inductor. The optimum structure is acircular spiral. This structure [Fig. 3.1(a)] places the largest amount of conductor inthe smallest possible area, reducing the series resistance (Rs) of the spiral. This struc-ture, however, is not often used because it is not supported by many mask generationsystems. Manyof thesesystemsareabletoonlygenerateManhattan(Manhattanstyle layouts only contain structures with 90 degree angles, like the streets of Manhat-tan, NY.) geometries (and possibly 45 angles as well). While the curved metal tracescanbeapproximatedinastep-wisefashion,asimplersolutionistoapproximatethecirclewithapolygon. Figure3.1(b)showsanoctagonalspiralthatonlyrequiresthemaskmakertogenerate45anglesinadditiontothestandardManhattangeome-tries. ThisstructurehasaQthatisslightlylowerthanthecircularstructure,butismuch easier to layout. For the CMOS process used in this thesis non-Manhattan-styleshapesareallowedbut notrecommended. ForthisreasonthestandardsquarespiralstructureofFigure3.1(c)waschosen. Thesquarespiralstructuredoesnothavethe33davgdavgn=3Figure 3.2: Parameters for Equation 3.2.bestperformancebutitisoneoftheeasieststructurestolayoutandsimulate.Thesquarespiralinductorhasbeenstudiedextensivelyin[29],[31],[32]. Thefollow-ing recently published expression has demonstrated good accuracy for predicting theinductanceofasquarespiral[33]:L =20n2davg_ln_2.067_+ 0.178 + 0.1252_, (3.2)wherenis thenumber of turns inthespiral, andtheparameters davg, andaredened in Figure 3.2. 0is the permeability of free space, davgrepresents the averagediameterof thespiral, andrepresentsthepercentageof theinductorareathatislledbyturns. Equation3.2isbasedonacurrentsheetapproximationofthespiralstructure, and is valid only for square spirals2. Predicting parameters such as inductor2Reference [33] also presents a range of expressions that are valid for other geometries.34Q and Self Resonant Frequency (fsr) generally cannot be done with a simple formula.Theseparametersareusuallyobtainedthroughsimulation.3.3 LossesinspiralinductorsThere are several sources of loss in a spiral inductor. The most obvious loss mechanismis theseries windingresistance, Rs. Theinterconnect metal usedinmost CMOSprocesses is aluminum. Depending on the metalization thickness and particular alloyused,thesheetresistivitycanbeanywherefrom30-70m/. TheDCresistanceofthespiraliseasilycalculatedastheproductofthissheetresistanceandthenumberof squaresinthespiral. However, athigherfrequenciestheresistanceof thespiralincreasesduetotheskineectandcurrentcrowdingatthecornersofthespiral.Asmentionedabove, theintroductionof coppermetalizationandthickupper-levelinterconnect have yielded improvements in the maximum inductor Qs that have beenreportedinCMOS[29]. Inaddition,multiplelevelsofmetalizationmaybestrappedtogether to create a spiral with a lower DC winding resistance [34]. However, substratelossesultimatelyremainthelimitingfactorevenwhentheconductivityofthespiralwindings is no longer an issue. Since the silicon substrate is neither a perfect conductornor insulator there are resulting losses in the reactive elds that surround the windingsofthespiral.Figure3.3showsthelossesduetotheelectriceldsintheinductorstructure. InaCMOSprocessthewindingsofthespiralareseparatedfromthesubstratebyathinlayerofsilicondioxide(SiO2). Thiscreatesacapacitancebetweenthespiralandthesurfaceof thesubstrate. Inmostdigital CMOSprocesses, thissubstrateisheavilydopedp+materialandistiedtogroundpotential. Thus,thesubstrateappearsasagrounded resistor in series with this capacitance. This substrate capacitance has twodetrimental eects in a circuit: (1) it allows RF currents to interact with the substrate,35WindingsOxideP+ BulkFigure 3.3: Electric eld (capacitive) losses.lowering the Q of the circuit;(2) it increases parasitic capacitances, reducing the selfresonantfrequency(fsr). Thiscapacitancecanbereducedbydecreasingtheareaoccupiedbytheinductortraces,butthisinturnwillincreasetheseriesresistanceoftheinductor. Thisisanimportanttradeo, sincewidetracesaregenerallyusedininductorsonsilicontoovercomethelowthin-lmconductivityof themetalization.Thisalsolimitsthefeasibilityofcreatingarbitrarilylargevaluedinductances.Figure3.4showsthelossesduetothemagneticeldintheinductorstructure. Themagnetic eld

B(t) extends around the windings of the spiral and into the substrate.Faradays Law states that this time-varying magnetic eld will induce an electric eldinthesubstrate. Thiseldwill forceanimagecurrent toowinthesubstrateintheoppositedirectionofthecurrentinthewindingdirectlyaboveit. Theseimagecurrentscanaccountfor50percentormoreof thelossesinaCMOSinductor[7].This eect canalsobethought of as aparasitictransformer, wherethesubstraterepresents anunwantedsecondarywinding. Larger inductors will have magneticeldsthatpenetratedeeperintothesubstrate, andwillthereforesuerfromhighersubstratelosses. Thiseectisinoppositiontothegoal oflimitingseriesresistance36WindingsOxideP+ BulkI I-I -IMagnetic Field, B(t)Ieddy-IeddyFigure 3.4: Magnetic eld (inductive) losses.withwidespiral traces. Thesubstrateeectscouldbeavoidedbyutilizingapostprocessingsteptoetchthesubstrateawayundertheinductor[35],howeverforthisresearchnonon-standardprocessingstepswereused. UsingsuchexoticprocessingstepswoulddefeatthepurposeofimplementinganRFcircuitinastandarddigitalCMOSprocess.Themagneticeldwillnotonlypenetrateintothesubstratebutalsointotheotherwindings of the coil, further increasing the loss [7]. Figure 3.5 shows the eddy currentsthat are generated in the center of a winding. This eect causes the inner turns of theinductor to contribute much more loss to the inductor while having a minimal impactontheactual inductance. This phenomenonis sometimes referredtoas currentcrowding[2],[36]. In[2]a9turninductorwassimulatedusinganite-elementeldsolver. Itwasfoundthattheresistanceoftheouterturnat2GHzwas18%higherthanitsDCvalue; however, theresistanceoftheinnerturnat2GHzincreasedby480%overitsDCvalue. Forthisreasonspiral inductorsonsilicontypicallyutilizehollowcentersinordertoincreasetheirQ[7].37Figure 3.5: Eddy currents in the spiral windings [2].3.4 InductorCircuitModelsAcircuitmodel foramonolithicinductoronalow-resistivitysubstrateisshowninFigure 3.6 [32]. This model includes circuit elements that model the loss mechanismsthatwerediscussedinSection3.3. Thiscircuitaccuratelymodelsinductorsonlowresistivity silicon substrates since it includes the eect of the magnetic eddy currents.The magnetic substrate loss is representedinthis model as anideal transformercoupledtotheresistor,Rsub(m).Someconfusionexistsintheliteratureregardinghowthequalityfactor(Q)andin-ductance(L) of amonolithicinductor shouldbedened, particularlywithregardtodierential (balanced)versussingle-ended(unbalanced)implementations. Typi-cally, theinductanceof amonolithicinductoriscalculatedbyconvertingmeasuredorsimulatedS-parametersintoY-parameters. TheseY-parametersarethenusedtoextract the value of L and Q. In cases where one side of the inductor is grounded (i.e.single-endedorunbalanced),Lisoftendenedas:L = Im_1Y112f_. (3.3)38RsubRsubCFL RsCOXCOXCsubCsubCsubPort 1 Port 2Rsub(m)Figure 3.6: Spiral inductor lumped circuit model.Inother cases wheretheinductor is useddierentially(i.e. balanced), Lis oftendenedas[32],[37],[31]:L = Im_1Y122f_(3.4)Dependingupontheinductorapplicationeitheroftheseexpressionsmaybeaccept-able.To understand the dierence between the above denitions it is helpful to look at theequivalentofatwo-portnetwork(Fig. 3.7). Thiscircuitmodelexpressesthetwo-portY-parametersasadmittancesinanetwork. Forapassivereciprocalnetwork,Y12= Y21. Ifthenetworkissymmetric,Y11= Y22. Todeneinductanceandqualityfactor,this model must be reduced to a single element (i.e. an inductance in seriesorparallelwitharesistance). ForthecaseofasimpleserieselementR +jX:L =X(2f)(3.5)39-Y12Y11+Y12Y22+Y12port 1 port 2Figure 3.7: equivalent circuit for a two-port network.orPort 1 Port 1 Port 1Port 2ZinZinFigure 3.8: Two methods of reducing-network.andQ =XR. (3.6)There are two simple methods of reducing the -circuit to the series element, R+jX(Fig. 3.8). If port 2 of the -circuit is grounded, the Y22+Y12 element is bypassed andthecircuitlookingintoport1reducestotheadmittanceY11connectedtoground(since admittances inparallel add, Y12is eliminated). Convertingadmittance toimpedance,R +jXbecomes:R +jX=1Y11. (3.7)Ifthisassumptionisvalid,thenLandQmaybedenedusing:L = Im_1Y112f_. (3.8)andQ =Im(1Y11)Re(1Y11). (3.9)40Thismethodisvalidiftheinductorwill beusedinacircuitwhereoneterminal oftheinductorisconnectedtoACground. ThisisoftenthecaseinmanyRFcircuits,particularly in LNAs and mixers, where inductors are used for degeneration or loading.This method is also equivalent to taking one-port S-parameter measurements with oneterminal of the inductor grounded, and converting the measured reection coecent,,intoaninputimpedance. Usingthisapproachwithport2groundedyields:1= S11S12S211 +S22. (3.10)Theseriesimpedanceisthengivenby:R +jX= Zin= Z01 + 11 1, (3.11)whichisequivalenttoEquation3.7.Ontheotherhand, if theinductorwill beusedinadierential conguration(i.e.neither port is at AC ground potential) a dierent approach is required. The oatingimpedance,R +jX,seenbetweenports1and2ofthe-networkis:R +jX=_1Y12______1Y11 +Y12+1Y22 +Y12_ =Y11 +Y22 + 2Y12Y11Y22Y212. (3.12)Sinceinthiscase, theshuntelementsY11 + Y12andY11 + Y12of thenetworkaretheparasiticcapacitancestoground(perhapsinserieswithasubstrateresistance,seeFig. 3.6), theyareoftenignored(particularlyintechnologies usinginsulatingsubstrates) and L is calculated using Equation 3.4 [32],[37]. The impedance calculatedinEquation3.12isreferredtoasoatingsinceitignoresthegroundconnectioninthe equivalent circuit. This is valid, since if the inductor is connected in this manner,thegroundas representedinFigure3.7is nolonger explicit andexists onlyas avirtual ground. Inductorsconnectedinthismannerareoftenreferredtoasoatingordierential andLandQcanbedenedas:L = Im_1Y122f_(3.13)41Q =Im(1Y12)Re(1Y12). (3.14)Inmostcasesthedierential Qmeasuredusingthismethodwill beslightlyhigher(3-5 percent) than in the grounded one port case. If the shunt elements Y11+Y12andY11 +Y12arenotnegligible(asisthecaseinstandardCMOS)itismoreaccuratetouseEquation3.12inconjunctionwithEquations3.5and3.6tocalculateLandQratherthanEquations3.13and3.14.InthisthesisbothmethodsofreportingLandQareused. Althoughthetotaltankinductanceisoating, itwill actuallybeimplementedastwoidentical inductorsinseries. While, the total tank inductance uses the dierential inductor denitions, eachindividualinductorisconsideredusingthesimpliedoneportapproach. Wherenotexplicitly stated, subsequent references to L and Q in this thesis should be consideredtofollowthisconvention.3.5 InductorSimulationAlthough the inductance value can be computed using Equation 3.2, or other similarexpressions found in the literature,it is dicult,if not impossible,to accurately pre-dict analytically the losses associated with a spiral inductor. This necessitates the useofelectromagneticeldsolvers. InitiallytheinductorsinthisprojectweresimulatedusingthefreewareprogramASITIC[38], However, itwasfoundthatthisprogramunderestimatedthemagneticsubstrateeddycurrenteects. Moreaccuratesimula-tions were obtained using Sonnet EM [39]. Sonnet EM is a planar full-wave EM solver(method-of-moments)packagethatcanaccuratelycalculatetheeldsandcurrentsofaplanarstructuresuchasaspiralinductor. SonnetEMaccuratelycalculatestheeldsinthesubstrateandthedielectric, butdoesnotaccountfortheeectsofthenitemetal thickness. 2Dand2.5DplanarsimulatorssuchasSonnetEMassumetheconductivelayerstobeinnitesimallythin,withanitesheetresistivity. Thus,42thecapacitancebetweenthespiral windingsandtheeddycurrentsinthewindingsare not modeled. In order to achieve the most accurate simulation possible a full 3-Dnite-elementsimulationmustbedone. ProgramssuchasAgilentHFSS[40]canbeusedtodothisattheexpenseoflongsimulationtimes. Suchcompletesimulationswerenotdoneinthisthesis.TheseelectromagneticeldsolversreporttheirsimulationresultsinS-parameters.These results can then be numerically tted to the circuit model of Figure 3.6. How-ever, anumberof thecomponentvaluesinthiscircuitmodel varywithfrequency(both the skin eect and the substrate losses vary with frequency). For this reason itmay be desirable to simulate circuits with inductors by directly using the S-parameterdata extracted from the eld solver. Advanced circuit simulators such as Spectre canacceptS-parametersdirectlyanduseaconvolutionbasedmethodtoperformtran-sienttime-domainsimulations[21],[41]. Bothmethodswereusedinthisthesis; thelattermethodismuchslowerbecauseitiscomputationallyintensivetoevaluateS-parameters inthetimedomain. Ontheother hand, frequency-domainsimulatorsusing techniques such as harmonic balance work well with S-parameter les; however,foroscillatordesignatime-domainapproachispreferred.3.6 FinalinductordesignTheinductorsforthisprojectweredesignedprimarilybyiteration. Originally2.5GHz was the desired frequency of operation and most of the simulations were focusedon obtaining oscillation near this frequency. However, the goal of this project was notas much to design an oscillator for a specic frequency range, but rather to implementabenchmark oscillatorthatcouldbeused exploremixed-signalnoiseeects. SinceatankcircuitwithC=1pFandL=4nHresonatednear2.5GHz, thiswasthechosenstarting point for the design. The ASITIC inductor simulation tool was used initially43ReqLFigure 3.9: Simple parallel RL inductor model.tocalculatetheinductanceandqualityfactorofavarietyofstructures;SonnetEMwasusedforthenalcomparisonofvariousstructures. Itwasfoundfromtheliter-ature[7],[9],[12], thattheoutsidediameterof a4 6 nHspiral inductorinCMOStechnologyistypicallyintherange200 300 m. Thiswasusedasaguidelineformostoftheinductorgeometriesthatwereexplored.Duringtheinductordesign,thetradeobetweeninductorsizeandoscillatorcurrentdrainalsoservedasaguideline. Largevaluedinductorswillreducecurrentdrainintheoscillator. Thishappensbecauselargerinductorshavelargerequivalentparallelresistances. If theinductorismodeledasanideal inductancewithashuntresistorReq(Fig. 3.9)then:Req= Q2foL. (3.15)Largervaluesof Reqaredesirablebecausetheactiveportionof thecircuitwill berequiredtogeneratelessnegativeresistancetosustainoscillationandthusconsumeless current. However, as L is increased, its self-resonant frequency decreases becauseitsparasiticcapacitancesalsoincrease. Largerinductanceswillalsodecreasetheos-cillatortuningrange. Thisoccursbecauseasmallertankcapacitanceisrequiredtoachieve the desired oscillation frequency. As the tank capacitance becomes smaller, itgets swamped out by the parasitic capacitances. As was discussed earlier, larger areainductorswillalsohaveanincreasedsubstrateloss,sincetheirmagneticeldspene-tratedeeperintothesubstrate. Allthesefactorsmustbeconsideredwhendesigningtheinductor. Thefeasibilityof usingalargerinductorislimitedbytheparasiticsthatwillbeassociatedwiththeactivecircuitryandthevaractortuningelement.44R=6.5 ohm/sqPolyR=0.085 ohm/sqMetal 1R=0.085 ohm/sqR=0.085 ohm/sqMetal 3Metal 2Metal 4R=0.05 ohm/sqP+ Bulk 0.01 ohm cm9250 6400 10000 10000 6400 6400 10000 10000 6650 5450 2750 2900 r=3.9r=3.9r=3.9 r=3.9r=3.9r=3.96.055 m4.415 m2.775 m1.11 mField OxideFigure 3.10: CMOS process layer stack-up.The CMOSprocess usedfor this designis a0.35 msingle-poly, 4-metal processavailablethroughMOSIS3. Thevertical dimensionsof theprocesslayersareshowninFigure3.10. Themetalizationthicknesses anddielectricthicknesses areknownaccurately,butthesubstrateparametersarenotdisclosedbyMOSIS.Consequently,thesubstrateresistivitywasassumedtobe0.01 cmasthisappearstobeatyp-ical valuefor moderndigital CMOSprocesses [7],[37],[42]. Thep+substratewasassumedtobe1500 mthickthroughoutthedesign. Althoughthisisanunreason-3MOSIS is a low-cost prototyping and small-volume production service for VLSI circuitdevelopment.45Free Spacer=1r=11.93000 m1.64 m1500 mr=3.94.415 mr=3.9r=3.9=10000 S/mmetal 4metal 350 m/sq85 m/sqFigure 3.11: Simplied layer data for Sonnet EM simulations.ably large thickness for a 0.35 m CMOS process manufactured on 8 inch wafers (thewafersizeandthicknesswereunknownduringthedesignphase),itisaconservativevaluefor simulationpurposes. ManyCMOSprocesses havesubstrates as thinas650 m. Typically8inchwafersare725 mthick[43]. Sonnetsimulationsshowedthat thicker substratesyieldedlower Qs. Whensimulationswereconductedusinga650 msubstratetheresultinginductancewasnearlyidentical tosimulationson1500 msubstratesandtheQwaslessthan1percenthigher.Figure3.11shows simpliedlayer parameters usedintheSonnet EMsimulationsoftheinductors. Onlytheuppermostmetalizationlayer(metal-4)wasusedfortheinductor(metal-3wasusedasacrossover). Morecomplicatedstructuresinvolvingmultiplelevelsofmetalwereavoidedduetothedicultyofsimulatingsuchastruc-ture. Sonnet simulates these metal layers as zero thickness layers (with a given sheetresistivity)betweenthedielectriclayers. Theareaabovetheinductorisassumedtobefreespace, but theentirestructureis surroundedbyagroundedPEC(perfectelectrical conductor)cavity. Thethicknessof thefreespacelayerwaschosentobe46WODSN=3Figure 3.12: Design variables for square spiral inductor.largesothattheeectsofimagecurrentsinthePECcavityofthesimulationwereinsignicant.AsquarespiralwiththefourrelevantdesignvariablesisshowninFigure3.12. ThetwoportS-parametersweresimulatedforthisstructure, overthefrequencyrangeof 0.1-10.1GHz. Avarietyof inductorstructureswerestudiedwithoutsidediam-eters (OD) varyingfrom150 300m, tracewidths (W) from10 25m, andaninterwindingspacing(S)of2 m. Figures3.13and3.14showtheinductanceandQversusfrequencyforavarietyofinductorsthatweresimulated. Thesegraphsshowsamplesfromthelargenumberofstructuresthatwereevaluated. Thesuitabilityofthese inductors for use in the complementary GMoscillator was determined by cal-culatingtheirequivalentparallelresistance(Eq. 3.15). SomeoftheinductordesignsyieldedhigherQs, butduetotheirlowinductancevaluesyieldedunacceptablylowReq. Figure3.15showsaplotofReqversusfrequencyforthesamesetofinductors.Although some improvement in Q appears to be available by using large tracewidths47Figure 3.13: Inductance (single-ended) versus frequency for a variety of dimensions (in m).Figure 3.14: Quality factor (single-ended) versus frequency for a variety of dimensions (inm).48Figure 3.15:Reqversus frequency for a variety of dimensions (inm).(W>18 m)andlargeinductorstructures(OD>240 m)theselargegeometrieswereavoided, becausetheauthorhaddoubtsabouttheaccuracyof planar, 2.5D,simulations onsuchlargestructures. SinceSonnet EMis aplanar solver, it can-not simulate some 3D eects such as current crowding that might become importantwithlargespirals. Tominimizetheimpactoftheselargegeometryeects,asmallerstructurewaschosen.The nal inductor designthat was selectedwas athree turnspiral, withOD=220 m, W=16 m, andS=2 m. Thisinductorhasaninductanceof 2.42nHandaQof 3.06at2.5GHz(calculatedusingEq. 3.7). Thisinductorrepresentsacompromisebetweenallthedesigntradeos. ThetotaltankcircuitinductancewasimplementedbyconnectingtwoinductorsinseriesasshowninFigure3.16. Thisisdone so that the dierential oscillator will see a symmetric reactive load. SimulationspredictedaQ=3.1andL=4.59nHat 2.5GHz, for this dual inductor structure.GraphsshowingQ,L,and ReqareshowninFigures3.17,3.18,and3.19respectively4916 m 2 m220 m220 m50 mFigure 3.16: Series connected tank circuit inductor and dimensions(thisisaoatinginductor,i.e. Eq. 3.12applies).The S-parameters and -model of this inductor were used in simulations to design theoscillator. Theinductordesignthathasbeenpresentedwastheresultofanumberof iterationsaftersimulationsof theoverall oscillatorwereconsidered. Inthenextchaptertheotherhalfofthetankcircuit,thevaractor,willbepresented.50Figure 3.17: Dual inductor quality factor (dierential) versus frequency.Figure 3.18: Dual inductor inductance (dierential) versus frequency.51Figure 3.19: Dual inductorReqversus frequency.52Chapter4VaractorDesign4.1 BackgroundAlthoughthequalityfactorof thetankcircuitwill bedominatedbytheinductor,thedesignofthevaractorisalsocritical. IfthevaractorisnotcarefullydesigneditsseriesresistancecouldsignicantlylowertheoverallQofthetankcircuit,adverselyimpactingthephasenoiseoftheoscillatorTraditionally, discrete VCOimplementations have usedjunctionvaractor diodes.Thesediodesareoperatedunderreversebiasandaredesignedtoenhancethevari-abilityoftheirdepletioncapacitancewithreversebiasvoltage. Inamonolithicen-vironmentRFdesignersaremuchmorerestrictedinthechoiceof tuningelements.ThejunctiondiodesthatareavailableinastandardsiliconCMOSprocessarenotoptimizedforuseasvaractors; still, manymonolithicLCoscillatorshaveusedsuchdiodes as tuning elements [2],[7],[13]. In a typical n-well CMOS process there are threejunctiondiodestructuresavailable: n+/p-bulk,p+/n-well,andn-well/p-bulk. Theonlysuitablechoiceforajunctionvaractordiodeisthep+/n-well junction. Sincethep- bulkistypicallyconnectedtoground, theotherstructureswouldrequirea53p+ n+n-wellp- epi(a)(b)Figure 4.1: CMOS P-N junction varactor. (a) p+/n-well varactor diode cross section. (b)Typical depletion capacitance versus voltage characteristic [44].negativebias voltage in order to be reverse biased. The p+/n-well structure also hasa lower series resistance due to the higher n-well doping level compared to the p- bulk.Figure4.1showsthisstructureanditscapacitanceversusvoltage(C-V)characteris-tic. Ap+/n-well structurecantypicallyhaveaqualityfactorof20orbetter. Onedisadvantageofjunctionvaractorsisthattheycanbecomeforwardbiasedbylargeamplitudevoltageswings.544.2 MOSvaractorstructuresInthisworkaMOScapacitor,ratherthanajunctiondiode,wasusedforthetuningelementof theVCO. TheMOScapacitoroperatesinasimilarmannerasasimpleparallel platecapacitor. Inthiscasetheplatesof thecapacitorareformedbythepolysilicon gate and the channel of a MOSFET. The capacitance of this MOS devicevariesnon-linearlyastheDCgatebiasof theMOSFETisvariedthroughaccumu-lation, depletionandinversion. ThereforeastructurewhichisalwayspresentinaCMOSprocesscanbeusedasthetuningelementofanoscillator. ThissectionwillbrieyexaminethreetypesofMOScapacitorsthataresuitableforuseasvaractors.Figure4.2showsthecrosssectionsandcorrespondingC-Vcharacteristicforeachofthesestructures. EachstructureshownissimilartoaPMOStransistorsituatedinan n-well;however, these devices could also be implemented as NMOS devices in thep-bulkaswell. However,PMOSispreferredbecausethebulkterminalofann-wellcanbebiasedatavariablevoltage(inann-wellprocess),whereasthep-bulkofanNMOSdevicemustbeatgroundpotential.Dierent variations on the basic MOS structure have been explored in order to realizevaractors with the highest possible quality factor [45]. The rst structure [Fig. 4.2(a)]consistsof aPMOStransistorwiththedrain, sourceandbulkconnectedtogether(D=S=B)toformonenodeof thecapacitor, andwiththepolysilicongateastheothernode. Thisstructurehasacapacitancethatvariesnon-monotonically1, sincethedevicecanoperateininversion, depletion, andaccumulation[24],[45]. Figure4.2(b)showstheDCtuningcurveof thisstructure. ThemaximumcapacitanceinbothinversionandaccumulationisapproximatedbyCox, whichcanbecalculatedfrom the device dimensions as a simple parallel plate capacitor. If fringing eects are1A function that is not strictly increasing or decreasing (i.e. a function that has a local minimumor maximum)55p- epip- epip- epin-wellp+ p+ p+ n+(a) (b)n+ n+n-wellp- epip- epip- epi(c) (d)Vddp- epip- epip- epin-wellp+ p+ p+ n+(e) (f)Figure 4.2: MOS capacitor structures. (a) D=S=B structure. (b) D=S=B C-V curve. (c)Accumulation mode structure. (d) Accumulation mode C-V curve. (e) Inversionmode structure. (f) Inversion mode C-V curve.56neglected:Cox=3.90WLtox(4.1)wheretoxisthegateoxidethicknessandisapproximately76Ainthisprocess. IfaMOSvaractoristobeusedasthetuningelementofanoscillator(asinthisthesis),thenthenonmonotoniccharacteristicofFigure4.2(b)canbeproblematicaswillbeseeninsection4.4.The C-V curves shown in Figure 4.2 are the DC or small signal characteristics. Thesecurves characterize the capacitance versus voltage for a very small signal superimposedontotheDCbiasvoltage,Vgs. Ifthesignalvoltageappliedacrossthedeviceislarge(asinaVCO),thentheinstantaneousvalueofthecapacitancechangesthroughoutthe signal period. The eective capacitance seenbythe large signal will be theweightedaverageof thesmall signal capacitanceover asingleperiod. BecauseofthisaveragingeecttheRFfrequencyversustuningvoltageandtheDCsmall-signal tuning curve (shown here) will not be equivalent. The eect of this large signalaveraging is to ll in the local minimum of Figure 4.2(b), degrading the tuning rangeof the oscillator. This large signal averaging eect will be discussed further in Section4.4MOScapacitors mayalsobe designedtooperate inaccumulationmode. Figure4.2(c)showsthestructureofanaccumulationmode(A-MOS)capacitor. Thisstruc-turedepartssomewhatfromthestandardPMOStransistor,sinceitreplacesthep+diusionsofthedrainandsourcewithn+regions. Thissuppressestheinjectionofminoritycarriers(holes)intothechannel andpreventsitfrominverting. Theuseof n+regionsalsoobviatestheneedforn+ohmiccontactstobiasthen-Well, sothis structure can be smaller than the other MOS capacitors. Since this device worksinaccumulationanddepletiononly, thecapacitancecharacteristicshowninFigure4.2(d) results. While still nonlinear, the curve is now monotonic. However this struc-turehasanumberofdrawbacks. SincethisstructureisnolongeraMOStransistor,57itscharacteristicsarenotrepresentedinthedevicemodelssuppliedbythevendor(e.g. BSIM3v3[23]). Inordertosimulatethebehaviorof thisstructure, adevicesimulatorsuchasMedici2mustbeused,requiringdetailedknowledgeofprocesspa-rameters such as doping concentrations. At the time of this writing MOSIS does notsupplytheircustomerswiththisdata.ThethirdoptionistheinversionmodeMOScapacitor[Fig. 4.2(e)]. Thisstructureisidentical toaMOSFET. Thedrainandsourceareshortedtogethertoformonecapacitor terminal whilethepolysilicongateforms theother. However, thebulk(n-well)ofthisstructureisconnectedtothehighestvoltageavailableinthecircuit,VDD. Since the n-well connection of the device is always at a higher or equal potentialwithrespecttothegate, thedevicecanonlyoperateininversion. ThisyieldstheDCC-VcharacteristicshowninFigure4.2(f). Thischaracteristicisalsononlinearandmonotonic, but the transitionfromCmintoCmaxis verysharp. While thischaracteristicsuggestsanextremelylargetuninggainintheoscillator, itshouldbenotedthattheoscillatorwill tunetothefrequencydeterminedbythelargesignalaveragecapacitance (see Section 4.4). The capacitances of the D=S=B and InversionmodecapacitorsarebothsupportedbytheBSIM3v3models. Anadditionalbenetof theinversionmodestructureisthatitsn-well connectionistiedtoVDDratherthanatuningvoltage, andthereforethedeviceislessvulnerabletolatch-up3. Forthesereasons,inversionmodevaractors(I-MOS)areusedinthisthesis.2Medici is a registered trademark of Avant! Corporation3Latch-up is a critical failure mechanism that can occur in CMOS circuits when high frequencypulses turn on a parasitic silicon controlled rectier existing across the substrate betweenVDDandground [6].58V+ V-VTUNEVddFigure 4.3: Series varactor connection4.3 VaractorDesignandLayoutTheMOSvaractordesignwastightlycoupledtotheoverall LCtankcircuitdesignandthedesignofthecompleteoscillator. AswasstatedinSection3.6,thestartingpointforthisdesignwasatankcircuitwithC=1pFandL=4nHwhichresonatesnear 2.5GHz. The total tank capacitance is formed by the combination of the variabletuningcapacitance(varactors)andparasiticcapacitancesassociatedwiththecircuitlayout,includingtheinductors.Thetuningcapacitanceisimplementedinadierential fashionbyconnectingtwoidentical PMOSvaractorsinseries(Fig. 4.3). Therefore, thetankvaractorcapaci-tance is half the value of the individual varactors. If the circuit is properly balanced,connectingthetuningcapacitorsinseriescreatesavirtual groundatthecommonnode. Thetuningvoltagecanbeappliedatthisnodethrougharesistor. Becauseofthevirtualground,thedierentialvaractorconnectiondoesnotrequireACcurrentsto ow into the bulk. Therefore, this connection makes the circuit insensitive to par-asitic capacitances from the p+ diusions to the n-well and from the n-well to the p-substrate.When the additional parasitics of the oscillator (tank circuit and actives) circuit wereconsidered,it was decided to design each varactor for a maximum capacitance of ap-proximately 1pF yielding a maximum total tank capacitance of 0.5pF. The parasiticsofthecircuitprovidetheotherhalfofthetankcapacitance. Thevaractormustbe59simulated carefully since BSIM3v3 models do not correctly predict the quality factorof MOScapacitors. Forexample, usingEquation4.1, a1pFcapacitorcouldcon-ceivablybeimplementedinthisprocessusingaPMOStransistorthatis14.8minlengthandwidth. However, suchanimplementationwouldhaveverypoorperfor-mance since the resistance of the channel (Rch) and the gate (Rg) would be excessive.BSIM3v3andmostotherMOSFETmodelspredictaninniteQevenwithabadlythoughtoutdevicegeometry,sincethemodelsdonotaccountforchannelresistancewhen the drain and source are shorted. Furthermore, the resistance of the polysilicongateandthedevicecontactsarenotaccountedforinthedevicemodels.Duringtheinitial designof theoscillator it was assumedthat thevaractor wouldhaveaqualityfactorofapproximately30. Thevaractorwasactuallydesignedwhiletheoscillatorcircuitwasbeinglaidout. Thelayoutgeometryof aMOScapacitordeterminesitsQ.TheQofacapacitorwithaseriesresistanceisdenedby:Q =10RsC. (4.2)Theseriesresistanceof aninversionmodePMOSCapacitorwill includethecom-binationof the gate resistance, the contacts topolysiliconanddiusion, andtheresistanceof theinvertedchannel. Toarst approximationtheresistanceof theinvertedchannel, Rch, andthegate, Rg, canbeconsideredinserieswiththeMOScapacitor. However the situation is far more complicated than this simple treatment.Rchdependsdirectlyontheconductivityof theinversionlayerof theMOSstruc-ture, whichisbiasvoltagedependent. AcompleteanalysismustalsoconsiderthedistributednatureoftheMOSstructure. WhentheMOSgateandchannelarecon-sideredasanRCtransmissionline, andthegateiscontactedonbothendsof thechannel,theintrinsicgateresistanceisgivenby[4]:Rg=112WL Rpoly,. (4.3)Thisexpressionisvalidonlyforthepolysiliconovertheactiveregionof adevice.Extrinsicresistances suchas thoseof contacts andpolysiliconextendingfromthe60device to the contacts, and metal interconnects must be added to this expression. Anexpressionfortheseriesresistanceof anaccumulationmodevaractorisdevelopedin[46]. Thisexpressionwasmodiedslightly(Rnw,then-wellsheetresistivitywasreplaced by Rch, the inversion layer sheet resistivity.)to reect its use in an inversionmodedevice:Rs=112 1N _Rch,LW+Rpoly,WL_. (4.4)where Rch, is set equal to the sheet resistance of the channel in the triode region [12]andNisthenumberof gatengers. Rch,isnotgivenexplicitlyintheMOSFETmodelsordesigndata,butitcanbeestimatedfromtheMOSFETmodelsusing:Rch, =1IDSVDSVDS=0WL=1nCox(VGSVth). (4.5)Since VGSvaries with the oscillation voltage, the resistance of the channel will not beconstant. InordertoobtainanestimateforRch,,VGSVthcanbesettoVDD2.Duringthetankcircuitdesignphase, Equation4.4wassimplyusedasaguideline.ThegateresistancewasestimatedtoensurethatthedesignledtoareasonableQ.SinceRch, Rpoly,,Equation4.4indicatesthatLshouldbeminimizedtoreducethe series resistance. For this reason the process minimum channel length was utilized.On the other hand, using the minimum channel width would result in a device with anexcessive number of ngers with large associated parasitic capacitances, compromisingthe tuning range. In addition, for small devices, the series resistance will be dominatedby the contact resistances, since small devices can only support a single contact ratherthan the preferred larger array of contacts [47]. Consequently, the MOS varactors fortheVCOdesignwererealizedusingtheminimumgatelengthallowedintheprocess(0.35m). Thewidthof eachchannel waschosentobe3.3m, whichrepresentsacompromisebetweenqualityfactor, varactorsize, andparasitics. Eachofthetwoseries varactors consists of 4 parallel devices with 40 ngers each (Fig 4.4). Therefore,the overall device is a 160 nger transistor, with W= 3.3m and L = 0.35m. UsingEquation4.1, CMAXwouldequal approximately0.84pF; however, theoverlapand61controlV+ V-VddFigure 4.4: Varactor implementation schematic.fringingeectsoneachngercausetheactual capacitancetobeabout30percentlarger. Figure4.5showsthelayoutofthevaractoralongwithadetailedviewofthegateandcontactarrangement. Noticethatthegatepolysiliconiscontactedoneachendof thedevice. Alsonoticethatinordertofurtherreducetheresistanceof thepolysiliconcontactstworowsofcontactsareused. Thecontactsareplacedasclosetogether as possible. Intheavailableprocess (andmanyother sub-micronsiliconprocesses), viasandcontactsmayonlybeofaxedsizeandmustbeseparatedbyminimumdistance. The3.3mchannel widthdoesincreasethegateresistanceofeachdevice,butthewiderdeviceallowstheplacementof4diusioncontactsonthesourceanddrainofeachnger. Theentirestructureisplacedinacommonn-well,and n+ ohmic bulk contacts connect the n-well to VDDbetween each 40-nger-sectionof thevaractor. Thecontrol voltageandthen-well biasenterthestructureinthecenteronthersttwometallevels;thetankcircuitisconnectedontheouteredgesbymetal2ngersthatrundowneachrowofpolycontacts.Figure4.7showsaplotof thesimulatedtotal varactorcapacitance(i.e. theseriescombinationofFig. 4.3)versusthecontrol voltage. ThisC-VcurvewasgeneratedusingatransientsimulationinSpectre. A2.5GHz, 10mVsignal wasappliedacrossthevaractorandthedisplacementcurrent4throughthedevicewasmeasured(Fig.4Because the BSIM3v3 models do not model the gate resistance or the channel resistance (when62Figure 4.5: Varactor layout with detailed view of gate and contact arrangement. Contactsare shown as solid black squares in the various regions.63Tuning Voltage10 mV 2.5 GHz+1.65 VRFC RFC RFCVDD=3.3 VFigure 4.6: Circuitusedtomeasuretotal tankcircuitvaractorcapacitanceversustuningvoltage.4.6). The DC voltage at the gates of the varactor is set toVDD2= 1.65 since this is closetotheactual DCoperatingvoltageatthetankcircuitnodesinthecomplementaryGMoscillator (seeSect. 2.2). Thetuningvoltagewas variedover anumber ofsimulationrunsandthecapacitancewascalculatedfromthedisplacementcurrentthroughthevaractorsforeachrun.TherelevantcontactandsheetresistancesnecessarytocalculatetheQofthisstruc-ture are given in Table 4.1. Rch, was calculated by doing a DC sweep in simulation,since short channel devices deviate somewhat from Equation 4.5. Using VGS= 1.65Vfor simplicity,Rch, 57000,(quite large,but recall that this is the resistance of theverythininversionlayerofthedeviceatVDS=0). VGS=VDD2waschosensinceitrepresentsanaverageoperatingpointforthevaractor. DuringactualoperationVGSwill swingbetweenVGS=0andVGS=VDDoveranoscillationcycle. Thiscausesthevaractortooperateinbothstrongandweakinversion. UsingEquation4.4forthedrainandsourceareshorted) it is assumedthat thecurrent intothegateterminal of thevaractors is in quadrature with the applied voltage (i.e. the device appears purely capacitive). Thusthe capacitance is easily calculated as the ratioC =12f|I||V |.64Figure 4.7: Simulated total tank circuit varactor capacitance versus tuning voltageTable 4.1: Sheet and contact resistances for a 0.35m processRpoly,6.3RP+,2.6RMetal1,0.07RM1Poly4.7RM1P+4.1RM1M21.465eachvaractor, Rswascalculatedtobe3.18. Consideringthetotal tankvaractor,thetotalseriesresistancewouldbe6.36. FromFigure4.7thevaractorcapacitancevariesfrom0.223pFto0.558pF. If thetuningrangeextendsfrom2.3GHzto2.8GHz(aswas expectedfromsimulations), Equation4.2predictsthat theQof thevaractorwillvaryfrom19.5to40.1,respectively.4.4 Large-SignalEectsAs was stated earlier the oscillator responds to the averagecapacitance rather than totheexactvalueontheDCC-Vcurve. SincetheACvoltageacrossthevaractors(ina GMoscillator, Fig. 2.5) will be large relative to the voltage required to transitionfromCmintoCmaxthetuningcurveof theVCOwill besignicantlymorelinearthan the small-signal (DC) C-V plot of the varactors themselves. Furthermore, largertank voltages will result in more smoothing and the tuning curve will become morelinear. For very small tank amplitudes the tuning curve becomes more nonlinear andapproaches the shape of the small signal C-V curve in the limit as the tank amplitudeapproaches zero (for this reason the C-V curve of Figure 4.7 was measured using a 10mV sig