Final report-Third part.pdf

1

DESIGN OF 2x2 NETWORK ON CHIP USING SYNCHRONOUS T-ROUTER

Part - III

LIBRARY DOCUMENTATION

Under the guidance of

Erik Brunvand Associate Professor

School of Computing University of Utah

Submitted by

Group 13 Manikanth Miryala Rajasekhar Vazrala

Nikhita

2

Contents 1. INV ....................................................................................................................................................... 6

i) Schematic .......................................................................................................................................... 6

ii) Symbol .............................................................................................................................................. 6

iii) Behavioral model .......................................................................................................................... 7

iv) Layout view .................................................................................................................................. 7

v) Timing data ....................................................................................................................................... 8

2. INV4X .................................................................................................................................................. 9

i) Schematic View ................................................................................................................................ 9

ii) Symbol view ..................................................................................................................................... 9

iii) Behavioral model ........................................................................................................................ 10

iv) Layout view ................................................................................................................................ 10

v) Timing data ..................................................................................................................................... 11

3. INV8X ................................................................................................................................................ 12

i) Schematic view ............................................................................................................................... 12

ii) Symbol ............................................................................................................................................ 12


iv) Layout view ................................................................................................................................ 13

v) Timing data ..................................................................................................................................... 14

4. NAND2 ............................................................................................................................................... 15

i) Schematic view ............................................................................................................................... 15

ii) Symbol view ................................................................................................................................... 15

iii) Behavioral view .......................................................................................................................... 16

iv) Layout view ................................................................................................................................ 16

v) Timing data ..................................................................................................................................... 17

5. NANDX2 ............................................................................................................................................ 18

i) Schematic view ............................................................................................................................... 18

ii) Symbol view ................................................................................................................................... 18


iv) Layout view ................................................................................................................................ 19

v) Timing data ..................................................................................................................................... 20

6. NAND3 ............................................................................................................................................... 21

i) Schematic view ............................................................................................................................... 21

ii) Symbol view ................................................................................................................................... 21


3

iv) Layout view ................................................................................................................................ 22

v) Timing data ..................................................................................................................................... 23

7. NOR2 .................................................................................................................................................. 24

i) Schematic view ............................................................................................................................... 24

ii) Symbol view ................................................................................................................................... 24


iv) Layout view ................................................................................................................................ 25

v) Timing data ..................................................................................................................................... 26

8. NORX2 ............................................................................................................................................... 27

i) Schematic view ............................................................................................................................... 27

ii) Symbol view ................................................................................................................................... 27


iv) Layout view ................................................................................................................................ 28

v) Timing data ..................................................................................................................................... 29

9. NOR3 .................................................................................................................................................. 30

i) Schematic view ............................................................................................................................... 30

ii) Symbol view ................................................................................................................................... 30


iv) Layout view ................................................................................................................................ 31

v) Timing data ..................................................................................................................................... 32

10. XOR2 .............................................................................................................................................. 33

i) Schematic view ............................................................................................................................... 33

ii) Symbol view ................................................................................................................................... 33


iv) Layout view ................................................................................................................................ 34

v) Timing data ..................................................................................................................................... 35

11. AOI22 ............................................................................................................................................. 36

i) Schematic view ............................................................................................................................... 36

ii) Symbol view ................................................................................................................................... 36

iii) Behavioral view .......................................................................................................................... 37

iv) Layout view ................................................................................................................................ 37

v) Timing data ..................................................................................................................................... 38

12. OAI22 ............................................................................................................................................. 39

i) Schematic view ............................................................................................................................... 39

ii) Symbol view ................................................................................................................................... 39

4


iv) Layout view ................................................................................................................................ 40

v) Timing data ..................................................................................................................................... 41

13. DFF ................................................................................................................................................. 42

i) User’s guide .................................................................................................................................... 42

ii) Schematic view ............................................................................................................................... 43

iii) Symbol view ............................................................................................................................... 43

iv) Behavioral model ........................................................................................................................ 44

v) Layout view .................................................................................................................................... 44

vi) Timing data ................................................................................................................................. 45

14. LATCH1BIT ................................................................................................................................... 46

i) User’s guide .................................................................................................................................... 46


iii) Symbol view ............................................................................................................................... 47


v) Layout view .................................................................................................................................... 48

vi) Timing data ................................................................................................................................. 49

15. REG1BIT ........................................................................................................................................ 50

i) User’s guide: ................................................................................................................................... 50


iii) Symbol view ............................................................................................................................... 51

iv) Behavioral view .......................................................................................................................... 52

v) Layout view .................................................................................................................................... 52

vi) Timing data ................................................................................................................................. 53

16. MUX2BY1TEST ............................................................................................................................ 54

i) Schematic view ............................................................................................................................... 54

ii) Symbol view ................................................................................................................................... 54


iv) Layout view ................................................................................................................................ 55

v) Timing data ..................................................................................................................................... 56

17. TRISTATE_INVERTER ................................................................................................................ 57

i) User’s guide: ................................................................................................................................... 57


iii) Symbol view ............................................................................................................................... 58


5

v) Layout view .................................................................................................................................... 59

vi) Timing data ................................................................................................................................. 60

18. BUFFER2X ..................................................................................................................................... 61

i) Schematic view ............................................................................................................................... 61

ii) Symbol view ................................................................................................................................... 61


iv) Layout view ................................................................................................................................ 62

v) Timing data ..................................................................................................................................... 63

19. BUFFER4X ..................................................................................................................................... 64

i) Schematic view ............................................................................................................................... 64

ii) Symbol view ................................................................................................................................... 64


iv) Layout view ................................................................................................................................ 65

v) Timing data ..................................................................................................................................... 66

20. BUFFER8X ..................................................................................................................................... 67

i) Schematic view ............................................................................................................................... 67

ii) Symbol view ................................................................................................................................... 67


iv) Layout view ................................................................................................................................ 68

v) Timing data ..................................................................................................................................... 69

21. FILLER_CELL ............................................................................................................................... 70

i) Layout view .................................................................................................................................... 70

22. FILL4 .............................................................................................................................................. 71

i) Layout view .................................................................................................................................... 71

23. FILL8 .............................................................................................................................................. 72

i) Layout view .................................................................................................................................... 72

24. TIEHI .............................................................................................................................................. 73

i) Schematic view ............................................................................................................................... 73

ii) Symbol view ................................................................................................................................... 73

iii) Layout view ................................................................................................................................ 74

25. TIELO ............................................................................................................................................. 75

i) Schematic view ............................................................................................................................... 75

ii) Symbol view ................................................................................................................................... 75

iii) Layout view ................................................................................................................................ 76

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1. INV This is a basic inverter cell with output as Y and input as A. Y = A� i) Schematic

Fig., 1.1

ii) Symbol

7

Fig., 1.2 iii) Behavioral model

iv) Layout view

Fig., 1.3

8

v) Timing data

With respect to output Y

For Input slope = 0.42 ns and Output net capacitance (fan out load) = 0.3 pf

RELATED PIN

CELL RISE

CELL FALL

RISE TRANSITION

FALL TRANSITION

A 2.14 2.88 1.84 2.39

9

2. INV4X This cell performs the basic function of an inverter but has a drive strength of four times that of normal inverter.

Y = A� i) Schematic View

Fig., 2.1 ii) Symbol view

Fig., 2.2

10

iii) Behavioral model

iv) Layout view

Fig., 2.

11

v) Timing data



RELATED PIN

CELL RISE

CELL FALL

RISE TRANSITION

FALL TRANSITION

A 0.76 0.95 0.49 0.62

12

3. INV8X This is an inverter with 8 times the drive strength of basic inverter cell.

Y = A�

i) Schematic view

Fig., 3.1

ii) Symbol

Fig., 3.2

13


iv) Layout view

Fig., 3

14

v) Timing data



RELATED PIN

CELL RISE

CELL FALL

RISE TRANSITION

FALL TRANSITION

A 0.53 0.63 0.30 0.35

15

4. NAND2 This cell performs the function of a two-input NAND gate.

Y = A. B��

i) Schematic view

Fig., 4.1

ii) Symbol view

Fig., 4.2

16

iii) Behavioral view

iv) Layout view

Fig., 4.3

17

v) Timing data



RELATED PIN

CELL RISE

CELL FALL

RISE TRANSITION

FALL TRANSITION

A 2.17 1.78 1.85 1.49

18

5. NANDX2 This cell performs logical NAND and has a drive strength twice that of a basic 2-input NAND.

Y = A. B�� i) Schematic view

Fig., 5.1

ii) Symbol view

Fig., 5.2

19


iv) Layout view

Fig., 5.4

20

v) Timing data



Units - ns

RELATED PIN

CELL RISE

CELL FALL

RISE TRANSITION

FALL TRANSITION

A 2.17 1.79 1.85 1.49

21

6. NAND3 This is a 3-input NAND gate.

Y = A. B. C�� i) Schematic view

Fig., 6.1

ii) Symbol view

Fig., 6.2

22


iv) Layout view

Fig., 6.3

23

v) Timing data



Units - ns

RELATED PIN

CELL RISE

CELL FALL

RISE TRANSITION

FALL TRANSITION

A 2.32 1.50 1.99 1.32

B 2.27 1.53 1.94 1.32

24

7. NOR2 This is a 2-input NOR gate with A, B as inputs and output as Y.

Y = A + B�� i) Schematic view

Fig., 7.1

ii) Symbol view

Fig., 7.3

25


iv) Layout view

Fig., 7.3

26

v) Timing data



Units - ns

RELATED PIN

CELL RISE

CELL FALL

RISE TRANSITION

FALL TRANSITION

A 1.85 3.04 1.62 2.51

27

8. NORX2 This cell performs 2-input logical NOR and has a drive strength of twice that of a basic 2-input NOR cell. Y = A + B��

i) Schematic view

Fig., 8.1

ii) Symbol view

Fig., 8.2

28


iv) Layout view

Fig., 8.3

29

v) Timing data



Units - ns

RELATED PIN

CELL RISE

CELL FALL

RISE TRANSITION

FALL TRANSITION

A 1.85 3.05 1.62 2.51

30

9. NOR3 This a 3-input NOR gate with A, B, C as input and Y as output.

Y = A + B + C��

i) Schematic view

Fig., 9.1

ii) Symbol view

Fig., 9.2

31


iv) Layout view

Fig., 9.3

32

v) Timing data



RELATED PIN

CELL RISE

CELL FALL

RISE TRANSITION

FALL TRANSITION

A 1.83 3.31 1.61 2.71

B 1.84 3.18 1.61 2.58

33

10. XOR2 This is a 2-input XOR gate with A, B as inputs and Y as output. Y = A�. B + A. B�

i) Schematic view

Fig., 10.1

ii) Symbol view

Fig., 10.1

34


iv) Layout view

Fig., 10.3

35

v) Timing data



Units - ns

RELATED PIN

CELL RISE

CELL FALL

RISE TRANSITION

FALL TRANSITION

A 2.14 2.11 1.64 1.61

36

11. AOI22 This is a 2-input AND-OR-INVERTER with 4 inputs, A, B, C, D and one output Y.

Y = A. B + C. D��

i) Schematic view

Fig., 11.1 ii) Symbol view

Fig., 11.2

37

iii) Behavioral view

iv) Layout view

Fig., 11.3

38

v) Timing data



Units - ns

RELATED PIN

CELL RISE

CELL FALL

RISE TRANSITION

FALL TRANSITION

A 1.74 1.96 1.47 1.64

D 1.49 1.82 1.49 1.54

39

12. OAI22 This is a 2-input OR-AND-INVERTER with A, B, C, D as inputs and Y as output.

Y = (A + B). (C + D)�� i) Schematic view

Fig., 12.1

ii) Symbol view

Fig., 12.2

40


iv) Layout view

Fig., 12.

41

v) Timing data



Units - ns

RELATED PIN

CELL RISE

CELL FALL

RISE TRANSITION

FALL TRANSITION

A 1.89 1.75 1.66 1.42

D 1.97 1.71 1.73 1.39

42

13. DFF This is a positive edge triggered, asynchronous active low reset, D flip-flop with Master and Slave circuits. Both these circuits constitute transmission gate, tristate inverter, a basic inverter and a 2-input NAND gate. Clock (CLK) and CLK_BAR (reset) signals are produced from two inverters as shown in the schematic. Q and Q_BAR are the outputs.

i) User’s guide

a) Truth table

CLK CLR_BAR D Q Q_BAR 0 1 0 x x 1 1 0 0 1 0 1 1 0 1(prev.

state) 1 1 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 1 0 1 0 1

b) Timing diagram:

Fig., 13.1

43

ii) Schematic view

Fig., 12.1

iii) Symbol view

Fig., 12.2

44

iv) Behavioral model

v) Layout view

Fig., 12.3

45

vi) Timing data

With respect to CLK


Units - ns

RELATED PIN

HOLD RISE

HOLD FALL

SETUP RISE

SETUP FALL

D 0.097 0.378 0.09 0.146

46

14. LATCH1BIT This is a 1-bit positive level-triggered, asynchronous active low reset latch circuit with D input and Q output. It uses the circuit parts of slave D-flip-flop (cell 13). The clock (CLK) signal of this circuit will be connected to the main CLK of the entire system being designed. This cell was custom designed to be used in elastic half buffer for our project.

i) User’s guide

a) Truth table

CLK CLR_BAR D Q 1 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1(prev.

state) 1 1 0 0 0 1 1 0(prev.

state) 1 1 1 1 0 1 0 1(prev.

state)

b) Timing diagram:

Fig., 14.1

47

ii) Schematic view

Fig., 14.1

iii) Symbol view

Fig., 14.2

48


v) Layout view

Fig., 14.3

49

vi) Timing data

With respect to CLK


Units - ns

RELATED PIN

HOLD RISE

HOLD FALL

SETUP RISE

SETUP FALL

D -0.07 -0.015 0.20 0.146

50

15. REG1BIT This is a positive level triggered 1-bit latch circuit with no reset signal as in LATCH1BIT cell described earlier and is designed to as a data register in this project. The circuit parts of this cell are analogous to those in the master D-flip-flop with the only difference of rest signal. This cell behaves as a latch with enable signal (represented here as CLK) and is connected to internal signals in the system according to requirement and NOT the system CLK.

i) User’s guide:

c) Truth table

CLK D Q 0 0 X 0 1 X 1 0 0 1 1 1 0 0 1(prev.

state) 0 1 1(prev.

state)

d) Timing diagram:

Fig., 15.1

51

ii) Schematic view

Fig., 15.2

iii) Symbol view

Fig., 15.3

52

iv) Behavioral view

v) Layout view

Fig., 15.4

53

vi) Timing data

With respect to CLK


Units - ns

RELATED PIN

HOLD RISE

HOLD FALL

SETUP RISE

SETUP FALL

D -0.24 0.04 0.315 0.09

54

16. MUX2BY1TEST This cell performs the function of a 2-input multiplexer with data inputs A, B and select input C. Y is the output. This circuit is designed using transmission gates to obtain minimal cell area as the number of transistors is only four.

Y = C� . A + C. B

i) Schematic view

Fig., 16.2

ii) Symbol view

Fig., 16.3

55


iv) Layout view

Fig., 16.4

56

v) Timing data



Units - ns

RELATED PIN

CELL RISE

CELL FALL

RISE TRANSITION

FALL TRANSITION

A 1.66 1.88 1.63 1.93

57

17. TRISTATE_INVERTER This cell acts as a basic inverter and drives the input based CLKN and CLKP inputs which are complements of each other.

Y = A� i) User’s guide:

a) Truth table

CLKN CLKP A Y 1 0 0 Z 1 0 1 Z 0 1 0 1 0 1 1 0

b) Timing diagram

Fig., 17.1

58

ii) Schematic view

Fig., 17.2

iii) Symbol view

Fig., 17.3

59


v) Layout view

Fig., 17.4

60

vi) Timing data



Units - ns

RELATED PIN

CELL RISE

CELL FALL

RISE TRANSITION

FALL TRANSITION

A 1.87 1.84 1.67 1.56

61

18. BUFFER2X This cell is designed to use in this project and serves the purpose of clock skew reduction. It uses two inverters, the second one having twice the drive strength of the first one.

Y = A

i) Schematic view

Fig., 18.1

ii) Symbol view

Fig., 18.2

62


iv) Layout view

Fig., 18.3

63

v) Timing data



Units - ns

RELATED PIN

CELL RISE

CELL FALL

RISE TRANSITION

FALL TRANSITION

A 1.45 1.76 0.93 1.20

64

19. BUFFER4X This cell performs the same function as BUFFER2X cell but with a greater drive strength. As the name suggests, the drive strength of the second inverter is four times the basic inverter cell.

Y = A

i) Schematic view

Fig., 19.1

ii) Symbol view

Fig., 19.2

65


iv) Layout view

Fig., 19.3

66

v) Timing data



Units - ns

RELATED PIN

CELL RISE

CELL FALL

RISE TRANSITION

FALL TRANSITION

A 1.44 1.25 0.52 0.64

67

20. BUFFER8X This cell performs the same function as BUFFER2X cell but with a greater drive strength. As the name suggests, the drive strength of the second inverter is eight times the basic inverter cell.

Y = A

i) Schematic view

Fig., 20.1

ii) Symbol view

Fig., 20.2

68


iv) Layout view

Fig., 20.3

69

v) Timing data



Units - ns

RELATED PIN

CELL RISE

CELL FALL

RISE TRANSITION

FALL TRANSITION

A 0.88 0.91 0.31 0.36

70

21. FILLER_CELL i) Layout view

Fig., 21.1

71

22. FILL4 i) Layout view

Fig., 22.1

72

23. FILL8

i) Layout view

Fig., 23.1

73

24. TIEHI This cell, when connected to an output, always ties it to logic 1 or HIGH state and hence the name.

Y =1

i) Schematic view

Fig., 24.1

ii) Symbol view

Fig., 24.2

74

iii) Layout view

Fig., 24.3

75

25. TIELO This cell, when connected to an output, always ties it to logic 1 or HIGH state and hence the name.

Y =0

i) Schematic view

Fig., 25.1

ii) Symbol view

Fig., 25.2

76

iii) Layout view

Fig., 26.3

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