DESCRIPTION OF FINAL REPORT FOR OUR TERM PAPER

EGCP 542 VLSI TESTING AND DESIGN FOR TESTABILITY

Low Transition LFSR for BIST based applications Authors: Mehrdad Nourani, Mohammad Tehranipoor, Meh, Nisar Ahmed

Tejasri Saladi 802725481

INTRODUCTION

There are many challenging issues faced by DFT engineers like test cost, yield, Power dissipation and quality while designing and testing the circuits. Among these, Power Dissipation is one of the major challenging problems in designing and testing the system-on-chip circuits. Moreover, power dissipation is higher in test mode than in normal mode. Consecutive vectors are connected by a significant correlation in normal mode while in test mode this does not exist. In test mode the correlation between vectors is low and because of this, there is an increase in switching activity of circuit which leads to power dissipation. Due to the power dissipation problem, various issues are caused like formation of hot spots, circuit damage, decrease in yield and performance of circuit. All these problems seen while testing the circuits motivated us to select this paper and our main objective is to reduce the average and peak power of these circuits while testing.

BIST is one of the most promising methodology providing solution for testing problems. Generally speaking, BIST is a technique which detects fault components with test logic built on the chip itself. LFSR is generally shift register, which has input with function as its previous state value. LFSR has good advantage of being used in BIST as well as scan-based BIST applications. The test patterns generated by LFSR are random and increase the switching activity. To reduce this problem, this paper proposes new method of test pattern generator called Low Transition linear feedback shift register (LT-LFSR). In LT-LFSR, transitions are reduced between consecutive patterns while testing. For this approach, two methods called Bipartite LFSR (Half-fixed strategy) and RI method (Random injection) are combined and embed together into LFSR which proposes our method reducing the total number of transitions.

As discussed in class, LFSR produces patterns algorithmically. It has most of desirable random number properties. For good fault coverage we need long sequences. Coming to BIST, it benefits with lower system test effort and better diagnosis. It reduces the testing and maintenance cost. It can also test at functional system speed. Also, LT-LFSR has unique aspects of reducing power dissipation and flexible to be used for BIST based applications.

DESCRIPTION OF OUR PAPER

Random patterns generated by LFSR are low correlated. This paper proposes LT-LFSR technique which uses two methods called Bipartite and RI method. To understand the concept of each of these methods the author considered two consecutive patterns T i and Ti+1 generated by LFSR consisting of n bits.

Generally there will be maximum of n transitions if T i and Ti+1 are complement to one another. Bipartite or half-fixed strategy reduces the number of transitions to n/2 where an inserted pattern Ti1 is placed in between Ti and Ti+1. The inserted pattern Ti1 is half identical to Ti and other half to Ti+1.

Fig1. (a) Pattern insertion based on Bipartite LFSR.

(b) Bipartite LFSR technique.

For the bipartite LFSR architecture, two non-overlapping signals en1 and en2 are present. If en1en2=10 then first half of LFSR works and other would be in idle mode. When en1en2=01, second half works. In order to store the n/2 th bit when en1en2=10 and send it to (n/2 th+1) output a shaded flip-flop is added and in this way an experimental analysis was done for 16 bit LFSR reducing the number of transitions.

In case of RI method, in order to preserve the randomness, a random value is injected in between two consecutive patterns if they both are complement to each other. To verify the randomness of the RI method in this paper it was tested with 20 bit LFSR.

Fig 2. Pattern insertion based on RI method.

Combining these two methods, LT-LFSR architecture was built reducing the transitions as possible as to n/4.

Worst case: Ni.i1trans= 0, Ni1, i+1

trans= n (or vice-versa)

Best case : Ni,i1trans= Ni,i+1

trans= n/2

Fig 3. Proposed LT-LFSR architecture

The architecture comprises of Bipartite LFSR and RI LFSR. In this proposed architecture, an external XOR LFSR is used. Random injector circuit taps present T i pattern and the next consecutive Ti+1 pattern of LFSR. Signals en1 and en2 select half of LFSR generating random patterns. The RI method consists of multiplexers which select either random bit or excess bit. The architecture also comprises of FSM which mainly controls the pattern generation. The test pattern generally proceeds in five steps. In the first step en1en2=10 and s1s2=11 where first half works and other stays in idle mode and sent to the outputs O1 to On generating T i. In the next step, en1en2=0 and s1s2=10 with both halves in idle mode with outputs sent to O1 and On/2 and On/2+1 to On generating the Ti1 pattern. In en1en2=01 and s1s2=11 second half LFSR works and Ti2pattern is generated. Ti3is generated when en1en2=00 and s1s2=01 then modes will be in idle mode. This process thereby continues to generate Ti+1.

This is how the author highlights the paper by describing the architecture of LT-LFSR by combining and utilizing the prominence of both techniques of bipartite and RI methods. This

point is supported adequately by successful experimental calculation of transitions shown in graph Fig.4 plotting the distribution of number of transitions in LT-LFSR.

Fig 4. Distribution of transitions between consecutive patterns in LT-LFSR.

There were no concerns on proposed architecture in this paper as every single detail was given by the author including the experimental results which confirm up to 77% and 49% reduction in average and peak power.

CONCLUSION

Concluding this report, we thus expected to learn how low transition LFSR reduces the average and peak power while testing the circuits. We have therefore ended up learning this, by studying about the bipartite and RI methods and embed them into single LFSR reducing the overall transitions. In our point of view, this is a very good paper which helped us to study more about the LFSR and BIST based applications which are useful in the reduction of average and peak powers of circuits in test mode. Hope this architecture of LT-LFSR would help the test engineers in future which helps in verifying the performance of circuits.

REFERENCES

Most of our reference was from our paper, “Low transition LFSR for BIST based applications” mentioned in reference 1.

[1] N. Ahmed, M. Tehranipoor and M. Nourani, ‘Low transition LFSR for BIST based applications,’ in Proc. Int. Symp. on Circuits and Systems (ISCAS’04), vol. 3, pp. 689-692, 2004.

[2] N. Ahmed, M. Tehranipoor and M. Nourani, ‘Low Power Pattern Generation for BIST Architecture,’ in Proc. Int. Symp. on Circuits and Systems (ISCAS’04), vol. 2, pp. 689-692, 2004.

[3] P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, H. -J. Wunderlich,”A modified Clock Scheme for a Low Power BIST Test Pattern Generator,” in Proc. VLSI Test Symp. (VTS’01), pp. 306-311, 2001.