Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke...
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Transcript of Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke...
![Page 1: Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke Instructor Mony Orbach Duration Single Semester.](https://reader035.fdocuments.in/reader035/viewer/2022070410/56649f2b5503460f94c45b56/html5/thumbnails/1.jpg)
Project overview. Card Spec’s. Hardware:
◦ Block Diagram of the Card.◦ Circuit diagram of the card.
Interface between the Analog card and the DE2. Software: DE2 functions
![Page 2: Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke Instructor Mony Orbach Duration Single Semester.](https://reader035.fdocuments.in/reader035/viewer/2022070410/56649f2b5503460f94c45b56/html5/thumbnails/2.jpg)
What is in the lab today?closed lab experiment consisting of only an 12 bit A/D and
a sample and hold.
What are the new features in our project? 8 bit A/D converter (less sensitive to digital noise) D/A converter. DE2 board
Our card will allow the students to process the digital signal and observe its effects on the reconstructed signal.
![Page 3: Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke Instructor Mony Orbach Duration Single Semester.](https://reader035.fdocuments.in/reader035/viewer/2022070410/56649f2b5503460f94c45b56/html5/thumbnails/3.jpg)
Design and produce a Prototype card that has on it:1. a sampler (plus an A/D) 2. a reconstructing unit (D/A).
External digital signal processing using the DE2 card.
Protect the card from users accidentally damaging it.
![Page 4: Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke Instructor Mony Orbach Duration Single Semester.](https://reader035.fdocuments.in/reader035/viewer/2022070410/56649f2b5503460f94c45b56/html5/thumbnails/4.jpg)
Design of a board for the new laboratory experiment in analog to digital conversion (ADC).
![Page 5: Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke Instructor Mony Orbach Duration Single Semester.](https://reader035.fdocuments.in/reader035/viewer/2022070410/56649f2b5503460f94c45b56/html5/thumbnails/5.jpg)
-10 volt reference voltage for ADC
5 volt voltage regulator+15 volt voltage regulator
-15 volt voltage regulator
![Page 6: Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke Instructor Mony Orbach Duration Single Semester.](https://reader035.fdocuments.in/reader035/viewer/2022070410/56649f2b5503460f94c45b56/html5/thumbnails/6.jpg)
![Page 7: Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke Instructor Mony Orbach Duration Single Semester.](https://reader035.fdocuments.in/reader035/viewer/2022070410/56649f2b5503460f94c45b56/html5/thumbnails/7.jpg)
8 bit digital signal
Buffers & interface
with DE2 or Logic
Analyzer
DE2 / Logic Analyzer
8 bit digital signalAnalog Input
Over voltage
protection+/- 10V
Sample & Hold
Bipolar to Unipolar converter
Unipolar / BipolarSwitch
SampleSwitch ADC
Over voltage
protection0 to +10V
DACUnipolar /
BipolaroutputSwitch
Unipolar to Bipolar
converter
Analog Output
Sort circuit protection
![Page 8: Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke Instructor Mony Orbach Duration Single Semester.](https://reader035.fdocuments.in/reader035/viewer/2022070410/56649f2b5503460f94c45b56/html5/thumbnails/8.jpg)
Clock Input
Over voltage
protection0 to +5V
Clock
nBusy
LogicClock’
8 bit digital signalAnalog Input
Over voltage
protection+/- 10V
Sample & Hold
Bipolar to Unipolar converter
Unipolar / BipolarSwitch
SampleSwitch ADC
Over voltage
protection0 to +10V
![Page 9: Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke Instructor Mony Orbach Duration Single Semester.](https://reader035.fdocuments.in/reader035/viewer/2022070410/56649f2b5503460f94c45b56/html5/thumbnails/9.jpg)
Opcode (supplied directly to the DE2 by user):◦ 8 bit – will determine the signal processing that is applied on the digital input.
Input:◦ 8 bit digital input from the card of the sampled and converted input signal.
Output:◦ 8 bit digital output of the processed signal to the card.
Data ready signal:◦ Card Clock’ is input into the DE2 from the card and acts as a signal telling the DE2 when the input is valid.
Clock output:◦ This feature allows the DE2 to control the DAC
rate of conversion.
![Page 10: Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke Instructor Mony Orbach Duration Single Semester.](https://reader035.fdocuments.in/reader035/viewer/2022070410/56649f2b5503460f94c45b56/html5/thumbnails/10.jpg)
Analog card
Register level DE2 inputs
DE2 outputs
סכימה גלובלית
![Page 11: Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke Instructor Mony Orbach Duration Single Semester.](https://reader035.fdocuments.in/reader035/viewer/2022070410/56649f2b5503460f94c45b56/html5/thumbnails/11.jpg)
קצת על הכרטיס
LEDs
switches
Buttons
FPGA
Power Supply
USB Blaster Clock
(27 MHz)Expansion Header
![Page 12: Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke Instructor Mony Orbach Duration Single Semester.](https://reader035.fdocuments.in/reader035/viewer/2022070410/56649f2b5503460f94c45b56/html5/thumbnails/12.jpg)
דיאגרמת בלוקים
![Page 13: Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke Instructor Mony Orbach Duration Single Semester.](https://reader035.fdocuments.in/reader035/viewer/2022070410/56649f2b5503460f94c45b56/html5/thumbnails/13.jpg)
פונקציות שמומשו על הכרטיס
Div by 2
saturateDelay
(pass the signal)
First-order hold
![Page 14: Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke Instructor Mony Orbach Duration Single Semester.](https://reader035.fdocuments.in/reader035/viewer/2022070410/56649f2b5503460f94c45b56/html5/thumbnails/14.jpg)
0 100 200 300 400 500 600 700 800 900 1000
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
input
output
0 100 200 300 400 500 600 700 800 900 1000
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
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1
input
output
0 100 200 300 400 500 600 700 800 900 1000
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
input
output
Div by 2Delay (pass the signal)saturate
0 100 200 300 400 500 600 700 800 900 1000
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
input
output
First-order hold
![Page 15: Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke Instructor Mony Orbach Duration Single Semester.](https://reader035.fdocuments.in/reader035/viewer/2022070410/56649f2b5503460f94c45b56/html5/thumbnails/15.jpg)
כניסות ויציאות של הכרטיס
interface
:כניסות לכרטיסInput data: 8 bitsControl from the card : 2 bitsInput control : 1 bit (unipolar / bipolar)
יציאות מהכרטיס : Output data: 8 bitsControl : 1bit (unipolar / bipolar)Clk : 1 bit (27 MHz)
![Page 16: Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke Instructor Mony Orbach Duration Single Semester.](https://reader035.fdocuments.in/reader035/viewer/2022070410/56649f2b5503460f94c45b56/html5/thumbnails/16.jpg)
ספציפיקציות
Inputs and outputs specifications : 3.3 -V LVTTL
Provided voltage : 5 V and 3.3 V
: הכרטיס נבדק ע"י התוכנות הבאות Quartus 7.2Modelsim 5.8b
![Page 17: Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke Instructor Mony Orbach Duration Single Semester.](https://reader035.fdocuments.in/reader035/viewer/2022070410/56649f2b5503460f94c45b56/html5/thumbnails/17.jpg)
ניצול משאבי הכרטיס(quartus results)
Logic elements : 388/33216 (1 %)
Registers : 128/33216 ( <1 %)
Total pins : 48/475 ( 10% )
Total Memory bits : 4096/483840 (< 1% )
DSP 9x9 : 0/70 ( 0%)
PLLs : 0/4 ( 0% )
![Page 18: Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke Instructor Mony Orbach Duration Single Semester.](https://reader035.fdocuments.in/reader035/viewer/2022070410/56649f2b5503460f94c45b56/html5/thumbnails/18.jpg)
כמו להרוג זבוב בעזרת טיל
![Page 19: Final Presentation Winter 2007-8 Final Presentation Winter 2007-8 Students Naftali Weiss Nadav Melke Instructor Mony Orbach Duration Single Semester.](https://reader035.fdocuments.in/reader035/viewer/2022070410/56649f2b5503460f94c45b56/html5/thumbnails/19.jpg)
שאלות
???????