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FP7-ICT-2011-7 – 288827 – CP IP DELIVERABLE D3.2.2

SMAC SMArt systems Co-design

FP7-ICT-2011-7 – 288827 – CP IP

D3.2.2 Final Multi-Level Models for Digital Components and Subsystems

Public Summary Due date of deliverable: June 2014

Start date of project: 1 October 2011 Duration: 42 months

Organisation name of lead contractor for this deliverable: EDALAB

Author(s): R. Gillon (ONSEMI), N. Bombieri (EDAL)

Validated by: M. Grosso (STP), G.Gangemi (ST)

Revision: 2.0

Date of Issue: 23-Feb-15

Doc reference: SMAC_D3.2.2_FinalMultiLevMod_R1.0

Work Pack. / Task WP3 / T3.2

Description: (max 5 lines)

Models are essential building blocks of the SMAC platform, which allow hiding implementation details from the lower levels and enable efficient high-level simulations. This document describes how the various model prototypes are implemented, which simulation scenarios are supported, what are features and how they are supported in the SMAC platform.

Nature: P

Dissemination Level: PU Public X

PP Restricted to other programme participants (including the JU)

RE Restricted to a group specified by the consortium (including the JU)

CO Confidential, only for members of the consortium (including the JU)

Copyright 2011-2014 STMicroelectronics S.r.l., ONSemiconductor Belgium BVBA, Keysight Technologies Belgium NV, Coventor Sarl, MunEDA GmbH, EDALab s.r.l. Fondazione Istituto Italiano di Tecnologia, University College Cork, National University of Ireland, Instytut Technologii Elektronowej, Politecnico di Torino, Università degli Studi di Catania, University of Nottingham, Katholieke Universiteit Leuven, Technische Universiteit Eindhoven, Slovak University of Technology Bratislava, STPOLITO S.c.a.r.l ( the SMAC Consortium )

This document and the information contained are the property of the SMAC Consortium and shall not be copied in any form or disclosed to any party outside the Consortium without the written permission of the Project Coordination Committee, as regulated by the SMAC Consortium Agreement.

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This document has been created in the context of the SMAC project. All information is provided “as is” and no guarantee or warranty is given that the information is fit for any particular purpose. The user thereof uses the information at its sole risk and liability. The EU has no liability in respect of this document, which is merely representing the authors' view.


SMAC Public © SMAC Consortium of 48

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Table of Contents

Table of Contents ..................................................................................................................................................... 3

List of Tables ............................................................................................................................................................. 4

List of Figures ........................................................................................................................................................... 5

Glossary ..................................................................................................................................................................... 7

1 Executive Summary ........................................................................................................................................ 8

2 Introduction ....................................................................................................................................................... 9

2.1 Innovations in this deliverable ............................................................................................................ 10 2.2 Contribution toward the SMAC platform ........................................................................................... 11

3 Cycle-accurate digital models .................................................................................................................... 12

4 Transaction-accurate digital models ........................................................................................................ 13

5 Models for Analogue Components in the Digital Event-driven Simulator ...................................... 17

5.1 Target simulation scenarios ................................................................................................................ 17 5.2 General Data-flow and Interfaces ...................................................................................................... 18

5.2.1 Basic two-component waveform-relaxation interface ................................................................. 19 5.2.2 Generalized multi-terminal waveform relaxation interface ......................................................... 20 5.2.3 Velocity-based formulation of the waveform relaxation .............................................................. 21

5.3 Implementation Details ........................................................................................................................ 22 5.4 Summary of Improvements, Features and Limitations ................................................................... 22 5.5 Model Extraction Procedures .............................................................................................................. 24 5.6 Validation Methodology ....................................................................................................................... 25 5.7 Benchmarking and Technical Exploitation Perspectives ................................................................ 28

6 Models to evaluate EMI Emissions from Digital Blocks ...................................................................... 29

6.1 Target simulation scenarios ................................................................................................................ 30 6.2 General Data-flow and Interfaces ...................................................................................................... 32 6.3 Summary of Improvements, Features and Limitations ................................................................... 36 6.4 Model Extraction Procedures .............................................................................................................. 37

6.4.1 Substitution of logic tiles and extraction of the supply network ................................................. 37 6.4.2 Library characterization for the extraction of the decoupling admittance components .......... 38 6.4.3 Evaluating statistical moments of the decoupling admittance at block-level ........................... 39

6.5 Implementation Details ........................................................................................................................ 41 6.5.1 Logic Tile Model ................................................................................................................................ 41 6.5.2 Built-in Decoupling Capacitance Model for logic cells ................................................................ 41

6.6 Validation Results ................................................................................................................................. 43 6.7 Benchmarking and Technical Exploitation Perspectives ................................................................ 44

7 Conclusions .................................................................................................................................................... 45

8 Bibliography .................................................................................................................................................... 46



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List of Tables

Table 1: Revision Control and Change Tracking .................................................. Error! Bookmark not defined.

Table 5: List of input and output quantities to the logic tile model .................................................................... 34



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List of Figures

Figure 1. Simulation levels / design-domain matrix. ........................................................................................... 12

Figure 2: The CA vs. TA model comparison in terms of protocol details ......................................................... 14

Figure 3: The abstraction flow of digital components and sub-systems in the SMAC platform .................... 16

Figure 4: Using waveform relaxation to embed a description of analogue blocks in the digital event-driven simulator .................................................................................................................................................................... 17

Figure 5: Mapping the EMI simulation flow onto the SMAC platform. .............................................................. 18

Figure 6: Detailed view of the waveform-relaxation-based mixed-signal flow. ............................................... 19

Figure 7: Analogue conservative electrical interface .......................................................................................... 20

Figure 8: Schematic of the waveform relaxation interface corresponding to the connection of Figure 7. .. 20

Figure 9: Analogue conservative multi-branch net : N degrees of freedom : 1 voltage, N-1 currents ......... 20

Figure 10: Definition of the N wave quantities allowing to capture the state of the new relaxation interface .................................................................................................................................................................................... 20

Figure 11: Schematic of the waveform relaxation interface for component #1 ............................................... 21

Figure 12: Final formulation of the waveform relaxation interface for one branch of a multi-terminal connection ................................................................................................................................................................. 21

Figure 19: Alternative representations used for validation: (a) conservative electrical connection in the circuit simulator; (b) waveform relaxation interface in the digital simulator; (c) emulation of the relaxation interface in the circuit simulator. ............................................................................................................................. 25

Figure 20: Comparing the waveforms obtained for a voltage pulse from a lossy voltage source to a mismatched resistor by relaxation (curves labelled VHDL) in the digital simulator and by .the emulation of relaxation in the circuit simulator (curves labelled CAD). The x-axis units are normalized time-steps. ...... 26

Figure 21: Comparing the waveforms obtained for a voltage pulse from a lossy voltage source to a diode by relaxation (curves labelled VHDL) in the digital simulator and by .the emulation of relaxation in the circuit simulator (curves labelled CAD). The x-axis units are normalized time-steps. ................................... 26

Figure 22: Comparing the voltage waveforms obtained for an inductor by relaxation (curves labelled VHDL) in the digital simulator and by .the emulation of relaxation in the circuit simulator (curves labelled CAD). The x-axis units are normalized time-steps. ............................................................................................. 27

Figure 23: Comparing the voltage waveforms obtained for a resistor with start connections on both terminals by relaxation (curves labelled VHDL) in the digital simulator and by .the emulation of relaxation in the circuit simulator (curves labelled CAD). The x-axis units are normalized time-steps. ........................ 27

Figure 24: Modelling a logic block as an array of abstract logic tiles : (a) Layout view showing “logic tiles model”; (b) Equivalent circuit. ................................................................................................................................. 29

Figure 25: Mapping the EMI simulation flow onto the SMAC platform. ............................................................ 30

Figure 26: Simulation scenario to evaluate the emission spectrum from digital blocks. ............................... 31

Figure 27: Flow-chart of the final top-level EMI analysis. ................................................................................... 32



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Figure 28: Flow-chart for the construction of the power-supply network model. ............................................ 33

Figure 29: Flow-chart for the construction of the dynamic consumption current waveforms. ....................... 33

Figure 30: Flow-chart for the construction of the dynamic consumption current waveforms. ....................... 34

Figure 31: Concept schematic of the logic tile showing IO pins. ....................................................................... 34

Figure 32 (a) : Original layout; (b) : Abstracted layout with supply nets and logic tiles only. ........................ 37

Figure 33 : Zoom into the core logic area : (a) Original layout; (b) Abstracted layout showing the labelled pins of the logic tiles................................................................................................................................................. 38

Figure 34 : 3D views generated by the PTM resistance extraction tool : (a) Top-side over the left-hand-side edge; (b) Bottom side from the same direction. .......................................................................................... 38

Figure 35: Schematic for the cell-level characterization of decoupling admittance components. ................ 39

Figure 36: Schematic of the logic tile component. ............................................................................................... 41

Figure 37: Generic cell model for the extraction of built-in decoupling capacitance in digital blocks. ......... 42

Figure 38 – Validation of the EMI modelling procedures : (a) Top-level view of the test-vehicle layout; (b) Comparison of simulations and measurements. ................................................................................................. 43



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Glossary

Abbreviation / acronym Description

AMS Analog Mixed Signal

AT Approximately Timed

CA Cycle Accurate

DSP Digital Signal Processor

EM Electromagnetic

EMC Electro-Magnetic Compatibility

EMI Electro-Magnetic Interference

GMR Geometrical Magneto Resistance

HDL Hardware Description Language

IC Integrated Circuit

IP Intellectual Property

LSF Linear Signal Flow

LT Loosely Timed

MEMS Micro-Electro-Mechanical Systems

MR Magneto Resistant

MRI Magnetic Resonance Imaging

MoC Model of Computation

RTL Register Transfer Level

RF Radio Frequency

SDF Synchronous Data Flow

TA Transaction Accurate

TEM Transverse Electro-Magnetic

TDF Timed Data Flow

TLM Transaction Level Modelling

TSDF Timed Synchronous Data Flow

VHDL Very high speed integrated circuit Hardware Description Language

WBAN Wireless Body Area Network



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1 Executive Summary

This deliverable is the final result of Task T3.2: Digital components and subsystems (Start: M4 – End: M33) where the participants under the leadership of EDAL are ONSemi, POLITO, UNOTT, and ITE.

The general objective of WP3 is to create and build the models that make the design and optimization of Smart Systems far more efficient, by enabling multi-domain simulations at various abstraction levels for the variety of devices found in this kind of systems. The models are built according to the requirements emanating from WP1. Overall, in the WP3, the following key dimensions have been considered: (1) The physical domains which must be covered by the models (e.g., electrical, thermal, mechanical) and the types of devices (e.g., analog IC, digital IC, sensor, MEMS, power source). (2) The type of interaction envisioned for the multi-domain simulation. (3) The level of detail (abstraction level) ensured by the model. (4) The constraints and the resources related to the physical domains and to the simulation infrastructure.

This deliverable addresses the topic of component and subsystem modeling in the digital domain. In particular, it describes multi-level models for digital components and subsystems, in which the main activities (which are related to Task 3.2) focus on the modeling of such components in discrete time and over a well-defined set of stable states.

This deliverable is the update of D3.2.1, which gave a preliminary description of the models suited to describe digital components at different abstraction levels such as, register transfer and transaction level, and to define simulation scenarios suitable to the identified models. D3.2.1 also identified issues that could arise during the integration of components and subsystems of the smart system and proposed preliminary possible solutions. D3.2.1 has been evaluated and approved by the project reviewers in the review of the first year activity of the project.



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2 Introduction

With respect to the other four domains of SMAC, the digital one has one important peculiarity, namely, the fact that the design flow is highly standardized (e.g., commercial, fully automated synthesis & optimization tools, technology libraries, etc.) and so are the formats and the models used in these design flows (i.e., SystemC TLM, VHDL or Verilog RTL).

On the other hand, several solutions are available to designers to model components and subsystems at different abstraction levels, from the most accurate and slowest in simulation (RTL) to the most abstracted and fastest (TLM). In addition, integration of such components, which is the keyword driving the design dimension of the digital domain, allows designers to mix different levels of design accuracy in the same model. This simplifies and speeds up the optimization of some components with respect to others and allows designers to create the model of the whole platform early in the design flow.

Nevertheless, such a multi-level integration of the model also gives rise to several issues. The SMAC platform for Task 3.2 deals with digital block which are parts of more complex and smart systems, such as electro-magnetic emissions models (OnSEMI), models for signal processors suitable for efficient elaboration of medical data derived from accelerometers, photo-detectors, electrodes and temperature sensors (UNOTT), smart microphone systems (ITE), models for general-purpose digital blocks which have been applied to implement the detection and correction design paradigm of T4.2 (POLITO).

In general, partners of Task 3.2 rely on different HDLs for describing their components and sub-systems, which require to be translated into a common language to be simulated. This deliverable summarizes how the SMAC platform, and in particular, the flows for translating the HDL descriptions into SystemC/C++ or SystemVue, have been adopted to deal with such model heterogeneity.

The deliverable presents a classification of digital components and subsystems that operate in discrete-time and over a well defined set of stable states: cycle-accurate (CA) digital models, transaction-accurate (TA) digital models, models for analogue components in the digital event-driven simulator, and models to evaluate EMI emissions from digital blocks.

In T3.2, EDAL supported the abstraction of the partners’ IP cores from RTL to TLM through the use of a tool developed in WP2. In addition, by exploiting the feedbacks of the abstraction process on the partners’ models, EDAL defined and developed an optimization of the abstraction methodology originally implemented in the SMAC toolchain to further increase the simulation speed of the generated abstract models.



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2.1 Innovations in this deliverable

The main innovations reported in this deliverable are:

• A classification of models suited to describe digital components and subsystems, which covers the different abstraction levels in which digital component may be implemented and the corresponding simulation scenarios.

• For each class of digital models, the document shows how they are supported by the SMAC platform, by underlying the flow and the tools of the platform involved and the corresponding simulation scenario.

• An extension of the RTL-to-TLM abstraction methodology to abstract the cycle-accurate digital models implemented by the SMAC partners in the context of WP3 into transaction-accurate (TLM) models.

• A new model to evaluate EMI emissions from digital blocks. The model focuses on estimating the filtering effect of the on-chip decoupling, the substrate network and the package.



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2.2 Contribution toward the SMAC platform

This deliverable allows moving forward the SMAC platform by providing the following fundamental components:

• The deliverable classifies the digital models and subsystems developed in different contexts, by different partners, through different developing tools, and with different hardware description languages.

• The deliverable defines methodologies and tools in the SMAC platform to deal with the heterogeneity of the classified models.

• The deliverable proposes an extension of the abstraction methodology, which abstracts cycle accurate models into transaction accurate models, by implementing an intermediate scheduling solution that allows gathering the advantages of both static and dynamic scheduling. The extension aims at improving the simulation speedup of the abstracted models, and has been implemented in a prototype tool built upon the A2T HIFSuite tool of EDALAB.

.



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3 Cycle-accurate digital models

This class of models aims at modeling and simulating digital components at the most accurate level of detail. In a design flow of digital components, the CA model is required for two main reasons:

1. To support software development, such as, software applications and IP device drivers;

2. To prove the value of the device through performance analysis and the evaluation of energy consumption and its potential impact in the smart system applications.

From this task partners’ point of view, the source of CA model is the RTL implementation. The RTL has the benefit of being a required deliverable that has been usually created by the hardware design group as a normal part of the development process. Thus, IP reuse, which is the key strategy to cope with complexity of modern smart system design and their time to market, mainly involves partners’ RTL IPs. The RTL IP model, which is implemented through a HDL language, is the entry point in the digital domain, as shown in Figure 1.

Figure 1. Simulation levels / design-domain matrix.

In T3.2, POLITO developed RTL CA models for general-purpose digital blocks, which have been applied to implement the detection and correction design paradigm of task 4.2. UNOTT concentrated on models for signal processors suitable for efficient elaboration of medical data derived from accelerometers, photo-detectors, electrodes and temperature sensors. ITE developed a CA digital decimation filter for MEMS microphone system.



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4 Transaction-accurate digital models

Even though the RTL CA model is the entry point for the digital domain, the simulation performance at RTL severely limits the amount of software and the types of analysis that could be done. In facts, from the software development point of view, there is no full need of a cycle accurate RTL model. A fast functional model would provide the best simulation performance, which is the primary need of the software developers.

As a consequence, some compromise is needed to balance the simulation performance with the timing and power accuracy. A cycle-approximate model, which is about 90% accurate, would provide the confidence needed for the design development.

In this context, the transaction-accurate digital model would allow creating loosely timed (LT) models for the software developers and approximately timed (AT) models with clock cycle annotation for use in the performance analysis case. This would guarantee a sound trade off between simulation performance and accuracy for a wide range of user's needs during the digital component design and verification.

The TA digital modeling, which is referred as TLM in literature, is nowadays the reference modeling style for HW/SW design and verification of digital systems. TLM greatly speeds up the verification process by providing designers with different abstraction levels whereby digital systems are modeled and verified. The complexity of modern systems can be handled by designing and verifying them through successive refinement steps.

With a TA model, designers build and verify a system in terms of functionalities characterized by high-level I/O events and data transfers between computational blocks. The model represents communication, which is separate from computation, as channels that provide high-level communication primitives to the computational components.

Figure 2 shows the comparison between the CA and TA models of a simple sequential adder. The adder calculates the sum of two data, (data1 and data2). The I/O operations performed by both CA and TA models are conceptually the following:

read data1; read data2; write result.



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Figure 2: The CA vs. TA model comparison in terms of protocol details

The CA model has three PIs (clock, data_IN, and data_en_IN) and two POs (result_OUT and result_en_OUT). Reading data1 corresponds to read ports data_IN and data_en_IN, for getting the data1 value only if the data_en_IN flag is set. The same happens for reading data2. Each read operation is associated with two CA events: one for reading data_en_IN, and the other for reading data_IN. In the same way, writing the result corresponds to two events associated to a write on result_OUT and a write on result_en_OUT.

A corresponding TA model of the same component preserves only the PI data and the PO result, since flags for enabling read and write operations are useless in the case of a transaction-based communication. The clock signal is not included in the model interface, while the clock cycles can be annotated in the TLM primitive. The read operation is associated with a write transaction performed by an initiator to the adder. During the first write transaction, the adder gets the data1 value by means of one or more primitive calls, depending on the TA interface. Such a read operation can be considered accomplished only when the write transaction ends, that is, when the one (or sequence of) TLM primitive(s) has been called and the data packet has been moved from the initiator to the adder module. The same happens for getting data2. Thus, each read operation is associated with 2 TA events. On the other hand, returning the result of the computation corresponds to 2 events (for the start and the end of the read transaction).

The TA model offers several practical advantages:

• It abstracts implementation details while preserving the system’s behavioral aspects, thus allowing up to 1,000 times faster simulation than CA modeling.

• Designers can modify and replace IP components and buses more easily than in the CA model, so system-level design exploration and verification are simpler.

• Designers can quickly create an early software development platform.

Integration of components into the system is easier than the corresponding CA model, since the level of details of both interfaces and communication protocols is lower.



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Easy integration of IP cores developed/provided by the SMAC partners is a key strategy that guarantees considerable saving of time in the smart system modeling. Modeling a complex smart system ex-novo at transaction level could be inconvenient, since the partners’ RTL IPs are continuously evolving and customized for different smart systems designs.

In T3.2, EDAL supported the abstraction of IP cores from RTL to TLM through the use of a tool developed in WP2. The RTL-to-TLM abstraction aims at increasing simulation speed by removing clock details from the models and preserving only the functional behavior of the system. Figure 3 shows how the abstraction process is involved in the SMAC platform, by highlighting the related flows between models, libraries, and tools. In particular, RTL-to-TLM abstraction relies on the methodology described by EDALab in D2.2.1 and it is automated by the A2T tool of HIFSuite. The reader is thus referred to the deliverable D2.2.1 for the basis of the abstraction process.

Finally, during the T3.2 activity, the feedbacks matured from the application of HIFSuite A2T to the partners’ RTL IPs have led to an extension of the abstraction methodology to improve the generated TLM model performance in simulation. The extension involves the scheduling activity of the HDL processes once converted into SystemC/C++ processes. The main idea behind the extension of the abstraction methodology relies on the results recently obtained for the HDL processes scheduling investigation for the efficient simulation of RTL IPs on GPGPUs [1] [2] [3] [4]. Such approaches are specific to each GPU architecture, but they propose in general to mix the mandatory static scheduling policy of a GPU, with a dynamic scheduling approach implemented in the controlling CPU.

The EDAL contribution in the abstraction activity of T3.2 starts from such investigations, and proposes to estimate the conditions that make one scheduling philosophy more efficient than the other. Then, it builds a novel scheduling technique that combines the advantages of both approaches for the execution on a standard CPU. The HDL design is partitioned into subsets that adopt the most suitable scheduling policy, that are then executed by respecting inter-process dependencies. The result is an optimal execution configuration. The partitioning process into subsets and scheduling policies is based on heuristics and on exploration of alternative solutions, that is further enhanced by automatic code generation.



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Figure 3: The abstraction flow of digital components and sub-systems in the SMAC platform



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5 Models for Analogue Components in the Digital Event-driven Simulator

This section describes a frame-work and the associated models allowing to translate the schematic of analogue circuit into a digital VHDL representation, which is event-driven and allows to implement conservative interfaces in simulators relying on a flow-chart oriented model of computation .

5.1 Target simulation scenarios

Debugging digital-to-analogue interfaces using co-simulation involving a digital simulator and a circuit solver is traditionally a very time-consuming process. Setting-up the appropriate configuration to interface the digital simulator and the circuit solver requires a lot of care, in many cases one is constrained to use only the simulators supported by a specific vendor. In practice the simulation speed is dictated by the circuit solver as the digital simulator is traditionally much faster (especially in the case of digital designs counting less than 100k gates). As a result, there is a strong incentive in trying to speed-up the process of debugging D/A and A/D interfaces by generating a model of the analogue function that can be executed in the digital simulator.

Figure 4 shows the corresponding simulation scenario. Its objective is to enable and speed up a systematic debugging of the digital to analogue interfaces by running tests in the digital simulator at RTL level, typically using a language as VHDL or Verilog. In order to realize this scenario, the conservative representation of the analogue and power components in the circuit simulator must be mapped into the discrete-time (eventually event-driven) flow-chart scheme of the digital RTL-level simulator. In order to realize this, the waveform relaxation scheme was adopted.

Figure 4: Using waveform relaxation to embed a description of analogue blocks in the digital event-driven simulator

Its benefit is that it allows to map the Kirchoff conservation laws which give rise to a coupled system of equations in the circuit simulator, into a directed flow-chart representation that converges in a few iteration to the target state and is easily implemented in a digital simulator. More details on this scheme will be given in Section 5.2.

MEMSSensors & Act

DigitalHardware

PowerSources

Analogand RF

EmbeddedSoftware

Functional

Structural

Device

C++ SystemC TLMC++

RTL HDL(ModelSim)

C++ C++SystemVue QEMU

Cycle AccurateQEMU

AMS HDLMatlab suite

MEMS+AMS HDLFEM Models

Spice

EMProMomentum

Spectre

Cycle Accurate

QEMU

PhysicalFEM modelsMatlab suite

MEMS+AMS HDLFEM models

Spice

EMProMomentum

Spectre

Discrete &power device

C++

EMProMomentum

Spectre

EMProMomentum

Spectre

Transactional SystemVueSystemC

TLMSystemVue

SystemVue SystemVue QEMUSystemVueSystemVue

ADS Cir. Sim.AMS HDL

Matlab suiteMEMS+

Matlab/Simulink AMS HDLVerilogA

VHDL-D Simulator

(ModelSim)

VHDL-D Simulator

(ModelSim)



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Figure 5 shows the mapping of the model preparation flow (from netlist to VHDL) and the target simulation flow onto the SMAC platform.

Figure 5: Mapping the EMI simulation flow onto the SMAC platform.

5.2 General Data-flow and Interfaces

As indicated in deliverable D3.2.1., the Kirchoff conservation laws that govern the interconnection of blocks in the analogue domain give rise in circuit simulators to a system of coupled equations that must be explicitly solved. Using the waveform relaxation principle it is possible to re-formulate the interconnection equations as a directed flow-chart system that converges after a few iterations to the correct state of the interface and is compatible with the event-based model-of-computation used in RTL-level digital simulators.

Applying the waveform relaxation principle, it is possible to transform analogue component models meant for use in standard circuit simulators into VHDL code which will be capable to reproduce the same behaviour in the ditigal simulator based on the event-based model of computation. Thanks to waveform relaxation it is possible to model an analogue block in the digital simulator with the same number of waveform relaxation ports as terminals in the circuit simulator. The connectivity of the analogue components in their representation in the digital simulator will be the same as that of the corresponding circuit netlist. The underlying data-types of these connection will be however a bit more complex, as it will be a structure type containing the quantities listed in the tables of sections 5.2.1till 5.2.3.

Figure 6 shows a detailed flow chart of how a mixed-signal simulation can be setup when using the waveform relaxation principle to create models for the analogue components in the RTL-level digital simulator. The critical point in order to enable the mixed-mode simulation is the availability of models for the analogue blocks in the

SystemVue(DF Simulator)

Data-Flow ModelsRF Models

MATLAB/Simulink

(CT Simulator)Simulink ModelsModelSim

(DE Simulator)

HIF Suite

QEMU(Instruction Set

Simulator)

WiCkeD

SystemC (DE Simulator)

ADS (Circuit simulator)

(DF Simulator)(EM Simulator)

(Thermal Simulator)Circuit Models

DF ModelsEM Models

SystemC RTL/TLM

VHDL

M-File

Verilog

Simulink C

SystemVue C++

VerilogA

C

C++

netlist

EM model

TRAPPIST

MEMS+(MEMS

simulator)MEMS models

EM-Pro(EM simulator)

EM Models

IP-XACT

SystemC

VHDL

Verilog

E- /H- fields

S-Parameters

Antenna parameters

Cadence(Circuit

simulator)

DatabaseOpen Access

SAT

PSL

LibrariesSCNSLHDTLib

Comsol(FEA Simulator)Thermal Models

Micro-Fluidic odelsPower Sources

WaveformRelaxation

VHDL

Light blue boxes indicate Simulation ToolsLight green boxes indicate Model Generation ToolsLight orange boxes indicate Modeling FormatsLight red cylinders indicate Database or external LibrariesUnidirectional blue lines indicate Input / Output Models in specific formatBidirectional red lines indicate access to a Database or external Libraries



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digital simulator (implementing waveform relaxation interfaces). Setting up a simulation once these models are available is a pretty straightforward task requiring simple netlisting operations.

In the present project, a comprehensive series of models for basic building blocks were implemented in order to demonstrate the feasibility of the envisioned simulation framework. Details about the implementation of these models is given in section 5.3.

Figure 6: Detailed view of the waveform-relaxation-based mixed-signal flow.

5.2.1 Basic two-component waveform-relaxation interface

This type of interface represents the current state-of-the-art in waveform relaxation applied to circuit solvers, and was already described in deliverable D3.2.1. As indicated in Figure 7 and Figure 8 below, the {𝐼𝐼(𝑡𝑡),𝑉𝑉(𝑡𝑡)} in continuous time formulation is replaced in waveform relaxation by a pair of voltage waves {𝑉𝑉𝑜𝑜1(𝑘𝑘𝑘𝑘),𝑉𝑉𝑜𝑜2(𝑘𝑘𝑘𝑘)} in discrete-time with sampling period 𝑘𝑘. A characteristic impedance 𝑅𝑅𝑜𝑜 is assigned to the connection and plays a key role as “default intermediate” termination in the relaxation process. The formulation {𝑉𝑉𝑜𝑜1(𝑘𝑘𝑘𝑘),𝑉𝑉𝑜𝑜2(𝑘𝑘𝑘𝑘),𝑅𝑅0,𝑘𝑘} is in fact inspired from transmission-line theory and the overall behaviour of the waveform relaxation interface corresponds to that of a loss-less transmission line of characteristic impedance 𝑅𝑅𝑜𝑜 and delay 𝑘𝑘.



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Figure 7: Analogue conservative electrical interface

Figure 8: Schematic of the waveform relaxation interface corresponding to the connection of Figure 7.

Besides the characteristic impedance parameter and the wave voltages, two additional logic signals are introduced : a clock signal defining the time-ticks for synchronization of state changes, and a convergence signal indicating whether the interface has reached a converged state (which can be compared directly to results from the analogue conservative formulation in the circuit simulator).

5.2.2 Generalized multi-terminal waveform relaxation interface

This section introduces an extension of the waveform relaxation formulation to cover multi-branch “star-type” connections between multiple blocks as shown in Figure 9. The new multi-terminal extension relies on the definition of “wave voltages” as shown on the schematic of Figure 10. The corresponding component-side schematic of the interface is shown in Figure 11 and Figure 12 along with the corresponding equations allowing to compute the node voltage from the “wave voltages” emitted by each of the component tied to the node.

Figure 9: Analogue conservative multi-branch net : N degrees of freedom : 1

voltage, N-1 currents

Figure 10: Definition of the N wave quantities allowing to capture the state of the new relaxation interface



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𝑉𝑉𝑇𝑇1,𝑘𝑘 = 𝑅𝑅𝑇𝑇1 ∙ �𝑉𝑉𝐾𝐾,𝑘𝑘−1

𝑅𝑅𝐾𝐾𝐾𝐾=2..𝑁𝑁

𝑅𝑅𝑇𝑇1 = � �1𝑅𝑅𝐾𝐾𝐾𝐾=2..𝑁𝑁

�−1

𝑉𝑉𝑃𝑃,𝑘𝑘 = � �1𝑅𝑅𝐾𝐾𝐾𝐾=1..𝑁𝑁

�−1

∙ �𝑉𝑉𝐾𝐾,𝑘𝑘

𝑅𝑅𝐾𝐾𝐾𝐾=1..𝑁𝑁

Figure 11: Schematic of the waveform relaxation interface for component #1

Figure 12: Final formulation of the waveform relaxation interface for one branch of a multi-

terminal connection

The formulation is more general than the formulation for a basic two-tier connection, as it allows to employ different characteristic impedances for each individual component involved in the connection. Besides the characteristic impedance parameters and the wave voltages, two additional logic signals are introduced : a clock signal defining the time-ticks for synchronization of state changes, and a convergence signal indicating whether the interface has reached a converged state (which can be compared directly to results from the analogue conservative formulation in the circuit simulator).

5.2.3 Velocity-based formulation of the waveform relaxation

When applying waveform relaxation in a discrete-time context, an error threshold is defined allowing a component model to refrain from generating new events and update its outputs as long as they are sufficiently close to the internally computed analogue target. In the case of strongly varying signals, the threshold constraint may lead to the need to generate many events in order to update the outputs frequently enough such that the stair-case approximation remains sufficiently accurate. This may cause a substantial computational burden, and cause a significant lack of speed-up with respect to a plain SPICE simulation. In order to reduce the number of update events generated, several alternatives are possible :

• Compute the slope of the signals besides the initial value for the given clock period. This enables to approximate a signal by a piece-wise linear representation instead of the stair-case representation used earlier. It corresponds to a velocity-based description of a dynamical system.

• Describe the signals based on their decomposition in function of some families of basis functions as in This will reduce the number of update events to a strict minimum, at the cost of a quite complex representation of the port signals, a substantial memory allocation and more calculations at each time-clock in order to determine update all coefficients in the series representation of the signal.

In the frame of this activity, the representation of signals based on one offset value and a slope was preferred, because of its limited memory consumption and ease of implementation.



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5.3 Implementation Details

Models for the following basic components were implemented by ONSEMI in the frame of this activity :

• Passive components : resistors, inductors, capacitors, voltage sources, current sources • Active components : diodes, low-voltage MOSFETs, high-voltage DMOS transitors

5.4 Summary of Improvements, Features and Limitations

The implementation of a comprehensive series of waveform relaxation models for key analogue components is a major step forward with respect to the initial feasibility work reported in deliverable D3.2.1. The implemented models allowed to validate the concept of waveform-relaxation on a series of circuits representative of the cases that would require co-simulation of digital and analogue components.

The main benefits experienced with the waveform relaxation approach are the following :

• Conservation of the topology and connectivity of the analogue circuit when implemented in the digital simulator. The relaxation scheme allows to solve for node and branch currents in a transparent fashion, without forcing the designer to cut feedback loops.

• The same core model equations can be implemented. Meaning that model libraries can just be “translated” without having to run a new model extraction whem mapping from the circuit simulator to the digital simulator.

• The waveform relaxation scheme introduces a degree of freedom allowing to trade accuracy versus simulation speed by playing with the threshold levels below which changes in output values are not propagated.

• Waveform relaxation was found to be more robust against convergence issues in switched inductors circuits than traditional circuit solvers.

The main limitations experienced with the waveform relaxation approach are the following :

• In order to simulate some analogue functions properly, it might be necessary to tighten the accuracy requirements to such a level that in the “stair-case” formulation of the waveform relaxation (see Sections 5.2.2), the dynamic elements (the capacitors and inductors) tend to generate many events (updates of their outputs) which result in a significant computational burden on the digital simulator and limit the acceleration that can be achieved with respect to the circuit simulator.

• The “velocity-based” formulation described in section 5.2.3 provides in principle a way to reduce the number of update events and improve on the previous point, however it could not be fully implemented till now.

• In the present implementation, the core model equations were encoded in VHDL directly. As VHDL supports direct calls to external function compiled from the “C” language, it would be possible to access external model libraries in the CMI format, such that exactly the same model code would be shared across both simulators.



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• At the time of writing, no link was yet established to TRAPPIST models. However implementation of TRAPPIST models in the waveform relaxation framework should be relatively simple. There is a natural fit of TRAPPIST and the “velocity-based” formulation, and the transfer trajectories matrices from TRAPPIST naturally provide the Jacobians needed to the Newton-Raphson iteration on non-linear devices.



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5.5 Model Extraction Procedures

The waveform relaxation principle was introduced as a means to implement analogue conservative netlists in an event-driven non-conservative flow-chart simulator typically used for RTL-level (structural, discrete-time) simulation of digital circuits. The waveform relaxation principle allows to map the Kirchoff conservations laws into a set of explicit equations easily implemented in the RTL-level digital simulator where the state of the connection is computed iteratively over a few iterations, instead of being implicitely resolved “at once” by a global Newton-Raphson solver.

As such, the waveform relaxation principle allows to re-use the core I(V), Q(V) or C(V) (also de V(I) or 𝜙𝜙(𝐼𝐼) in case of inductive branches) equations from the original circuit simulator models, which are just “connected” through the relaxed waveform interfaces. In the case of non-linear devices, it might be necessary to wrap a local Newton Raphson solver around the core model equations, in order to account for the effect of the characteristic port impedances on the model response. These “wrappers” must typically solve a very simple problem and do not represent a significant burden on the simulation.

As the core of the device equations are the same in both the circuit-solver or the event-driven ditigal simulator, the model extraction task can be done in either one, and transferring the parameters into the other implementation is sufficient in order to obtain the same responses. In the frame of this work, parameter extraction was done on VerilogA implementations of the models using the SPECTRE simulator. The parameters were then transferred into the waveform-relaxed VHDL implementation of the model and the responses were compared, in order to check the validity of the implementation.

At the time of building the digital event-driven netlist for the analogue block, a few “choices” still have to be made which help to optimize the rate of convergence and the accuracy of the analogue / digital co-simulation. These parameters are :

• The clock-period which must be sufficiently high such that the Nyquist criterion is met for all physical time-constants present in the system.

• The characteristic port impedances must be chosen. When these are chosen such as to match the real load impedance seen by the port, the waveform relaxation converges in a single step. However in the case of non-linear circuits or dynamic loads (inductors and capacitors) a perfect match cannot be realized as the load will vary in function of time or internal states. A good criterion is to take a value which is the geometrical mean of the minimum and maximum load impedance encountered.



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5.6 Validation Methodology

In order to validate the models implemented in the frame of this work, the results from the digital netlists implementing the waveform relaxation principle were compared both to the results obtained in the circuit simulator using the original analogue netlists, but also to a modified netlist emulating the waveform relaxation interface in the circuit simulator using loss-less transmission lines, as illustrated in Figure 13.

(a)

(b)

(c)

Figure 13: Alternative representations used for validation:

(a) conservative electrical connection in the circuit simulator; (b) waveform relaxation interface in the digital simulator;

(c) emulation of the relaxation interface in the circuit simulator.

The figures shown below provide a non-exhaustive overview of the model validation results for various components: Figure 14: Comparing the waveforms obtained for a voltage pulse from a lossy voltage source to a mismatched resistor by relaxation (curves labelled VHDL) in the digital simulator and by .the emulation of relaxation in the circuit simulator (curves labelled CAD). The x-axis units are normalized time-steps.Figure 14 compares the results obtained in the case of a resistor; Figure 15 in the case of a diode put in forward bias; Figure 16 for an inductors switched in an H-bridge configuration; Figure 38 in the case of a resistor with multi-pole connections on each of its terminals.

The waveform relaxation models were found in all cases to produce the correct voltages and current values as soon as the relaxation iterations had died out.



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Figure 14: Comparing the waveforms obtained for a voltage pulse from a lossy voltage source to a mismatched resistor by relaxation (curves labelled VHDL) in the digital simulator and by .the emulation of

relaxation in the circuit simulator (curves labelled CAD). The x-axis units are normalized time-steps.

Figure 15: Comparing the waveforms obtained for a voltage pulse from a lossy voltage source to a diode by relaxation (curves labelled VHDL) in the digital simulator and by .the emulation of relaxation in the circuit

simulator (curves labelled CAD). The x-axis units are normalized time-steps.



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Figure 16: Comparing the voltage waveforms obtained for an inductor by relaxation (curves labelled VHDL) in the digital simulator and by .the emulation of relaxation in the circuit simulator (curves labelled CAD). The

x-axis units are normalized time-steps.

Figure 17: Comparing the voltage waveforms obtained for a resistor with start connections on both terminals by relaxation (curves labelled VHDL) in the digital simulator and by .the emulation of relaxation in the circuit

simulator (curves labelled CAD). The x-axis units are normalized time-steps.



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5.7 Benchmarking and Technical Exploitation Perspectives

There have been several reports about dedicated solvers based on the waveform relaxation principle in the past. However so far no application of the waveform relaxation principle in order to implement event-driven models for analogue components in the gate-level digital simulator was found in the literature.

The most advanced high-level modelling of analogue blocks in an event-driven simulator is represented by the work of Hoeldampf et al at INFINEON. This team implemented state-based models in a System-C environment. On the contrary to the work realized in the frame of SMAC, the System-C models built by the INFINEON team have to encompass the full analogue function and only allow composition of blocks in a non-conservative manner. As such these models are well suited for simulation at high abstraction levels, but they do not provide an appropriate solution for the interactive debugging of digital to analogue interfaces occurring at the structural level.

Most other approaches for the analogue mixed-signal modelling of blocks only consider “signal path” propagation of signals and when dealing with non-linearities do not cover the possibility of state changes. The waveform relaxation formulation, especially with the Newton-Raphson wrappers around the non-linear models instrinsically covers state changes.



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6 Models to evaluate EMI Emissions from Digital Blocks

As indicated by Badaroglu et al. in [5], moving along the technology roadmap, the risk exceeding the noise emission limits is increasing. As a result it has become increasingly important to evaluate the anticipated EMI levels sufficiently early in the design cycle. For this purpose ONSEMI adopted an approach similar to that demonstrated by Steinecke in [6]. The general principle is that the emission spectrum is estimated from simplified dynamic current waveforms which are then filtered by models of the on-chip decoupling, the supply-network, the package model, and eventually PCB-level decoupling and parasitics.

The model developed at ONSEMI in the frame of SMAC focusses on estimating the filtering effect of the on-chip decoupling, the substrate network and the package. As illustrated in Figure 18, the complex nature of a digital block is abstracted as an array of tiles, allowing to apply “standard” layout extraction techniques in order to build a filtering network model.

(a)

(b)

Figure 18: Modelling a logic block as an array of abstract logic tiles : (a) Layout view showing “logic tiles model”; (b) Equivalent circuit.



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6.1 Target simulation scenarios

The purpose of estimating the level of emissions generated by a digital block is to assess that the resulting noise levels do not disturb the operation of other (eventually more susceptible) parts of the system. Whilst the source of the noise is the switching of gates, which is related to events in the digital domain, the propagation of the noise in the system and the assessment of its impact is mainly an analogue-domain task. As a result, information has to be extracted out of the digital-domain description of the logic block and transformed into waveforms and models to be used in analogue-domain circuit simulation.

As digital-domain tools and data representations have the ability to handle much higher complexity than analogue tools, the transfer of information from the digital domain to the analogue side has to happen in conjunction with a change in the abstraction-level, in order to reduce the complexity of the simulations that need to occur on the analogue side. The “logic tile” model used here, is an abstraction for the content of a logic block, where a large number of gates of various types (typically several tens of thousands of instances selected out of a hundred of possible cell types) is replaced by a small number (maximum a few hundreds) of instances of a single model with “average” parameters. The “logic tiles” model allows to substitute the detailed layout of a digital block by a simpler array of “logic tiles” and to then subject the simplified model to standard extraction flows, allowing to account for parasitics of the supply network and the substrate and to obtain a realistic model of the filtering capability of the design. Applying this filter to the total instantaneous current consumption waveform, the final emissions spectrum can then be estimated in various modes of operation (represented by different consumption waveforms and their repetition rate and timings).

Figure 19: Mapping the EMI simulation flow onto the SMAC platform.

SystemVue(DF Simulator)

Data-Flow ModelsRF Models

MATLAB/Simulink

(CT Simulator)Simulink ModelsModelSim

(DE Simulator)

HIF Suite

QEMU(Instruction Set

Simulator)

WiCkeD

SystemC (DE Simulator)

ADSSPECTRE

(Circuit simulator)(DF Simulator)(EM Simulator)

(Thermal Simulator)Circuit Models

DF ModelsEM Models

SystemC RTL/TLM

VHDL

M-File

Verilog

Simulink C

SystemVue C++C

C++

netlist

EM model

MEMS+(MEMS

simulator)MEMS models

EM-Pro(EM simulator)

EM Models

IP-XACT

SystemC

VHDL

Verilog

E- /H- fields

S-Parameters

Antenna parameters

Cadence(Circuit

simulator)

DatabaseOpen Access

SAT

PSL

LibrariesSCNSLHDTLib

Comsol(FEA Simulator)Thermal Models

Micro-Fluidic odelsPower Sources

VerilogA

TRAPPIST

Magwel(Field-solver)

Substr. model

Light blue boxes indicate Simulation ToolsLight green boxes indicate Model Generation ToolsLight orange boxes indicate Modeling FormatsLight red cylinders indicate Database or external LibrariesBidirectional green lines indicate Co-simulation LinksUnidirectional blue lines indicate Input / Output Models in specific formatDotted unidirectional blue lines indicate Output Modeling Functions (extending models

by parameterization)Bidirectional red lines indicate access to a Database or external Libraries



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Figure 19 shows the mapping of the EMI modelling flow for a digital block. Its core consists in a series of simulations which are run in the circuit simulator, where the instantaneous current consumption waveform representing the switching activity of the block in the target operation mode is filtered by the model of the supply network, substrate, package and eventual board-level components.

Key inputs in this flow are :

1. The instantaneous current consumption waveform which represents the charge consumption related to switching activity within the block during a clock cycle. It can be related to one single specific test-vector imposed on the logic block or can represent an average computed as the superposition of the consumption waverforms from several clock cycles in a given operating mode, taking the clock edge as time-reference. This waveform can be evaluated using extensive RTL-level simulations as proposed in in [7] or [8]. Or it can be constructed at a high-level of abstraction considering the total charge consumed per cycle and architectural information such as the depth of the clock-tree, the number of flip-flops and the distribution of path lengths in the logic, [9], [10].

2. Library characterization data providing the “average” decoupling capacitances and associated resistances for the library cells used in the design. This allows to construct the model of the “logic tiles” which will be substituted to the content of the logic block in order to evaluate its filtering capability.

3. Floorplan information for the IC showing the logic block and how it is interconnected to the supply domain and the corresponding bond-pads and connections to external supplies. This allows to build a substrate model, to extract the parasitics of the supply nets and to correct connect the logic tiles into a final netlist model of the “overall supply network filter”.

Figure 20: Simulation scenario to evaluate the emission spectrum from digital blocks.

The proposed EMI simulation scenario operates essentially at the “structural level”, as illustrated in Figure 20. Indeed most functional blocks (core logic, memories, analogue blocks, LDO regulators) are represented by small signal equivalent models, interconnected by the supply network and substrate model as described in [11]. However, in order to obtain realistic estimates the supply and substrate parasitics, a “detour” at a lower abstraction level is necessary in order to extract relevant floor-planning data in the layout, as illustrated in Figure 20 by the blue “implementation” and “red” abstraction arrow. It is this latter one, the abstraction process for the core logic block, which is the main focus of the present contribution.

MEMSSensors & Act

DigitalHardware

PowerSources

Analogand RF

EmbeddedSoftware

Functional

Structural

Device

C++ SystemC TLMC++

(RTL HDL)AMS HDLCkt Simul.

C++ C++SystemVue QEMU

Cycle AccurateQEMU

AMS HDLMatlab suite

MEMS+AMS HDLFEM Models

Spice

EMProMomentum

Spectre

Cycle Accurate

QEMU

PhysicalFEM modelsMatlab suite

MEMS+Layout DBFEM models

Spice

EMProMomentum

Spectre

Discrete &power device

C++

EMProMomentum

Spectre

EMProMomentum

Spectre

Transactional SystemVueSystemC

TLMSystemVue

SystemVue SystemVue QEMUSystemVueSystemVue

ADS Cir. Sim.AMS HDL

Matlab suiteMEMS+

Matlab/Simulink AMS HDLVerilogA

AMS HDLCkt Simul.

AMS HDLCkt Simul.



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6.2 General Data-flow and Interfaces

The objective of the EMI simulation flow is to enable fast estimation of the conducted emission spectra resulting from switching activity patterns inside a logic block, by enabling the filtering of the total instantaneous current consumption waveform by an elaborated power-supply network model. Figure 21 illustrates the corresponding analysis flow.

Figure 21: Flow-chart of the final top-level EMI analysis.

In order to build a comprehensive model of the power-supply network, information from several data sources have to be gathered, as illustrated in Figure 22. The modelling activities occurring at ONSEMI in the frame of Task 3.2 focussed mainly on the exploitation of the “logic tiles” concept and its impact on the estimation of “supply rail parasitics” and “core natural decoupling” capacitances, as well as how to realize its interconnection to the substrate network.



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Figure 22: Flow-chart for the construction of the power-supply network model.

Two main options are available in order to construct the total instantaneous current consumption wavefor : (1) a “vector-based” extensive approach as in [7] or [8], which ONSEMI experimented in a previous project, or higher-level approach as in [9], [10], which ONSEMI considered in the frame of SMAC. Both are illustrated below in Figure 23.

Figure 23: Flow-chart for the construction of the dynamic consumption current waveforms.

In order to estimate the average “core decoupling” capacitances of a logic block, a library characterization step is necessary which allows extracting the built-in decoupling capacitance network for every cell.



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Figure 24: Flow-chart for the construction of the dynamic consumption current waveforms.

The resulting cell-level decoupling impedance networks are then combined as shown in Figure 24Figure 23 in a weighted sum according to number of cells present in the design and the respective probabilities of the different input states, in order to generate a total “built-in” or “natural” decoupling model for the block. A density of decoupling capacitance per length of digital rail is then determined for the block and used (together with associated series resistances) as an input parameter into the logic tiles model in order to build the final filtering model.

Figure 25: Concept schematic of the logic tile showing IO pins.

Figure 25 shows a simplified schematic of the logic tile model and how it interconnects to the remainder of the emission model. More details about the interfaces of this model are provided in Table 2 below.

Table 1: List of input and output quantities to the logic tile model

Symbol Description Type

VDDk kth Upper Supply Pin : Electrical pin allowing to connect the power domain to the higher potential supply. The connection must be conservative as the impedance levels both inside and outside the block play a key role in defining the content of the emission spectrum.

Electrical, Conservative, (input/output)

VSSk kth Lower Supply Pin : Electrical pin allowing to connect the power domain to the lower potential supply. The connection must be conservative for the same reason as

Electrical, Conservative



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above. (input/output)

Itick Total Instantanous Consumption Waveform for kth Supply : Waveform representing the instantaneous sum of all currents consumed within the power domain. This input is split across all logic tiles constituting the model of the power domain in order to approximate the distributed nature of the switching activity within the block (see Figure 18). The computation of this waveform falls out of the scope of this model. It can be realized at different levels of abstraction which constitutes the advantage of the approach, which is applicable at various stages of the design cycle.

Electrical, Non-conservative, input

Lrail Length of rail : Parameter specifying the length of rail represented by the specific instance of the logic tile model. This allows to evaluate the amount of decoupling capacitiance as well as the fraction of the noise current that needs to be injected by the instance

Parameter, Real

Ltotal Total Length of rail : Parameter specifying the total length of rail present in the block in order to compute applicable ratios within each logic tiles.

Parameter, Real



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6.3 Summary of Improvements, Features and Limitations

The EMI modelling procedure described in Section 6 is a new contribution which was not included in Deliverable D3.2.1, Invalid source specified.. The EMI models generated by this procedure provide the following features :

• Ability to evaluate the emission profiles in a given operating mode of the digital block characterized as collection of activities (probability of having a logical 1) imposed on its logic nodes.

• Ability to construct a netlist modelling the filtering action of the supply network including built-in decoupling capacitances, substrate network, on-chip interconnect, package parasitics and PCB components, independently of the actual operating mode of the digital block. In order to consider different operating modes, the instantaneous current consumption waveform as well as the decoupling admittance densities, one being an input to the logic tile instances, the others being parameters, must be changed, without having the re-run the complete extraction flow.

• The flow can interface with several ways to compute the instantaneous current waveform and hence can be operated at different stages of the design cycle, working either purely form high-level architectural information or from low-level design-data extracted from RTL-level simulations.

At this stage the proposed flow suffers some limitations :

• The extraction of the on-chip supply-network interconnect is limited to series resistances and junction capacitances. This is sufficient for typical smart-power technologies relying on CMOS processes of generations older than 180nm, but extensions will be required in the future to incorporate (a) interconnect capacitances, (b) supply network inductances.

• Neglecting the correlations between signals or logic variables in a digital block is known to limit the accuracy of the evaluation of power consumption and hence could also affect the accuracy of the EMI prediction. Higher-level modelling, considering bits as parts of some typed entity for which a probability distribution is a known way to remedy to the problem.



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6.4 Model Extraction Procedures

6.4.1 Substitution of logic tiles and extraction of the supply network

In the frame of Task 3.2, ONSEMI implemented an extraction flow allowing to automatically perform the following operations :

1. Isolate the supply nets and remove all unrelated metals

2. Identify the boundaries of logic blocks and isolate the lowest-level metal corresponding to supply rails

3. Partition the supply rails in order to assign sections to individual logic tiles, position the pins of the logic tiles on the supply rails and provide unique labels

4. Generate the layout data-base required as input for the supply network resistance extraction

5. Extract the netlist instanciating the tiles with appropriate parameters (particularly the extracted rail length, the reference model to use) and connectivity.

(a)

(b)

Figure 26 (a) : Original layout; (b) : Abstracted layout with supply nets and logic tiles only.

Figure 26 illustrates the layout transformations performed by the flow described above seen at the full-chip level. A logic block can be recognized close to the bottom-left corner of Figure 26.a, whilst the large structures at the top are power transistors.



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(a)

(b)

Figure 27 : Zoom into the core logic area : (a) Original layout; (b) Abstracted layout showing the labelled pins of the logic tiles.

Figure 27 shows a zoom into a corner of the digital block allowing to distinguish logic cells and their transistors in the original view (a) and the labelled pins of the logic tiles in the extracted view (b).

The modified layout data-base is then fed into the ESDi resistance extraction tool from MAGWEL which produces a netlist containing resistive network models for the supply nets, typically in less than one hour.

(a)

(b)

Figure 28 : 3D views generated by the PTM resistance extraction tool : (a) Top-side over the left-hand-side edge; (b) Bottom side from the same direction.

6.4.2 Library characterization for the extraction of the decoupling admittance components

In order to extract the state-dependent decoupling admittance components allowing to evaluate the statistical moments of the total built-in decoupling admittance of a digital block in operation, logic library cells are individually instantiated in a simple test-bench as illustrated in Figure 29. This test-bench serves for the extraction



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of the small-signal admittance matrix for every possible state of the cell inputs, enforced as DC biasing conditions at which the circuit is linearized for AC analysis.

Figure 29: Schematic for the cell-level characterization of decoupling admittance components.

In order to easily obtain the key decoupling admittance components, the extracted defined N-1 terminal admittance matrix is transformed into a floating N terminal admittance matrix. The relevant decoupling components (YkD, YkS, YDS, YxD, YxS, for all inputs k and all outputs x) are then directly extracted as elements in the floating admittance matrix. This extraction is performed at every frequency. Eventually the data can be reduced by extracting a poles-zeroes representation of every of the key decoupling components.

6.4.3 Evaluating statistical moments of the decoupling admittance at block-level

In order to evaluate the average (and eventually the variance) of the total decoupling capacitance of a digital block in a certain operating mode (corresponding to some distribution of probabilities over all its interface and internal nodes), it is necessary to consider two kind of contributions:

a. Node-related contributions, involving VDD-VSS discharging path crossing the cell boundaries through their input or output pins. These correspond to components marked with green and red frames in Figure 31 or Figure 29.

b. The internal contributions, involving VDD-VSS discharging paths not crossing cell boundaries (except for the connection to the supplies). These correspond to components marked with blue frames in Figure 31 or Figure 29.

As indicated in Section 6.4.2, the components of the decoupling admittance of logic cells depend in general on the state of the cell (logical values present at inputs or stored in a previous state for flip-flops). However, obtaining the probability of a given state for a particular cell is a non-trivial problem, as in most cases, correlation information between the logic variables in a design is not available and expensive to obtain. The probability of having a specific logic value at a given node is however standardly available, hence the interest of formulating the calculation of the total decoupling capacitance in function of node-related contributions (which are dominating in the case of simple logic cells).

6.4.3.1 Calculation of the node-related contributions

The calculation of the node-related contributions is performed in the following steps:



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1. For every gate instance for the target power domain of the digital block, collect the individual marginal probabilities of their inputs. Then compute the probability of all states of the gate (assuming uncorrelated inputs).

2. For every node in the target power domain of the digital block, list the driver gate instance, compute the average driving admittance YZD|high , YZS|low for the high and low state of the driving output Z, summing over all corresponding states of the driver gate.

3. For every node in the target power domain of the digital block, list the loading gate instances. For every input K of the loading gate instances connected to the node under consideration, compute the average loading admittances YKD|high , YKS|low for the high and low state of the node, summing over all corresponding states of the loading gate.

4. For every node N of the target power domain, create a model for the decoupling contribution in the high (YDS|N=Hi) and low (YDS|N=Lo) states by combining the driver admittances YZD|state and YZS|state with the loading admittances YKD|state and YKS|state for all the connected loading gates, according to the circuit shown in Figure 29. Then evaluate the average contribution from node N as :

𝑌𝑌𝑁𝑁avg = 𝑝𝑝(𝑁𝑁 = 𝐻𝐻𝐻𝐻) ∙ 𝑌𝑌𝐷𝐷𝐷𝐷|𝑁𝑁=𝐻𝐻𝐻𝐻 + 𝑝𝑝(𝑁𝑁 = 𝐿𝐿𝐿𝐿) ∙ 𝑌𝑌𝐷𝐷𝐷𝐷|𝑁𝑁=𝐿𝐿𝑜𝑜 5. Finally sum all average contributions over all nodes : 𝑌𝑌Nodes = ∑ 𝑌𝑌𝑁𝑁avg𝑁𝑁

6.4.3.2 Calculation of the internal cell contributions

The calculation of the internal cell contributions is performed in the following steps:

1. For every gate instance for the target power domain of the digital block, collect the individual marginal probabilities of their inputs. Then compute the probability of all states of the gate (assuming uncorrelated inputs).

2. For gate instance in the target power domain of the digital block, list the driver gate instance, compute the average internal decoupling admittance YGavg summing over all states of the gate : 𝑌𝑌Gavg = ∑ 𝑝𝑝(𝐺𝐺 𝐻𝐻𝑖𝑖 𝑠𝑠𝑡𝑡𝑠𝑠𝑡𝑡𝑠𝑠(𝑥𝑥)) ∙ 𝑌𝑌𝐷𝐷𝐷𝐷|𝐺𝐺 𝐻𝐻𝑖𝑖 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠(𝑥𝑥)∀ 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠(𝑥𝑥)

3. Finally sum all contributions from all gates : 𝑌𝑌Gates = ∑ 𝑌𝑌𝐺𝐺avg𝐺𝐺

6.4.3.3 Evaluation of the decoupling admittance density

Once all contributions assigned to nodes and gates have been aggregated, the total average admittance can be computed for the block by summing the two aggregates: 𝑌𝑌Domain = 𝑌𝑌Gates + 𝑌𝑌Nodes . The decoupling admittance density can then be simply evaluated by dividing the total decoupling admittance by the total length of rail measured in the block. The resulting densities are then used as inputs for the logic tile model described in Section 6.5.1.



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6.5 Implementation Details

6.5.1 Logic Tile Model

The logic tile is an abstraction of the dense core-logic area of a digital block. It represents the average contribution of logic cells for a given length of rail to the noise current injected on the supplies as well as the built-in decoupling capacitance. An array of logic tiles can be substituted to the original cells in the design, in order to simplify the extraction problem whilst still retaining a sufficient level of accuracy on the final model, as distributed effects on the propagation of the noise are taken into account, whilst the total charge consumption and total decoupling capacitance is correctly represented. Figure 30 shows the schematic of the logic tile model.

The injected noise current is modelled by the “CCCS1” current-controlled current source which takes the total instantaneous consumption current waveform as input and locally injects the fraction into the supplies that corresponds to its share in the total length of supply rail present in the block.

The contribution to the built-in decoupling admittance is evaluated based on the length of rail occupied the logic tile and a density of average decoupling admittance computed for the digital block based on data extracted in a library characterization run. The simple model with two capacitors and one resistance is sufficient to capture the frequency dependence of the built-in decoupling capacitance of logic library cells up till a few GHz, [5].

Figure 30: Schematic of the logic tile component.

6.5.2 Built-in Decoupling Capacitance Model for logic cells

In order to correctly predict the emissions generated by a digital block, it is essential to estimate the built-in decoupling admittance of the block. Contributions from the basic logic cells to the block total decoupling admittance can be decomposed in three components, identified by the colored frames in Figure 31:

• The internal decoupling capacitances, marked in blue, which form a charging path from VDD to VSS without crossing the cell borders;

• The decoupling capacitances resulting from the connection of some input of the cell to one of the supply by the output transistor from the driving cell, marked in red;

• The capacitances at the output of the cell related to drain to well junctions of the output transistors, marked in green.



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Most elements of the generic equivalent circuit shown in Figure 31Error! Reference source not found. are of course state-dependent, in the sense that their value depend on the logic state present at all inputs of the cells (or eventually also on the prevoius internal state of the cell in the case of flip-flops).

Figure 31: Generic cell model for the extraction of built-in decoupling capacitance in digital blocks.

During a library characterization round, the key elements from the above equivalent circuit can be easily extracted for every possible combination of the input variable (ie. every possible state of the cell). For a given design, based on activity information, the average contribution from every de-coupling component from the cells present in the design can be estimated by performing a weighted average of the decoupling admittances according to the probability of occurrence of every state. The total average decoupling admittance is then obtained by summing all average cell-level contributions.



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6.6 Validation Results

At this stage of the project, ONSEMI was not able to complete an experimental validation of the full procedure developed in the frame of Task 3.2. However, results from preliminary studies based on manually constructed models showed the validity of the underlying principles, in the case of the emissions generated by a specific EMI test-vehicle realized in a previous project, as illustrated in Figure 32.

Figure 32.b compares measured EMI data with simulations performed with models of increased complexity : (i) the IC on its own, considering the noise source, on-chip decoupling and package parasitics only (‘RD2E’ label), (ii) the IC with a basic model of the board, consisting only in ideal models of the components (‘RD2E + PCB’ label), (iii) the IC with a more elaborate model of the board where PCB tracks are taken into account, but component models are still ideal (RD2E + PCB + TL’ label), and finally, (iv) the most elaborated model where detailed models of all components are also included. The final results achieves a residual error of less than 3dB on the predicted di/dt peak (a measure of the EMI level).

(a)

(b)

Figure 32 – Validation of the EMI modelling procedures : (a) Top-level view of the test-vehicle layout; (b) Comparison of simulations and measurements.



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6.7 Benchmarking and Technical Exploitation Perspectives

The topic of EMI or supply noise has been a very active field of research in the last decade. The EMI modelling procedures described in Section 6 are still advancing the state-of-the-art to the best knowledge of the authors on the following two specific points :

a. Re-usability of the models and procedures throughout the design cycle, enabling either early evaluation based on preliminary floor-plans, high-level estimates of current consumption and activity profiles, or post-layout verification using most detailed evaluations of the dynamic current consumption and application-related activity profiles. With the advantage that the same tools are used in both cases, facilitating the verification tasks, as only incremental updates are required. State-of-the-art methods such as those from Badaroglu [7] or Steinecke and Gstöttner, [8], [12], or Villavicencio and Mussolino [11], [9], mostly use techniques which are specific to one single phase of the design cycle.

b. More accurate evaluation of the state-dependent built-in decoupling capacitance in the digital block. The state-of-the-art method in evaluating state-dependent de-coupling capacitance is currently represented by the method published by Hagiwara et al. This method only considers capacitances and neglects the series resistances associated with each of them at cell-level. However for EMC purposes, broadband responses are of interest, requiring one to consider both the frequency variation of the imaginary and the real part of the admittance. The method proposed here allows taking the frequency dependency of the decoupling admittance into account over the full spectrum, whilst benefitting from a similar speed-up as Hagiwara et al. with respect to SPICE, due to the fact that the full transistor-level netlist of the circuit is never solved.

With the risk of increasing emission levels as one advances along the technology roadmap, the proposed EMI modelling procedure will become more and more critical for the successful design of new products at ONSEMI, especially in the automotive, aero-spatial and medical domains, where EMC requirements play an important role.



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7 Conclusions

This document has summarized the activities carried out in Task 3.2 during the M4-M33 period of the SMAC project. The topic of component and subsystem modeling in the digital domain, which was preliminarily described in D3.2.1, has been extended and completed by this current deliverable. A final classification has been presented to categorize different digital blocks (and their simulation scenario) that are parts of more complex and smart systems, such as electro-magnetic emissions models, models for signal processors suitable for efficient elaboration of medical data derived from accelerometers, photo-detectors, electrodes and temperature sensors, smart microphone systems, models for general-purpose digital blocks which have been applied to implement the detection and correction design paradigm of T4.2. All these digital blocks have been developed in the context of SMAC by different partners (POLITO, UNOTT, ITE, ONSEMI). The classification allows understanding how the SMAC platform, and in particular, the flows for translating the HDL descriptions into SystemC/C++ or SystemVue, have been adopted to deal with such model heterogeneity. The deliverable detailed the abstraction activity conducted by EDAL to abstract cycle accurate models into TLM models and a related optimization of the abstraction technique to improve the simulation speedup of the generate TLM models. A few journals on theses topics are going to be submitted.



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