Filter Design, Distributed...

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Filter Design, Distributed Arithmetic

EE219A – Spring 2008Special Topics in Circuits and Signal Processing

Lecture 13

Slide 2EE219A – Spring 2008 Lecture 13

Agenda

Back to filters: raised cosine– Sampling issues– Spectral mapping

Implementation: distributed arithmetic– Applicable to multi-standard designs

Special use of FFT: wavelets

Announcement: Synplicity training– Wed 5/23, 44-110 Eng-IV

Filter Design for Digital Radios


First Version

Digital Radio

ANALOG

NC

BasebandModulation

Transmit Filter

D/A

A/DReceive Filter

Wireless Channel

Timing Correction

Adaptive Equalizer

Demod/

Detection

Received Data

Input Data

ft

ND

Nc

fs

NB NT

NR

NA ND

Exp(jwot)I

Q

I Q

EE219A – Spring 2008 Lecture 13

Design Procedure

Assume: Modulation, Ts, Bandwidth Specified

I. Algorithm Design:1) Transmit / Receive Filters2) Modulator3) Demodulator4) Detector5) Timing Correction6) Adaptive Equalizer

II. Implementation Architecture

III. Word Length Optimization

IV. Hardware Mapping


Transmit / Receive Filters

1 Mhz

Filter Response

Bandwidth Specification

Actually a concatenation of the digital T/R filters & RF filters

Digital D/A

I

QRF SAW or

MicrostripFilter

Baseband


Filter Design

0 1/2T 1/T-1/2T-1/T

3dB|H(f)|

Symbol Rate = fsymbol bits/sec. = 1/Ts = 1/T

T1 1 10 0 0

Frequency Response of 1 pulse (real)


Filter Design (Cont’d)

Sample Rate = fsBaseband BW = fsymbol/2; Passband BW = fsymbol

If we bandlimit to the minimum possible amount 1/2T

1

-1/2T 1/2T

Then the time response goes on forever; so we compromise with a raised cosine filter.

0 T 2T 3T


Raised Cosine Filter

Frequency Response

HRC(f) =

s

ss

ss

ss

s

Tf

Tf

TTfTT

Tf

2)1(;0

21

21)]

21((cos1[

2

2)1(;1

α

ααααπ

α

+>⇔

+≤<

−⇔

−−+

−≤⇔

NO ISI with this filter


Raised Cosine Filter (cont’d)

Normally we split the filter between the transmit & receive.

HRC(f) = HT(f) HR(f)

HTR(f) = HRC(f) = √H(f)


Raised Cosine Filters (cont’d)

To get the square root filter impulse response we chose a sample rate for the filter, f?, which will be the same as the A/D & D/A sample rates fSQ if we let fAD = fDA = 4 1/Ts(4 times the absolute minimum).We get:

hTr (n) = Σ √HRC (4m/NTs) e j(2Πmn)/N

m = +(N-1)/2

m = -(N-1)/2

; - (N-1)/2 < n < (N-1)/2


Now to Implement the Filter

hn = hTr(n)

+ +

h0 h1 h2

Xin(n)

FIR N=3 (TAP)

Z-1 Z-1A clock cycle delay using a register (ie. D-Flip Flop)

Draw the signal flow graph

XOUT(i) =Σ hnXiN (i – n)N - 1

n = 0


FIR Filter

Let’s start with the FIR filter:

+ +

h0 h1 h2

Xin(n)Z-1 Z-1

Xout(n)

Z-1 = DelayXin(n) Xin(n-1)

A Delay by one sample period


FIR Filter (cont’d)

A more abstract and efficient notation:

h0 h1 h2

Xin(n) Z-1 Z-1

Xout(n)

Assume an add when nodes come together.

Distributed Arithmetic


Distributed Arithmetic: Concept

FIR filter response

Equivalent representation– Bit-level decomposition

Filter parameters– N: number of taps– W: wordlength of x– |xk−n| ≤ 1

MSB Remaining bits

Next step: interchange summations, unroll taps


Distributed Arithmetic: Concept (Cont.)

FIR filter response: bit-level decomposition

Interchange summations, unroll taps into bitsMSB Remaining bits

MSB

Otherbits

tap 1 tap Ntap 2

tap 1 tap Ntap 2 Bit: MSB − i


Example: 3-tap FIR

h0 + h1 + h2111h0 + h1011h0 + h2101

h0001h1 + h2110

xk xk−1 xk−2 Hi (bit slice i)

0 0 0 00 0 1 h2

0 1 0 h1

xk

xk−1

xk−2

…0 … 0 0

…0 … 0 1

…0 … 1 1

MSB LSBi

h0 + h1 + h2

…h2

0 0

1

7

3 bits

address

LUT

Hi is the weightedbit-level sum of filter coefficients


Basic Architecture

…

i

…

i

xk xk−N+1

N bits

address

LUTprecomputedcoefficients

Add / Sub >>

LSB

Out select

yk

Clock rate: (W×fsample)

Add/Sub

2N words foran N-tap filterN=6: 64N=16: 64k

MSB

LSB

Reg

Parallel data stream(fsample)

(fsample)Issue: memory size grows quickly!


#1: LUT Memory Partitioning

1

2N

1 2 M

…2N/M

Idea: split memory into M clusters– N bit address, M clusters N/M bits each cluster

1×2N words required M×2N/M words required

Example: N = 16 M = 2 M = 4

216 = 65,536 words 2×216/2

= 512 words4×216/4

= 64 words


Example: 6-taps, 2 partitions

xk

xk−1

xk−2

…

…

…

3 bits

address

xk−3

xk−4

xk−5

…

…

…

3 bits

address

LUTPart 1

(h0, h1, h2)

LUTPart 2

(h3, h4, h5)

+

N = 6 taps, M = 2 partitions


#2: Memory Code Compression

Idea:

Bit-level expression

cW−1

cW−1−i

Signed-digit offset binary coding: {1, −1} instead of {1, 0}

Next step: plug this inside expression for yk


#2: Memory Code Compression (Cont.)

Use:

Another representation of yk

Term HW−1−i has only 2N−1 values– Memory requirement reduced from 2N to 2N−1


Memory Code Compression Example

Example: 3-tap filter, 6-bit coefficients

[From: M. Ler, 2006]


References

Distributed Arithmetic– Melinda Ler, “An Energy Efficient Reconfigurable FIR

Architecture for a Multi-protocol Digital Front-End,” M.S. Thesis, UC Berkeley, Spring 2006.

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