Figure 5.1 Memory and processing subsystems for MiniMIPS.

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1. 2. Figure 5.1 Memory and processing subsystems for MiniMIPS. Figure 5.2 Registers and data sizes in MiniMIPS. Figure 5.3 A typical instruction for MiniMIPS and steps in its execution. 5.2 Instruction Format. - PowerPoint PPT Presentation

Transcript of Figure 5.1 Memory and processing subsystems for MiniMIPS.

Page 1: Figure 5.1   Memory and processing subsystems for MiniMIPS.

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Page 2: Figure 5.1   Memory and processing subsystems for MiniMIPS.

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Page 3: Figure 5.1   Memory and processing subsystems for MiniMIPS.

Computer Architecture Parhami 3Copyright 2005 by Oxford University Press, Inc.

Figure 5.1 Memory and processing subsystems for MiniMIPS.

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Computer Architecture Parhami 4Copyright 2005 by Oxford University Press, Inc.

Figure 5.2 Registers and data sizes in MiniMIPS.

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Computer Architecture Parhami 5Copyright 2005 by Oxford University Press, Inc.

Figure 5.3 A typical instruction for MiniMIPS and steps in its execution.

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Computer Architecture Parhami 6Copyright 2005 by Oxford University Press, Inc.

Figure 5.4 MiniMIPS instructions come in only three formats: register (R), immediate (I), and jump (J).

5.2 Instruction Format

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Figure 5.5 The arithmetic instructions add and sub have a format that is common to all two-operand ALU instructions. For these, the fn field specifies the arithmetic/logic operation to be performed.

5.3 Simple Arithmetic and Logic Instructions

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Computer Architecture Parhami 8Copyright 2005 by Oxford University Press, Inc.

Figure 5.6 Instructions such as addi allow us to perform an arithmetic or logic operation for which one operand is a small constant.

What are the machine code for:andi $t0,$s0,61ori $t0,$s0,61xori $t0,$s0,61

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Computer Architecture Parhami 9Copyright 2005 by Oxford University Press, Inc.

Figure 5.7 MiniMIPS lw and sw instructions and their memory addressing convention that allows for simple access to array elements via a base address and an offset (offset = 4i leads us to the ith word).

5.4 Load and Store Instructions

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Computer Architecture Parhami 10Copyright 2005 by Oxford University Press, Inc.

Figure 5.8 The lui instruction allows us to load an arbitrary 16-bit value into the upper half of a register while setting its lower half to 0s.

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Figure 5.9 The jump instruction j of MiniMIPS is a J-type instruction which is shown along with how its effective target address is obtained.The jump register (jr) instruction is R-type, with its specified register often being $ra.

5.5 Jump and Branch Instructions

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Figure 5.10 Conditional branch (bltz, beq, bne) and comparison (slt, slti) instructions of MiniMIPS.

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Figure 5.11 Schematic representation of addressing modes in MiniMIPS.

5.6 Addressing Mode –how to obtain operand’s address

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Table 5.1 The 20 MiniMIPS instructions covered in Chapter 5.

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