Figure 5–1 An example of AND-OR logic. Open file F05-01 to verify the operation. Thomas L. Floyd...

Figure 5–1 An example of AND-OR logic. Open file F05-01 to verify the operation.

Thomas L. FloydDigital Fundamentals, 9e

Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458

All rights reserved.

Figure 5–2




Figure 5–3 An AND-OR-Invert circuit produces a POS output. Open file F05-03 to verify the operation.




Figure 5–4




Figure 5–5 Exclusive-OR logic diagram and symbols. Open file F05-05 to verify the operation.




Figure 5–6 Two equivalent ways of implementing the exclusive-NOR. Open file F05-06 to verify the operation.




Figure 5–7 Logic circuit for X = AB + CDE.




Figure 5–8 Logic circuits for




Figure 5–9 Logic circuit for . Open file F05-09 to verify the operation.




€

Figure 5–10 Open file F05-10 to verify the operation.




Figure 5–11 Open file F05-11 to verify the operation.




Figure 5–12 Open file F05-12 to verify that this circuit is equivalent to the circuit in Figure 5–13.




Figure 5–13




Figure 5–14




Figure 5–15




Figure 5–16 Universal application of NAND gates. Open files F05-16(a), (b), (c), and (d) to verify each of the equivalencies.




Figure 5–17 Universal application of NOR gates. Open files F05-17(a), (b), (c), and (d) to verify each of the equivalencies.




Figure 5–18 NAND logic for X = AB + CD.




Figure 5–19 Development of the AND-OR equivalent of the circuit in Figure 5–18.




Figure 5–20 Illustration of the use of the appropriate dual symbols in a NAND logic diagram.




Figure 5–21




Figure 5–22




Figure 5–23




Figure 5–24 NOR logic for X = (A + B)(C + D).




Figure 5–25




Figure 5–26 Illustration of the use of the appropriate dual symbols in a NOR logic diagram.




Figure 5–27




Figure 5–28




Figure 5–29




Figure 5–30




Figure 5–31




Figure 5–32




Figure 5–33




Figure 5–34




Figure 5–35 Simplified comparison of the VHDL structural approach to a hardware implementation. The VHDL signals correspond to the interconnections on the circuit board, and the VHDL components correspond to the IC devices.




Figure 5–36 Predefined programs for a 2-input AND gate and a 2-input OR gate to be used as components in the data flow approach.




Figure 5–37




Figure 5–38 Illustration of the instantiation statements and port mapping applied to the AND-OR logic. Signals are shown in red.




Figure 5–39




Figure 5–40 A VHDL program for a combinational logic circuit after entry on a generic text editor screen that is part of a software development tool.




Figure 5–41 A typical waveform editor tool showing the simulated waveforms for the logic circuit described by the VHDL code in Figure 5–40.




Figure 5–42 Illustration of a node in a logic circuit.




Figure 5–43 Open output in driving gate. For simplicity, assume a HIGH is on one gate input.




Figure 5–44 Open input in a load gate.




Figure 5–45 Shorted output in the driving gate or shorted input in a load gate.




Figure 5–46 Example of signal tracing and waveform analysis in a portion of a printed circuit board. TP indicates test point.




Figure 5–47




Figure 5–48 Fluid storage tank with level and temperature sensors and controls.




Figure 5–49 Karnaugh map simplification and implementation for the inlet valve logic.




Figure 5–50 Karnaugh map simplification and implementation for the outlet valve logic.




Figure 5–51




Figure 5–52




Figure 5–53




Figure 5–54




Figure 5–55




Figure 5–56




Figure 5–57




Figure 5–58




Figure 5–59




Figure 5–60




Figure 5–61




Figure 5–62




Figure 5–63




Figure 5–64




Figure 5–65




Figure 5–66




Figure 5–67




Figure 5–68




Figure 5–69




Figure 5–70




Figure 5–71




Figure 5–72




Figure 5–73




Figure 5–74




Figure 5–75




Figure 5–76




Figure 5–1 An example of AND-OR logic. Open file F05-01 to verify the operation. Thomas L. Floyd...

Documents

Transcript of Figure 5–1 An example of AND-OR logic. Open file F05-01 to verify the operation. Thomas L. Floyd...