FIFOAPP

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FIFO APPLICATIONSGUIDE

September 1999

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© 1999 Integrated Device Technology, Inc.

3 1999 Integrated Device Technology, Inc.

TITLE APPLICATION PAGENOTE NUMBER

FIFO Family & Part Number Application Note Cross Reference Table 5

Introduction to FIFO Memories 7

CUSTOMER SPECIFIC APPLICATION NOTESPCI Bus

Prototyping System/ Algorithm Accelerator Utilizing the IDT72V36110 AN-243 11

HDTV & Image ProcessingApplication of the IDT72V2113 High Density FIFO within an HDTV Encoder AN-244 15

Medical EquipmentApplication of the IDT72V2105 FIFO within an X-Ray Image Processing System AN-245 17

GENERAL APPLICATION NOTESSuperSync II Mid-Bus FIFO - The Solution to High Density FIFO Requirements AN-242 25within 36 Bit Bus Applications

Operating FIFO's on Full and Empty Boundary Conditions TN-08 27

Cascading FIFO's or FIFO Modules TN-09 29

Width Expansion of SyncFIFO's AN-83 32

Using IDT SyncFIFO's as Parallel Data Delay Lines AN-122 37

Serial Programming of SuperSync FIFO Flag Offsets: A State Machine Approach AN-130 42

Dual SyncFIFO Applications using the IDT728x1 and IDT728x5 AN-134 59

ADDITIONAL INFORMATIONThermal Performance Calculations for IDT's Packages 73

TABLE OF CONTENTS


FIFO FAMILY PART NUMBER DESCRIPTION APPLICATION PAGENOTE #

SUPERSYNC II 72V36110 PCI BASED ALGORITHM ACCELERATOR AN-243 11

SUPERSYNC II 72V2113 HDTV ENCODER SYSTEM AN-244 15

SUPERSYNC II 72V2105 X-RAY IMAGE PROCESSING AN-245 17

SUPERSYNC II 72V3660/3670/3680 36 BIT MID-BUS REPLACES SUPERSYNC AN-242 253690/36100/36110

SUPERSYNC 72V255LA/V265LA SERIAL PROGRAMMING OF FLAG OFFSETS AN-130 4272255LA/265LA72V261LA/V271LA72261LA/271LA

SYNCFIFO 72V2X5/ 722X5 WIDTH EXPANSION OF SYNCFIFO'S AN-83 3272V2X1/ 722X1

SYNCFIFO 72V2X5/ 722X5 USING SYNCFIFO'S AS PARALLEL DATA AN-122 3772V2X1/ 722X1 DELAY LINES

DUAL SYNCFIFO 72V8X5/728X5 DUAL SYNC FIFO APPLICATIONS AN-134 5972V8X1/728X1

ASYNC FIFO 7201 - 08 SYNC FIFO OPERATION AT THE FULL & TN-08 27EMPTY BOUNDARY CONDITION

ASYNC FIFO 7201 - 08 CASCADING ASYNC FIFO'S TN-09 29

Application Note and FIFO DeviceCross Reference


FIFO MemoriesA FIFO is used as a "First In-First Out" memory buffer between two

asynchronous systems with simultaneous write and read access to andfrom the FIFO, these accesses being independent of one another. Datawritten into a FIFO is sequentially read out in a pipelined manner, suchthat the first data written into a FIFO will be the first data read out of theFIFO. So, the fundamental architecture of a FIFO has an input (write)port, and an output (read) port. Each port has its own, associated pointerwhich points to a location in memory, after a FIFO reset both write andread pointers will be at the first memory location within the FIFO. Everywrite operation will cause the write pointer to increment to the nextlocation in memory, similarly every read operation will cause the readpointer to increment to the next location in memory. FIFO write and readoperations will loop in a circular fashion, from the last memory location tothe first memory location without the need for any kind of read or writepointer reset.

FIFO status flag outputs are a function of the comparison of therespective write and read pointers. A FIFO will always have some statusflag outputs; at least a flag that indicates the empty condition and a flagthat indicates the full condition. An empty flag is asserted when the FIFOmemory is empty. This is generated by the comparison of the write andread pointers and results in the number of memory locations betweenthem being zero, (i.e. when they are at the same memory location). A fullflag is asserted when the FIFO memory is full. This is generated by thecomparison of the write and read pointers results in the number ofmemory locations between them being the maximum FIFO depth, thewrite pointer is 'D' locations ahead of the read pointer, where D is theFIFO depth. Note, a FIFO that is full cannot be written in to and a FIFOthat is empty cannot be read from.

IDT FIFO's can be either Synchronous or Asynchronous, thefundamental difference between the two being the presence of clockinputs on the Synchronous FIFO's, the Asynchronous FIFO's have noclock inputs. The entire operation of a Synchronous FIFO is dependenton the application of a either a write clock signal or read clock signal. IDToffers a wide variety of FIFO's available in many densities providingvarious widths and depths. Data bus widths vary from 1 bit to 72 bits andFIFO depths vary from 64 to 512,000. IDT's range of FIFO's alsoincludes many different grades of performance and feature offerings. IDTFIFO's are available as Uni-directional devices (where data flow througha FIFO is in one direction only), or Bi-directional (data can flow in bothdirections through the FIFO). IDT provides specialty FIFO's whichinclude 'Parallel-to-Serial' and 'Serial-to-Parallel' FIFO's. Here the datainput to, or the data output from a FIFO can be either a parallel databus or serial bit stream.

IDT's FIFO Family TreeIDT has three main FIFO families, Asynchronous FIFO's, Synchro-

nous FIFO's (both families being Uni-Directional) and Bi-DirectionalSynchronous FIFO's. Asynchronous FIFO's have no clock input for eitherthe read or the write operations. Data is written into or read from the

FIFO based on an Asynchronous edge triggered input. AsynchronousFIFO's do not offer the same level of performance or feature set as theSynchronous FIFO families, but due to their simplicity they are stillcommonly used. They have densities up to 512Kbits. AsynchronousFIFO's are Uni-Directional.

The Synchronous FIFO family has seen a number of developmentsover the years. The first Synchronous FIFO family, SyncFIFOTM , hasimproved performance and some added features when compared to theAsynchronous FIFO's, but has the main difference of read and writeclock inputs. IDT's SyncFIFO's have maximum clock speeds of 100MHzand a maximum density of 64Kbits. IDT also has the SuperSyncTM

FIFO, which offers better performance and added features whencompared to SyncFIFO's. SuperSyncTM FIFO's are available in speedsup to 100MHz and densities up to 4Mbits. IDT's latest and industryleading FIFO is the SuperSync IITM family. This again has improvedperformance and added features when compared to SuperSyncTM

FIFO's. Supersync IITM offers speeds up to 133MHz, densities up to4Mbit and the most comprehensive set of FIFO features to date. Thisfamily has an architecture and packaging selection that will allow thefamily to be further developed in terms of speed, density and features.In the future we expect to achieve speeds up to 200MHz and 18Mbitdensity with the continued development of SuperSync IITM FIFO's .These FIFO's are all Uni-Directional.

The final family are the Bi-Directional FIFO's. These are capable of36 bit bus widths with Bus Matching options. This family also includesthe TripleBusTM FIFO, which connects two 18 bit wide Uni-Directionalports (one is an input port, the other an output port), to a single 36 bitwide Bi-Directional port.

As mentioned above, IDT's latest FIFO family is the industry leadingSuperSync IITM. This family of FIFO's offers three groups, 'Narrow Bus'(x9/ x18 bus width), 'Mid Bus' (x36) and the 'Extended Bus' (x72).SuperSync IITM offers the best FIFO performance and also offers manyfeatures that are common to all groups. Newly added features on theSuperSync IITM FIFO's include:a) Bus Matching, the FIFO input and output bus widths can be different;b) Endian control, to determine the byte arrangement during BusMatching; c) Eight programmable flag default values, are selectedduring Master reset; d) Retransmit with zero latency;e) Synchronous or Asynchronous programmable flag operation;f) Serial or parallel loading of the flag offsets. Default values are alsoavailable.Also, the 'Extended Bus' FIFO will introduce some new features to FIFOdevices, these include:i) Separate clock input for serial flag offset loading;ii) JTAG - provides 'Boundary Scan' of the FIFO;iii) Synchronous output enable, synchronized to the read clock;iv) 256 pin, fine pitch BGA package.

IDT selects leading edge, industry standard semiconductor pack-ages. Packaging types include standard plastic DIP and CERDIP,surface mount ceramic LCC, PLCC, SOIC, TQFP and STQFP. IDT's

An Introduction to FIFO Memories and their Applications

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package development is committed to board space saving packages,this is highlighted in the SuperSync IITM family of FIFO's, where 80 pinand 128 pin TQFP packages are used. This family will also include a256 pin fpBGA (fine pitch BGA) package for its 72 bit wide device, forthe first time in a FIFO, this device will include JTAG, this allows forthe implementation of a Boundary Scan function. Dual packaging forFIFO's is also available. Here, two discrete FIFO's are packagedtogether to save board space. IDT FIFO's are available with standardpower supply voltages of 3.3V and 5V. Also, Industrial, Military andCommercial temperature grades are available.

IDT is committed to supplying the communication and networkingcommunities with high performance, feature rich FIFO products. IDTstrives to provide the highest level of product support and customerservice, FIFO product development includes a large degree offeedback, which takes into consideration customer needs and futureneeds. With the continued development of IDT FIFO products and inparticular the SuperSync IITM family, the future offerings of IDT FIFO'slook very exciting.

General FIFO ApplicationsThe sequential operation of a FIFO is particularly useful for

performing any number of system level functions that include, PacketBuffering, Frequency Coupling, and Bus Matching.

Packet Buffering – Data written into the FIFO can be stored untilthe system on the output of the FIFO is ready to accept the data.Here data input to a FIFO from a digital source are buffered until thereceiving network is ready to read the data. This is particularly usefulin network switching or routing arrangements where several FIFO’shave discrete input busses, but all FIFO outputs are connected to acommon bus. The outputs of the FIFO’s are ‘polled’ for data by thereceiving system.

Frequency Coupling – Data may need to be transferred from onefrequency domain to another. That is, data may be transmitted from adigital system running on a particular clock frequency and receivedby a system running at a different frequency. Here the FIFO providesfrequency coupling, taking data in at one rate and outputting it atanother. The input and output data rates of the FIFO being controlledby the discrete Read and Write clock signals.

Bus Matching – Data transfer may need to take place betweenseparate digital domains with different bus widths. Here the FIFO actsas a bridge between the domains, channeling the data from the inputof a particular bus width, to the output with another bus width. Busmatching is a feature that is easily setup on the SuperSync IITM familyof FIFO's. All IDT FIFO's can be easily cascaded to provide greaterdepth and expanded in width to give wider data busses.

This Application Guide will show some typical customer FIFOapplications, as well as provide some useful FIFO Application Notes.The guide will continually be updated and added to, and later versionspublished.

A Brief History of IDT FIFO'sIn the early 1980s, FIFOs were nothing more than a bank of

parallel shift registers, 4 or 5 bits wide and 8 to 64 nibbles deep.Within these FIFOs, data ripples from one register to the next, andthe FIFOs thus suffered from long data latency.

By replacing the registers with dual-ported memory cells, FIFO

vendors boosted densities and reduced latencies. The FIFO’s internalcounters kept track of the location that was being written to and thelocation that was available to be read. FIFO control logic used thestatus of the counters to provide flag information. With this approach,data written into the FIFO became available for reading almostimmediately, and the size of the memory array was independent of theFIFO’s throughput.

Designers found that when using these faster devices, it was difficultto take full advantage of the memory capacity because the FIFO offeredonly full and empty flags. The addition of a programmable flag functionallowed designers to set the exact full/empty points needed to compen-sate for system pipeline delays. If a system requires three clock-cycledelays to recognize a flag, for example, the flag could be programmedto full minus 3 or empty plus 3. Programmable flags therefore increaseperformance and simplify system design.

To accommodate a wider variety of applications, today’s FIFOarchitectures offer features such as bus matching; mark and retransmit;serial load of programmable flag settings; and partial reset — all IDTinnovations. To save board space, IDT also offered the first bidirectionalFIFOs by putting two back-to-back FIFOs in one package.

Increases in system speeds have required more dramatic architec-tural changes. For example, a synchronous interface (also introducedby IDT) moves data in or out only on a clock edge rather than on anasynchronous read or write enable signal. The synchronous interfaceeases the interface timing and signaling requirements, as well asimproving the device cycle time.

System speed increases and the need to interconnect systems thatrun at radically different speeds have also resulted in the need forhigher-capacity FIFOs. Because the use of 6- or 8-transistor dual-portmemory cells limits FIFO capacity, some FIFOs have moved to 4-transistor single-port SRAM cells. Known as SuperSync devices, theseFIFOs outwardly function like any other FIFO but offer capacities ashigh as 4 Mbits. Internally, SuperSync FIFOs still use small blocks ofdual-ported memory to decouple the inputs and outputs from the mainbank of single-ported SRAM blocks. These FIFOs use complex internalstate machines to monitor counters for multiple memory boundaries,two variable clock boundaries (read and write), the state of the flaglogic, and pointers for the retransmit function, all of which is transparentto users.

Even more complex FIFO architectures will further improve speed,latency, and capacity without major cost increases. One such architec-ture, known as SuperSync II from IDT, employs small three-portmemories to implement the traditional FIFO input and output along with

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Customer SpecificApplication Notes

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CUSTOMER SPECIFIC APPLICATION NOTES

PCI BusPrototyping System/ Algorithm Accelerator Utilizing the IDT72V36110 AN-243 11

HDTV & Image ProcessingApplication of the IDT72V2113 High Density FIFO within an HDTV Encoder AN-244 15

Medical EquipmentApplication of the IDT72V2105 FIFO within an X-Ray Image Processing System AN-245 17


JUNE 1999

Features of Report

♦♦♦♦♦ This application utilizes the IDT72V36110, 128K x36 FIFO♦♦♦♦♦ Bus Matching is performed – a 32 bit PCI bus is connected to a

16 bit data bus♦♦♦♦♦ Frequency Coupling is utilized, WCLK and RCLK are at

differing speeds

OverviewThe FIFO’s are used to buffer data going to and from a PCI bus to

the PRPB (PCI-based Rapid Prototyping Board), data processingsystem, this system is actually an “Algorithm Accelerator” based on theRPP (Rapid Prototyping Platform), which is a product of the systemdeveloper. A typical application would be to run a complex DSP type ofalgorithm, such as vocoders and modems.

This application shows how an IDT FIFO in conjunction with a PLDdevice is used to implement a PCI bridge. This offers a solution overusing conventional PCI bridge devices which would limit the functional-ity of this application. This application is a computationally intensiveapplication, requiring high intensity data transfer flow between theprocessing system and the PCI bus, therefore a large FIFO buffer is

FIGURE 1. PRPB BLOCK DIAGRAM

required, this is typical of many DSP type applications. A standard PCIbridge chip, such as the PLX 9080 device has a relatively shallow FIFOmemory, 32 bits wide by 32 long words deep. The IDT72V36110 FIFOprovides a 128K deep FIFO memory, which is adequate for thisapplication.

IntroductionThe hardware Rapid Prototyping Platform (RPP) attempts to bridge the

concept with implementation. It provides a metric for gross decision-making—on such aspects as the feasibility of the scheme’s complexity andthe partitioning between the hardware and firmware boundaries. For a givenalgorithm say there are certain tasks that are time critical and requireenormous computations, like codebook search in the voice processing, itwould be ideal to relegate these types of duties to the hardware where asother functions of the vocoder can be carried out by firmware. The hardwarecan concurrently search for the best or optimal vector while say the gainshape of the vector can be estimated by firmware since the estimateinvolves variable parameters only some of which are used at a giveninstance, this would be ideal to implement by firmware. The other metricsare traditional such as power consumption and cost to implement a functionetc...The RPP is also an algorithm accelerator that is flexible,

DSC-2679/7

Application of the IDT72V36110 FIFOwithin a Prototyping System/AlgorithmAccelerator. Utilizing a PCI BasedArchitecture.

APPLICATIONNOTE

AN-243

Processor

Module

Control

and Data

Interface

ClockDistribution

Power Distribution

+2.5V +3.3V

RecoveredBus Clock

External

Clock

Reference

External

Signals

Interface

PCI Bus

+2.5V

+3.3V

Low-Skew Clocks

Bi-directional

Parallel

Port

FIFO 1

FIFO 2

32

16

16

PLL

Skew Control

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expandable, and portable. Simulated impairments may be encoded into thetest bed and run in real-time. The processed data may then be stored forother post-processing or displayed for prompt visual inspection, such asduring an onsite customer’s demonstrations.

The PCI-based Rapid Prototyping Board (PRPB) consists of severallogical entities as shown in Figure 1. The Processing Module (PM) containsall the array of processors with their associated memory support. The PMmay be configured to provide a customized processor through the PCI bus.The actual data that the PM needs to process and the manipulated data afterbeing processed both travel through the PCI bus. The Control and DataInterface (CDI) primary responsibility, then, is to transfer data from and to thehost’s PCI bus while also providing the necessary board’s administrativecontrolling logic. The Clock Distribution (CD) network ensures that thedevices within the PM and the CDI receive clocking with no skew and at theproper frequency. The Power Distribution (PD) provides the power supplyconditioning throughout the PRPB. The CD network comprises of a 'SkewControl' element and a PLL (Phase Lock Loop), the PLL can be set-up forany frequency up to 160MHz as required by the different processor modulesthat can be tested.

Application of FIFOFrom Figure 2 we can see that the FIFO provides data buffering

between the PCI bus and the processors, the FIFO is performing both BusMatching and Frequency Coupling. The FIFO on the board is used largelyto benefit from its ability to pass data between the two data buses that areasynchronous from each other. This is particularly useful when passingdata between two systems, each operating at different frequencies, theincoming data needs to by synchronized to the local clock before use.Therefore by passing the data through the FIFO stage the synchronizationis done automatically. In the current design this feature is particularly usefulto synchronize data coming of the PCI bus to the board or system clock priorto distributing the data to Processing Element. The FIFO’s used on theboard are two unidirectional FIFO devices, the IDT72V36110 which are128K x 36. One FIFO provides link from PCI world to the board and the otherfrom the board to PCI world. The FIFO also has a flexible x36/x18/x9 busmatching feature on both the read and write ports of the device.

The device can be operated in two modes, Standard IDT mode or FirstWord flow through (FWFT) mode. The FIFO F1 connects ProcessingElement to PCI Interface, which is used to transfer input data to the

FIGURE 2. CONNECTION DIAGRAM

IDT APPLICATION NOTE AN-243

PC I

Interface

IDT72V36110

32

16

PC I Bus

ProcessingElement

I/PPort

O /PPort

FIFO 1

32

Q 0-Q 15

D0 - D15

D18 - D33

66M Hz

ALTERA

10K 100A

RCLKW CLK33M H z

IDT72V36110

16

FIFO 2

32

D0-D15

Q 0 - Q15

Q 18 - Q 33

66M HzW CLKRCLK

33M H z

33M Hz

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BUS MATCHING SIGNAL FOR FIFO F1 (PCI TO PROCESSING ELEMENT)

BM IW OW WRITE PORT WIDTH READ PORT WIDTHH L H X 36 X 18

BUS MATCHING SIGNAL FOR FIFO F2 (PROCESSING ELEMENT TO PCI)

BM IW OW WRITE PORT WIDTH READ PORT WIDTHH H L X 18 X 36


processing array. The FIFO F2 connects PCI Interface to ProcessingElement which is used to transfer processed data to the PCI bus or externalworld. Figure 3 shows the block diagram of such a connection and logicalsignal flow between FIFO’s, Processing Element and PCI Interface. Thecontrol signals can be say classified as those related to read/write signalsand status monitoring signals and other control signals related to busmatching. The Processing Element generates all the read signals for FIFOF2, including the clock signal. All the status monitoring signals such as FIFOempty, FIFO partially empty signals or re-transmit signals are monitored byProcessing Element. It also generates the appropriate write signals forFIFO F1, including the write clock signal. All status monitoring signals suchas FIFO full, FIFO partially full are controlled by Processing Element.Conversely on the other side, the PCI Interface generates write relatedsignals for FIFO F2 and read signals for FIFO F1. However both the readand write clocks are generated by the Injection Lock Loop (ILL), rather thanfed from the PCI clock. Since the PCI Interface does not have a local PLLand the clock can only be taken out via a flip flop there by the frequency atwhich FIFO can operate is PCI clk /2 , i.e at 16.66 MHz (given that PCI clockoperates at 33MHz). Thereby the through put of the FIFO is effected, so inorder to maintain at least PCI clock rate the clock to the FIFO’s from PCIInterface end comes from the Injection Lock Loop, (which runs at 33MHz). All the bus matching related signals and internal programmable registersare controlled by the PCI Interface. The FIFO’s are reset from the PCIInterface via the master reset signal.

The clock frequency between the FIFO and the PCI bus is 33MHz, thefrequency between the FIFO and the Processor Module is variable, but willbe less than 100MHz. This is Frequency Matching, the PCI bus runs at33MHz into one port clock of each FIFO, the other clock of each FIFO istypically running at twice the PCI frequency, around 66MHz.

Bus MatchingThe bus matching feature of the FIFO is particularly useful in connecting

data buses of uneven width. This feature is used to match the data bus ofthe PCI world and the data bus to the processing array. There are tworeasons to for bus matching.

The data coming from the PCI bus is a burst of 32 bit words. The datafor the application does not require high bandwidth, thereby the ProcessingElement side does not require such a high bandwidth of data bus. So thereis no need to connect all 36 bits of bus on the output or input side of the FIFOon the Processing Element side. Translation of the 36 bit word to smallerword sizes is performed by the FIFO thereby shifting the burden away fromthe PCI Interface to the FIFO. There is a provision on the FIFO to selectwhich part of the small word can be shifted out first, Endian Control. FIFOF1 passes data from the 32 bit PCI bus to the Processor Module, thereforeits input port bus width is set-up for x36 and its output port width is x18. FIFOF2 takes data from the Processor Element and passes it to the PCI bus,therefore its input port is set-up for x18 and its output port is x36. The datafrom the processing array side can be read or written at twice the rate of thePCI bus and thereby maintain the throughput. The 32 bit word from the PCIbus is buffered in the PCI Interface and moved to the 36 bit input data busto the FIFO (the upper 4 bits can be zero). The FIFO splits the word into two18 bit words and can be read on the 18 bit output data bus whose clockfrequency can be different to the PCI clock frequency. Similarly two 18 bitwords are written into the FIFO prior to reading the 36 bit word. The settingsfor the bus matching signal for current configuration are tabulated below.For other bus configuration matching set ups refer data sheet forIDT72V36110.

The signal BE is used to select which half of the word needs to be readfirst during the read cycle . During reset if FIFO finds BE to be Low then BigEndian format is used if BE is high than little Endian format is used.

The 36 bit word can only be read after both the 18 bit words have written.This can be checked by sampling the Empty Flag. The empty flag will beasserted until both the 18 bit words are written, only after that it will be de-asserted.

14

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FIGURE 3. CONNECTION DIAGRAM

AD[31 :0 ]

C/BE#[3:0]

PAR

FRAME#

TRDY#

IRDY#

ST OP#

DEVSEL#

IDSEL

CL K

RST #

PERR#

SERR#

PRSNT1#

PRSNT 2#

GN D

INTA#

TDI

TDO

T CK

T MS

TRST#

REQ6 4#

ACK64#

TDI

TDO

FF1M RS#

FF1D[0 :35 ]

FF1W EN#

FF1FF#/IR#

FF1PAF #

FF1FSEL0

FF1FSEL1

FF1L D#

FF1OW

FF1IW

FF1BM

FF1PFM

FF1FW F T/SI

FF1BE#

D0-D35

W CLK

W EN#

FF2Q[0 :3 5]

FF2REN#

FF2 PAE#

FF2EF#/OR#

FF2OE#

FF2FSEL0

FF2FSEL1

FF2L D#

FF2OW

FF2IW

FF2BM

FF2PFM

FF2M RS#

FF2FW F T/SI

FF2RT#

FF2BE#

FIFO F1

IDT7 2V36 110

MRS#

OW

Q0-Q35

RC LK

REN#

PAE#

EF#

OE#

FSEL0

FSEL1

LD#

IW

BM

PF M

PRS#

FW FT/SI

RT#

SEN#

IP

HF#

BE#

FIFO F2

IDT7 2V36 110

D0-D17

W CLK

W EN#

FF#

PAF#

FF1Q[0 :17

FF1 RCLK

FF1 REN#

FF1 PAE#

FF2 D[0 :17 ]

FF2W CLK

FF2W EN#

FF2FF#

FF2PAF #

R M

Q0-Q17

RC L K

REN #

PAE#

EF #

O E#

RT#

Processing

Elem ent

GN T#

REQ#

Vcc

from IL L

from IL L

PCI in ter face

33MHz (R ef)

OW

FF#

PAF #

FSEL0

FSEL1

LD#

IW

BM

PF M

MRS#

PRS#

FW FT/SI

SEN#

IP

BE#

HF#

RM

FF1EF#

FF 1OE#

FF1 RT#

AL TER A

10K 100 PLD



15DSC-2679/7

JUNE 1999

Application of the IDT72V2113 FIFOwithin an HDTV Encoder

APPLICATIONNOTE

AN-244

Features of Report

♦♦♦♦♦ This application utilizes the IDT72V2113, 512K x9 FIFO♦♦♦♦♦ FIFO’s are used at numerous points within the design♦♦♦♦♦ Frequency Coupling is utilized, WCLK and RCLK are at

differing speeds♦♦♦♦♦ The FIFO operates in First Word Fall Through mode♦♦♦♦♦ Depth Expansion is performed

OverviewThe system described is an HDTV encoder. Within this system an

input video stream is compressed using MPEG2 and output as com-pressed HDTV video. The FIFO’s are used at various points within thepath, mainly to provide frequency coupling. The FIFO’s are setup in bothx9 and x18 configuration and are typically connected in banks to givedepths of 1Meg. The FIFO’s write and read clocks vary from 27MHz upto 74MHz. Read and write operations are performed on the FIFOsimultaneously.

ApplicationThe recent introduction of High Definition Digital Television (HDTV)

by U.S. major broadcasters created the need for very high performanceinfrastructure equipments such as audio and video compressors.Compression of the digital video pixel data, coupled with higher ordermodulation techniques, is necessary to fit the HDTV broadcast signalwithin the FCC allocated spectrum. The relatively high pixel samplerates and picture density, (compared with a conventional, digitized NTSC

FIGURE 1. SYSTEM BLOCK DIAGRAM - HDTV VIDEO COMPRESSOR

format television signal), leads to demanding requirements for databuffering and storage in a HDTV compressor. This is particularly true inthe case of equipment used at the network broadcast centers, where thehighest possible picture quality (and in turn, a high number of bits percompressed picture frame) must be maintained, because a signal mayundergo several concatenations of encoding and decoding by affiliatestations prior to delivery to the home. A block diagram of a HDTV videoencoder section is shown in Figure 1. Please refer to Table 1 forcorresponding read and write clock frequencies for the FIFO's shown inFigure 1.

In order to compress the raw digitized video data using theAdvanced Television Standards Committee (ATSC) specified MPEG-2algorithm, it is first necessary to capture a field or frames worth of activevideo pixel data (data in the equivalent of the horizontal and verticalblanking regions is not used here). At this time, there are two broadcaststandards preferred for prime time HDTV. There is an interlaced formatcarrying 1920 horizontal pixels by 1080 lines in two fields of 540 lines at60 fields per second called the 1080i format. There is also a progressiveformat carrying 1280 pixels by 720 lines at a 60 frame per second rate.In both formats, 20 bit pixel data (10 luminance and 10 chrominance) issampled at 74.25MHz. Thus, a field or frame buffer must be capable ofholding over 20Mbits in the case of 1080i, and must maintain sustainedwrite speeds of 74.25MHz during the active video scan time. This isover three times the depth required for conventional NTSC field buffersat a sample rate 2.75 times faster. Specialized DRAM based field bufferFIFOs typically used in the video industry do not have the requireddepths, are difficult to cascade, and cannot meet the speed require-ments.

SMPTE-292MBit Stream(Video In)

VIDEOPARSER

MPEG-2COMPRESSOR FIFO

9 PARALLELPROCESSORS

TILESTITCHING

OUTPUTPROCESS

Compressed

FIFO

FIFO FIFO

MPEG-2COMPRESSOR

FIFO

HDTV Video

16

(8 LUMA)(8 CHRO MA)

VIDEO CAPTUREBOARD

16



www.idt.com

Table 1. Respective FIFO WCLK and RCLK Frequencies:

Video Parser è FIFO è MPEG-2 WCLK=74.25MHz; RCLK=63MHzMPEG-2 è FIFO è Tile Stitching WCLK=63MHz; RCLK=54MHzTile Stitching è FIFO è Output Process WCLK=54MHz; RCLK=27MHzOutput Process è FIFO WCLK=27MHz; RCLK=27MHz

A cascade of IDT’s SuperSync II FIFOs proved to ideally satisfy therequirements. As shown in Figure 2, the pixel data can be logicallypartitioned into luminance and chrominance channels and storedseparately for ease of processing. Thus, two banks of 10Mbits, or1Mword each is required to completely hold one 1080i field. A depthcascade of two IDT72V2113 parts at 512K words each is sufficient tomeet the depth requirements. Next, the word width of 10bits must besatisfied. While width expansion using SuperSync II FIFOs is easilyaccomplished by additional parts, it is desirable to reduce system partscount. In this case, we recognize that the MPEG-2 algorithm onlyoperates on 8-bit data samples, so the original 10-bit pixel data may berounded to 8 bits, fitting nicely into 9-bit wide FIFOs.

In Figure 1, a number of parallel MPEG-2 processors are shown,each of which compresses a tile of the larger HDTV picture. These tilesmust be “stitched” together in a manner which allows for seamlessmotion of objects between tiles. SuperSync II FIFOs may be exploitedhere for their depth, comparatively low parts count, and high speed

access to accommodate bursty data from the compression engines.Similarly, fast access FIFOs are required to act as rate buffers betweenthe picture processing block and the final output processing which mayoperate at disparate clock rates. The final output processing block inFigure 1 forms the Video Elementary Stream, or VES, which includeshigher level MPEG-2 required syntax elements such as presentationtime stamps, used at the receive end of the broadcast chain to lip syncaudio and video. The VES will be multiplexed with other bit streamssuch as Dolby AC-3 encoded audio, user data, and identification tablesin a broadcast grade HDTV encoder to form a final transport stream fordelivery to an RF modulator. While the read/write access requirementsfor the final output FIFO are low compared to the up-stream signalprocessing, the depth requirements of this FIFO can be very large.Once again, depth cascaded SuperSync II FIFOs are employed becausetheir industry leading 4Mbit density provides a significant parts countreduction over alternative implementations.

FIGURE 2. HDTV FIELD/ FRAME BUFFER

72V2113512K x9

IR

WEN

OR

REN

D0-D7

Q0-Q7

WCLK RCLK

72V2113512K x9

IR

WEN

OR

REN

D0-D7

Q0-Q7

WCLK RCLK

8 8 8LUMADATA IN

LUM ADATA OUT

EMPTY

WRITE ENABLE

WRITE CLOCK

FULL

READ ENABLE

READ CLO CK

72V2113512K x9

WEN

OR

REN

D0-D7

Q0-Q7

WCLK RCLK

72V2113512K x9

IR

WEN REN

D0-D7

Q0-Q7

WCLK RCLK

8 8 8CHRO MADATA IN

CHROMADATA OUT


17 1999 Integrated Device Technology, Inc. DSC-2679/7

JUNE 1999

Application of the IDT72V2105 FIFOwithin an X-Ray Image ProcessingSystem

APPLICATIONNOTE

AN-245

Features of Report

♦♦♦♦♦ This application utilizes the IDT72V2105, 256K x18 FIFO♦♦♦♦♦ Illustrates a deep FIFO requirement - 1.5M depth♦♦♦♦♦ FIFO depth expansion is performed♦♦♦♦♦ Frequency Coupling is utilized, WCLK and RCLK are at

differing speeds♦♦♦♦♦ Contains an analysis of FIFO depth based on input and

output data rates and packet size♦♦♦♦♦ FIFO is used in First Word Fall Through mode

OverviewThe system described In this report is used for predevelopment of

image processing algorithms, which enables testing of algorithms in realtime with a software only implementation directly connected to an X-raysystem. The system is made of 2 elements, the I/O element and theProcessing element, the IDT FIFO’s are used in the I/O element. The I/Oelement is bi-directional, within a given system there will always be an I/O at the front end (set-up for input) and one at the back end (set-up foroutput). In between there can be 1-8 Processing elements. Data is inputfrom a detector system and processed by the Processing Elements. datais then output from the back end one of the final Processing Element to adisplay system.

Previously, an I/O element in this design had two IDT72255 FIFO’s(18kx18) connected “anti-parallel” to create a bi-directional FIFObetween an image detector/display system and a DSP system (SHARC– Super Harvard Risc Computer). The main task of the FIFO’s was de-coupling of the clock domains (detector/display system and DSPsystem), a FIFO being ideal for this task. To adapt to the introduction ofan upgraded detector, producing an image peak data rate up to 100 MB/sec., the system needed extra memory in the DSP section to bufferimage data in order to have the DSP’s processing near to 100% of theavailable time. This would require a 1.5 M x 18, preferably dual portedmemory, running at 20 nsec cycles.

The IDT72V2105, 256K x 18 FIFO was utilized to provide this depth.This FIFO is pin and functionally compatible to the smaller density72V255 FIFO. A total 6 of these devices connected in depth expansionand two Altera PLD’s are used to implement the bi-directional portsbetween the detector/display-IO and SHARC-IO. The PLD's here selectinput or output of the FIFO’s to set the data direction.

Details of ApplicationThis report specifies the design of the hardware modules of the

multiprocessor-based real-time digital image processing subsystem fordynamic or static x-ray . The system is built of two basic hardwaremodules: the I/O Module and the Processing Module. Each basic moduleis placed on a discrete board. Both boards may be supplemented byadd-on boards for special functions. Any number of the two basic

modules - within physical limits - can be combined in order to meet theprocessing and data I/O requirements of the target application. Typicallya processing pipeline structure of the modules is applied.

The I/O module can be configured as image data input or as imagedata output. Hence, it is typically placed at the beginning and at the endof the pipeline. The module communicates with the system host via abidirectional control interface and with the image data source/ destina-tion. The communication in between all boards of the system is alwaysdone via dedicated SHARC links (Super HArvard Risc Computer),which is the ADSP21060 floating point DSP by Analog Devices.

The Processing Modules perform their function on the data derivedfrom the input I/O Module and pass the data to the subsequentProcessing Module in the processing pipeline or, for the last processingmodule, to the output I/O module. The maximum number of Processingmodules within an input and output is 8, so we can have 8x12=96SHARCs for image processing. The number of DSP’s used is deter-mined by the required processing power.

I/O ModuleThe I/O Module performs all image data input or output from/to the

system and the communication with the host. Its major tasks are:In Input Mode: it receives the image data stream coming in from theimage data source - e.g. a detector system – and performs a datadistribution to the subsequent DSP processing nodes located on theProcessing Modules.In Output Mode: it performs collection of the processed image datafrom the processing nodes and the transmission to data destination e.g.a display system.

In both modes the I/O Module performs a decoupling of the imagedata streams between the image source, the processing unit and theimage destination utilizing a FIFO's functionality.

The I/O module also performs the control interfacing to the host ofthe system. At first the commands coming from the host are respondedto on interface level. Then they are passed to the command destinationusing the same data paths through the pipeline as the image data usingthe Message Passing mechanism. Any answer from the destinationnode to the host goes again via an I/O Module.

The I/O Module includes a Generic Image Data Interface, (GIDI). Asmentioned above, an application dependent image data interface canbe added as an add-on board.

Refer to Figure 1 'Block Diagram - I/O Module', this shows datainterface elements bridging between the GIDI and DSP nodes. Here thedata interface section utilizes 72V2105 FIFO's (connected in depthexpansion) to buffer data that passes in both directions between theGIDI and DSP nodes. More detail is gived in the remainder of thisreport.

18

FIGURE 1. BLOCK DIAGRAM - I/O MODULE

Generic Image Data InterfaceThe Generic Image Data Interface (GIDI) is a 32 bit high speed image

data port connected to the two busses of the SHARC DSP nodes on theI/O Module. The GIDI is divided into two channels, each channel includes16 bits of pixel data and 10 control signals. Each channel can be used asinput or output. However, in this system, both channels operate in thesame direction always. The mode of operation depends on the input/output function of the I/O Module selected via SHARC DSP software.

Protocol for GIDI in Input Mode.Refer to Figure 2 'Detailed Diagram of GIDI & Data Port Interface'. An

I/O channel is set to INPUT mode by setting Direction_x to LOW.Img_End_x will be set inactive by the DSP to initiate an image input (oroutput run). The 'Data Port Interface' consists of the Altera PLD and abank of IDT FIFO's. The interface (FIFO) will set /IR_x to indicate that itis ready to accept data. A data word is written into the interface when /IR_x and /WEN_x are active during the rising edge of CLOCK_x. Whenthe last data word is read by the DSP from the FIFO, Img_End_x isasserted again to indicate that the image is complete. In input mode, theFIFOs will request more data then the DSP is going to read at thismoment. This data has to be flushed from the FIFO to the DSP beforethe next image starts. The image source must be capable of handlingthis additional request. The /PAF_x signal can be used to prevent aninput overflow. The DSP software has to react within the time the datasource takes to fill this buffer space. Writing into the interface can bestopped or slowed down until /PAF_x is de-asserted. Note the /OE_xmust be high when the GIDI operates as input.

Protocol for GIDI in Output Mode.An I/O channel is set to OUTPUT mode when Direction_x is set

HIGH. Img_End_x will be set inactive by the DSP to initiate an imageinput (or output run). The interface (FIFO) sets /OR_x as soon as imagedata is available for output. A data word is read from the interface when/OR_x and /REN_x are active during the rising edge of CLOCK_x.When the last data word is read from the interface, Img_End_x isasserted to indicate that the image is complete. The /PAE_x signal canbe used to prevent an input underflow. The DSP software has to reactwithin the time the data source takes to empty this buffer space.Reading from the GIDI can be stopped or slowed down until /PAE_xbecomes de-asserted again. The /OE_x signal can be used to preventbus collision when the GIDI changes direction.

I/O FIFO'sThree FIFOs per input channel are implemented in order to decouple

the DSP system clock from the external data clocks. See also Fig. 1and Fig. 2. The FIFOs allow the system to relax data bursts at the inputor output, thereby yield an optimized load for the processors. Acalculation for the most demanding mode allows us to determine aminimum FIFO capacity that is required to bridge the data gap betweentwo successive images.

Image size: 4.62 MpixImage speed: 7.5 Img/secClock rate: 50 Mpix/sec.

Generic Im age Data Interface

Data I/F

DSP Block 0

HostInterface

0(SC SI)

Sharc Link 0..5 Sharc Lin k 0..5

DSP Block 1

HostInterface

1(SC SI)

Signa lBus

DoseControl

Data I/F

Data Port Data Port

FIFO FIFO

Im age D ata Interface Data InterfaceData Interface


19

Channel_0 includes DATA(15..0) for pixel data and control signals: CLOCK_0 Continous clock input range 100 kHz up

to 40 Mhz. Direction_0 Input/Output mode selection;

to be selected during system startup only. Img_End_0 End of Image controlled by DSP

/OE_0 Image data DATA(15..0) outputs enable

/OR_0 FIFO Output Ready /PAE_0 FIFO buffer Almost Empty /REN_0 Read Enable /IR_0 FIFO Input Ready /PAF_0 FIFO bufferAlmost Full /WEN_0 Write Enable DREQ_0* DMA Request DACK_0* DMA Acknowledge

Channel_1 includes DATA(31..16) for pixel data and control signals:CLOCK_1 Continous clock input range 100 kHz up to

40 MHz. (equal rate as CLOCK_0)Direction_1 Input/Output mode selection. Should not be used

dynamically.Img_End_1 End of Image controlled by DSP/OE_1 Image data DATA(15..0) outputs enable/OR_1 FIFO Output Ready/PAE_1 FIFO buffer Almost Empty/REN_1 Read Enable/IR_1 FIFO Input Ready/PAF_1 FIFO buffer Almost Full/WEN_1 Write EnableDREQ_1 DMA RequestDACK_1 DMA Acknowledge

Note: * The GIDI provides extra signals to handle DMA transfers. These signals may be used to simplify the handling of devices supporting DMA placed on the adapter module.

TABLE 1. SIGNALS ASSOCIATED WITH THE GIDI CHANNELS

TABLE 2. SIGNALS REQUIRED FOR IMAGE INPUT & OUTPUT

Channel_0 input Channel_1 input Channel_0 output Channel_1 outputDirection_0 =low Direction_1 =low Direction_0 = high Direction_1 = highImg_End_0 Img_End_1 Img_End_0 Img_End_1DATA(15..0) DATA(31..16) DATA(15..0) DATA(31..16)/WEN_0 /WEN_1 /REN_0 /REN_1/IR_0 /IR_1 /OR_0 /OR_1/PAF_0 /PAF_1 /PAE_0 /PAE_1/OE_0 = high /OE_1 = high /OE_0 = low /OE_1 = low

Optimized FIFO capacity must be: 4.62 – (4.62)2 * 7.5 / 50 =1.42 Mpixels(A derivation is provided at the end of the report).

FIFO Clock Speeds:When the FIFO is at the input to a system:WCLK = 0 – 40MHz and RCLK = 25MHz

When the FIFO is at the output of a system:WCLK = 25MHz and RCLK = 0 – 40MHZ

FIFO access from the GIDI Interface.The GIDI Interface control is implemented in the GIDI_IF-EPLD. The

EPLD is located between the image data I/O and the FIFO. It managesthe FIFO read and write access. The GIDI interface supports one cycleaccesses to or from the FIFOs.

FIFO access from the Data Port InterfaceThe data port interface is a memory mapped I/O system towards the

FIFO and the data port. It monitors the FIFO flags, supports the I/O fromand to the FIFOs and to/from the data port connector.


20

FIGURE 2. DETAILED DIAGRAM OF GIDI & DATA PORT INTERFACE

sharc_bus_0

direction

image_end_0

oe/

ren/

data[15..0]

/or_0

/pae_0

/paf_0

/wen

clock_0

/ir_0

clock_0

DATA PORT

ALTERA EPLD

EPM

7256TQC208-7

FIFO 0..2

IDT72V2105256K x 18

fifo_flags_1

fifo_flags_0

GIDI_IF

ALTERA EPLD

EPM

7128SQC100-7

fifo_data_out[15..0]

fifo_data_in[15..0]


fifo_data_in [15..0]

sharc_bus_1

direction

image_end_0

oe/

ren/

data[15..0]

/or_0

/pae_0

/paf_0

/wen

clock_0

/ir_0

clock_0

DATA PORT

ALTERA EPLDEPM

7256TQC208-7

FIFO 0..2

fifo_flags_1

fifo_flags_0

GIDI_IF

ALTERA EPLD

EPM7128SQC100-7


fifo_data_in[15 ..0]


fifo_data_in [15..0]

Bank of 3

GENERIC

IMAGE

DATA

INTERFACE

IDT72V2105256K x 18

Bank of 3




www.idt.com

FIFO Depth DerivationRefer to Figure 3 'Input and Output Data Rate'. The FIFO data

contents will increase according to the slope r of the solid line. At inputspeed r, an image size C is written into the FIFO after C/r seconds.When the image speed is v, the next image input will start after 1/vseconds. At this time the FIFO has to be read empty! Now we can drawa (dashed) line, that represents the continuous readout speed with slopeC*v. The distance between the lines represents the amount of data inthe FIFO at any time. The FIFO is maximum filled at time C/r. It is nowobvious, that the required fifo capacity is defined by C – x

C = Image size: 4.62 Mpixv = Image speed: 7.5 Img/secr = Clock rate: 50 Mpix/sec.

FIFO Capacity = C – x.

x = (C*v ) * C/r = C2 * v / r

FIFO Capacity = C – (C2 * v / r) = 4.62 – ((4.62)2 * 7.5 / 50) = 1.42Mpixels.(Note that C*v must be less then the SHARC bus speed)

FIGURE 3. INPUT AND OUTPUT DATA RATE

Accumulated

data

Time

r

C*v

C/r 1/v

x

C

0

Next image


23

General ApplicationNotes

24

GENERAL APPLICATION NOTES

SuperSync II Mid-Bus FIFO - The Solution to High Density FIFO Requirements AN-242 25within 36 Bit Bus Applications

Operating FIFO's on Full and Empty Boundary Conditions TN-08 27

Cascading FIFO's or FIFO Modules TN-09 29

Width Expansion of SyncFIFO's AN-83 32

Using IDT SyncFIFO's as Parallel Data Delay Lines AN-122 37

Serial Programming of SuperSync FIFO Flag Offsets: A State Machine Approach AN-130 42

Dual SyncFIFO Applications using the IDT728x1 and IDT728x5 AN-134 59


JUNE 1999

IDT72V3660-110 MID-BUS FIFO:The IDT72V3660-36110 Mid-Bus FIFO can be configured as 36 bit wide

input/ouput busses, with word depths from 4K to 128K. Both Read andWrite clock frequencies up to 100MHz can be applied. The Mid-Bus seriesof FIFO's is the ideal FIFO for applications requiring a deep FIFO for 36 bitwide busses. Where previously one may have performed width expansionof two IDT72V255LA-65LA SuperSync FIFO's to obtain FIFO depths up to16K with a bus width of 36 bits, this can now be much more easily achievedusing the new SuperSync II Mid-Bus device. Figure 1 below shows the basicconnections to the Mid-Bus FIFO.

The IDT72V255LA is an 8Kx18 FIFO, the IDT72V265LA is a 16Kx18FIFO, both are capable of 100MHz operation. Two of these devices can beconfigured in Width Expansion to give x36 bit bus width, (provided it is thesame part, giving the same depth). For a 36 bit application where twoIDT72V255 devices would have previously been the solution, theIDT72V3670 should now be applicable. The V255 and V3670 options bothprovide 8K depth. In contrast, a V265 combination should now be replacedby an IDT72V3680, both options here providing 16K depth.

ADVANTAGES:The advantages of using the SuperSync II family of Mid Bus devices

over the SuperSync, 72V255LA/265LA parts are:♦♦♦♦♦ Reduction in cost and board space used♦♦♦♦♦ Reduced Power consumption♦♦♦♦♦ No need for Width Expansion♦♦♦♦♦ One device can provide a 36-bit bus width with a depth of

4K up to 128K♦♦♦♦♦ A single 72V3670 can replace two 72V255LA parts

(or a 72V3680 can replace two 72V265LA's)♦♦♦♦♦ No External Flag Logic is required♦♦♦♦♦ No reduction in operating speed, capable of 100MHz

MID-BUS DIAGRAM

Figure 1. The IDT72V3660-110 - 36 bit FIFO

Easy to ImplementWhen comparing the implementation of the new SuperSync II, Mid-Bus

FIFO to the older SuperSync IDT72V255-65LA in a system design, thereare a number of advantages that should make the Mid-Bus the naturalchoice. The first advantage offered by the new Mid-Bus FIFO is that theneed for width expansion is removed. The Mid-Bus FIFO's are 36 bit widedevices, the V255/265 parts are 18 bit wide and therefore 36 bit busapplications required 2 of these devices to be connected in Width Expan-sion mode. Please refer to Table 1 for a diagram showing the widthexpansion arrangement.No Glue Logic

From the diagram we can also extract a second advantage offered bythe new mid-bus. When performing width expansion there are now 2devices both possessing discrete status flag outputs, in particular the emptyand full flags. Due to possible timing conflicts between the 2 devices, theactual empty or full flag status must be a 'composite' of the flag outputs fromboth devices, FIFO #1 and #2. Hence, added external logic gates arerequired to provide the composite signal. (The gate logic shown is either an'AND' gate or an 'OR' depending on whether IDT standard mode or FWFTof operation has been selected). These added gates obviously introduceadded cost, increased power and may take up circuit board real estate.When designing in the Mid-Bus there is only one empty or full flag signal toconsider, there is no need for composite signals and therefore externallogic.Low Power

This brings us to a third and often critical point when designing the FIFOinto a system, and that is power consumption. The Mid-Bus FIFO con-sumes less power even when compared to a single V255/265 device. TheMid-Bus part has an Icc1 maximum rating of 40mA (when operated at20MHz, 3.3v Vcc). The V255/265 parts are rated at 55mA. Therefore when2 of these are connected in width expansion a total Icc1 maximum of 110mAis obtained. So, within a given 36 bit bus application if two V255/265 devicesare used there is a increase in Icc1 maximum of 70mA.

DSC-2679/7

SuperSync II Mid-Bus FIFOThe Solution to High Density FIFORequirements within 36 bitBus Applications

APPLICATIONNOTE

AN-242

36D0-D35

36Q0-Q35

WEN

WCLK

PAF

FF/IR

IDT72V3660-IDT72V36110

REN

RCLK

PAE

EF/OR

Write Clock

Write Enable

Full Flag/ Input Ready

Programmable Almost Full Flag

Read Clock

Read Enable

Empty Flag/ Output Ready

Programmable Almost Empty Flag

Data Input Bus Data Output Bus

(4K x36 to 128K x36)

LDLoad OE Output Enable

26



www.idt.com

TABLE1: COMPARISON OF THE FIFO OPTIONS

IDT72V3660-110, Icc1 = 40mA 2 x IDT72V255-265LA, Icc1 = 110mA

64 % POWER SAVING

15% PRICE SAVING

30 % BOARD SPACE SAVING

+TOTAL AREA = 280mm 2

IDT72V3660-110 IDT72V255/65LA

TOTAL AREA =

IDT72V3660-110 2 x IDT72V255/65LA

392mm2

(4K x36 to 128K x36) (8K x36 to 16K x36)

68-Pin PLCC

128 - pin TQFP

68-Pin PLCC

64-pin TQFP

68-Pin PLCC

64-pin TQFP

36D0-D35

36Q0-Q35

WEN

WCLK

PAF

FF/IR

IDT72V3660-IDT72V36110

REN

RCLK

PAE

EF/OR

Write Clock

Write Enable

Full F lag/ Input Ready

Programmable Almost Full Flag

Read Clock

Read Enable

Empty Flag/ Output Ready

Programmable Almost Empty Flag

Data Input Bus Data Output Bus

(4K x36 to 128K x36)

LDLoad OE Output Enable

18D0-D17

18Q0-Q17

WEN

WCLK

PAF

FF/IR

REN

RCLK

PAE

EF/OR

Data OutputBus

LD

OE

18D0-D17

18Q0-Q17

WEN

WCLK

PAF

FF/IR

REN

RCLK

PAE

EF/OR

Full Flag/ Input Ready Empty Flag/ Output Ready

Data InputBus

LD OE

3636

GATE GATE

V255/265FIFO#1

V255/265FIFO#2

Cost & Board Space ReductionAs previously mentioned, two other advantages offered when using the

Mid-Bus FIFO as opposed to the V255/265 devices are the reduction in costand PCB real estate consumed by the FIFO. Refer to Table 1 for a pricecomparison.

With regards to the board space, the Mid-Bus FIFO's are available in a128 pin TQFP package with a footprint area of 280mm2, the V255/265 areavailable in a 64 pin TQFP packages which have an area of 196mm2,therefore 2 devices (required for width expansion) gives a total area of392mm2.Further Advantages & Benefits

Some further advantages offered by using the Mid-Bus include greaternoise immunity. The Mid-Bus device utilizes a 128 pin TQFP package whichincludes additional ground and Vcc lines. Extra pins also allow for the futuredevelopment of the SuperSync II family of FIFO's eventually leading todeeper parts with greater bus widths and faster operating speeds.

There are also some added benefits with the SuperSync II devicescompared to the IDT first generation SuperSync. These include ZeroLatency Retransmit, when a retransmit operation is performed the first wordto be retransmitted appears on the output immediately. Reduced first dataword latency, this is the time taken for the first word written to an empty FIFOto appear on the output. The SuperSync II family is setting the future of IDTFIFO's, along with all of the benefits mentioned above, the SuperSync IIoffers a road map that includes faster and deeper FIFO's, with many addedfeatures.



The IDT7201, IDT7202, IDT7203 and IDT7204 (512 x 9, 1,024 x 9, 2,048x 9 and 4,096 x 9) FIFOs have only four control lines: Read, Write, Reset andRetransmit. The focus of this tech note is the relation of the Read ( R ) andWrite ( W ) lines to the FIFO’s empty and full conditions.

These high-speed FIFOs can perform asynchronous and simultaneousread and write operations. R and W assert and deassert the Empty Flag( EF ) and Full Flag ( FF ).Therefore, special conditions exist when a fullFIFO continues to be written to and a read operation takes place. Also,special timings occur when an empty FIFO continues to be read to and awrite operation takes place. These operations are called the FIFO boundaryconditions.

Read and Write increment the read and write pointers on their respectiverising clock edges.The read and write pointers affect the Empty Flag and FullFlag counters.The Empty Flag timings are shown in Figure 1. When theFIFO has only one word in it, the falling edge of R causes EF to be asserted.After the clock cycle is completed ( R goes HIGH again), EF will remainasserted and the internal read counter is not affected by subsequent readcycles. EF is deasserted by the next rising edge of W , after which anotherread pulse can be applied to do a read operation. In asynchronous systems,read and write operations take place at any time; EF is set by one signal anddeasserted by another asynchronous signal.

When R is being clocked on an empty FIFO, the outputs will be in high-impedance. If a write operation is performed during asynchronous readcycles, a possible violation of the read pulse width minimum can occur, asshown in Figure 2. EF is deasserted, but there is an insufficient read pulseminimum width. To prevent the minimum read pulse width violation, initiatea read operation only after EF is HIGH, or guarantee a long enough readpulse width minimum time. A violation of the timing causes an internal glitchon the FIFO Read which can cause the read pointer to be “out of sync”. Thenthe data inside the FIFO may be scrambled or may be garbage. The EmptyFlag and Full Flag counters may also be upset by the internal glitch, whichupsets FIFO memory usage. The only way to recover from this violation isto do a master reset.

Figure 1. Empty Flag from Last Read to First Write

DSC-4307

March 1999FAST is a trademark of Fairchild Semiconductor Co.

A similar situation arises at the full FIFO boundary condition. When theFIFO is one word from being full, the falling edge of W causes the FF tobe asserted. After the write cycle is completed ( W goes HIGH again), FFwill remain asserted and the internal write counter is not affected bysubsequent write cycles. The FF flag is deasserted by the next rising edgeof R , as shown in Figure 3, after which another write pulse can be appliedto do a write operation.

When the FIFO is full and W is being clocked, data sent to the FIFO willbe ignored and the write pointer will not incre-ment. Here, as in the earliercase, if these write cycles are asynchronous during a read operation, apossible violation of the write pulse width minimum can occur, as shown inFigure 4. Here, FF is deasserted but a sufficient write pulse minimum widthis not met. To prevent the problem, initiate a write operation only after FFis HIGH, or guarantee a long enough write pulse width minimum time. Aviolation of the timing causes an internal glitch on the FIFO write line. Thiscan cause the write pointers to be “out of sync” where the data inside theFIFO may be scrambled or may be garbage. The Empty Flag and Full Flagcounters may also be upset by the internal glitch. Again, the only way torecover from this condition is to do a master reset.

In summary, these FIFOs are designed to transfer only valid data frominput to output. To ensure that valid data is written into and read from,empty and full FIFOs handshake through the flag mechanism. When thereis no output data available, the reading side must wait until the end of awrite. In a full FIFO, the writing side must wait for the reading side to createan “empty” location. Incomplete read and write cycles can not onlyinvalidate data, but can cause the pointers to be out of synchronization,requiring a master reset to renew data transfer.

tWEFtREF

This read pulse is ignored by the FIFO

R

W

EF

Operating FIFO's on Full and EmptyBoundary Conditions

TECHNICAL NOTE TN-08

28



www.idt.com

NOTES:1. Pulse within the FIFO used to clock the read pointer and the Empty and Full Flag counters.2. If t1 < tWPW (minimum write pulse width low), then the write pointer, Empty Flag and Full Flag counters may be out of sync. See Figure 16 of IDT7201/7202LA data sheet.

Figure 4. Violation of tWPW During Boundary Conditions

This read pulse is ignored by the FIFO

NOTES:1. Pulse within the FIFO used to clock the write pointer and the Empty and Full Flag counters.2. If t1 < tRPW (minimum read pulse width low), then the read pointer, Empty Flag and Full Flag counters may be out of sync. See Figure 15 of IDT7201/7202LA data sheet.

Figure 2. Violation of tRPW During Boundary Conditions

Figure 3. Full Flag from Last Write to First Read

t1

R (Internal)

EF (Internal)EF

R

Externalto FIFO

INTERNAL READ (1)

R

W

EF

R

tRFFtWFF

This write pulse is ignored by the FIFOW

FF

t1W

FF (Internal)FF

W

Externalto FIFO

(Internal)

This write pulse is ignored by the FIFO

INTERNAL WRITE (1)

R

W

FF

IDT TECHNICAL NOTE TN-08


March 1999

The IDT7200/7201/7202/7203/7204/7205/7206/7207/7208 are high-speed 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768x 9 and 65,536 x 9 FIFOs, respectively, that can be cascaded to form evendeeper FIFOs. This tech note explains how these FIFOs are cascaded.

A cascaded FIFO configuration of 512 x 9 FIFOs is shown in Figure 1.The FL pin (First Load) of the first FIFO to be loaded after a reset is tied toground. The other FIFOs have their FL pin tied to VCC. After a resetoperation, the first 512 writes occur in the first FIFO. During these writeoperations, the XO (Expansion Out) and XI (Expansion In) lines are high.On the 512th write, a pulse is created on the XO line following the Write (W ) line. The pulse informs the second FIFO that is going to receive the nextword. It also informs the first FIFO that its write pointer will no longerincrement due to an internal evaluation of the XO line. The XO line of thefirst FIFO is connected to the XI line of the second FIFO. The XO of thesecond FIFO is connected to the XI of the third, and so on. The XO of thelast FIFO is connected to the XI of the first FIFO. A typical XO operationof 2,048 writes after a reset is shown in Figure 2.

The same procedure holds true for read operations. During the 512thread operation after a reset, another pulse will be created on the XO linefollowing the Read ( R ) line. This pulse will inform the second FIFO that itwill be read from on the next cycle (provided it is n’t empty). Also the firstFIFO’s read pointer will not increment until it receives a second pulse on itsXI line.

Figure 3 shows the XO and XI relationship to read and write. The XOpulses are transferred to the XI of the next level of FIFO. The first pulsetransfers write pointer control and the second transfers read pointer control.There is an important advantage to this method expansion. A word writtento the FIFO after a master reset is immediately available at the FIFO output.A read cycle can be initiated as soon as the Empty Flag ( EF ) is unasserted.This is called zero fall-through time. Earlier shift register-based FIFOs havea fall-through time in the µsec range.

To take full advantage of this unique expansion feature, some designprecautions must be observed. Since a pulse on XI activates read or writeoperations of the FIFO, they must be relatively free from cross-talk noise.A long trace from the XO of the last FIFO to the XI of the first FIFO is apotential source of cross-talk noise. To prevent noise spikes from alteringthe XI input on this and other XO to XI interconnects, a small capacitorin the 22pF to 47pF range should be inserted between the XI inputs andground.

by Suneel Rajpal and Frank Schapfel

DSC-4410

Cascading FIFOs or FIFOModules

TECHNICAL NOTE TN-09

Another important point is how to handle flags in the expansion mode.To create the composite Full Flag, tie the four individual FIFO Full Flags (FF ) to an OR gate. The composite EF is created similarly. This additionallogic is shown in Figure 1.

To create intermediate flags using the individual Full and Empty Flagsis more tricky, but can be done. For example, an attempt to create acomposite Half-Full Flag ( HF ) is described here. Let us define Flag f1 aswhen any two FIFOs are full and at last one other FIFO is not empty.Boolean Equation for f1:

f1 = FF1.FF2(EF3 + EF4 ) +FF2.FF3(EF1 + EF4 ) +FF3.FF4(EF1 + EF2 )FF4.FF1(EF2 + EF3 )

FFi = Full Flag of FIFOi

EFi = Empty Flag of FIFOi

In one extreme case, f1 is asserted when there is 1,500-1 words in theFIFO array. The first two FIFOs are full, with 512 words in each, and thethird FIFO has 511 words. Another extreme case is when two FIFOs are fulland the third FIFO has only one word. Therefore, Flag f1 is only a range ofwords where the half-full condition exists, from 1,024+1 to 1,500-1words in the array. It may not be used as a half-full indicator, because theFIFO array may be almost 3/4 full before Flag f1 is asserted.

As shown in Figure 4, an empty FIFO array has a word written to it andthen read from it. Then, 1,500-1 words are written to the FIFO array. Thewrite pointer is on the last word of the third FIFO. Only at this time is Flagf1 asserted, while the FIFO array has 1,500-1 words in it. Intermediate flagslike f1, generated from Boolean Equations, can only provide a range ofvalues when f1 is to be asserted. A precise position for f1 cannot bedetermined. If Boolean Equations are used to generate intermediate flags,consider all the different locations of the read and write pointers which mayassert or deassert at a particular condition.

30

NOTE:Read, Write and Reset controls go to all four FIFOs.

Figure 1. Four Cascaded 512 x 9 FIFOs

Figure 2. The XOXOXOXOXO/XIXIXIXIXI Timing Pulse for 2,048 Writes and Zero Reads

NOTE:Read line is assumed to be HIGH in this example

XOFF EF

XIFL

DO-8 QO-8

XO

XO

XO

FF

FF

FF

EF

EF

EF

DO-8

DO-8

DO-8

QO-8

QO-8

QO-8

XI

XI

XI

FL

FL

FL

VCC

VCC

VCC

GND#1

#2

#3

#4

0-8DATA OUTDATA IN

0-8

COMPOSITE FF COMPOSITE EF

TN-09 drw 01

512th WRITE

TN-09 drw 02

2,048th WRITE1,536th WRITE1,024th WRITE

W

XO (FIFO 1)

XO (FIFO 2)

XO (FIFO 3)

XO (FIFO 4)


31

NOTES:1. Pulse 1 is created by the 512th write pulse; it is a delayed write pulse.2. Pulse 2 is created by the 512th read pulse.

3. Pulse 3 from FIFO 2 is created by the 1,024th write pulse.4. Pulse 4 is created by the 1,024th read pulse.5. XO (FIFO 3) and XO (FIFO 4) are not shown, but they follow the same pattern.

6. XO (FIFO 4) will be created by the 2,048th write pulse and later by the 2,048th read pulse, thereby transferring pointer control back to FIFO 1.

Figure 3. The XOXOXOXOXO and XI XI XI XI XI PulseTimings

Case 1: In the cascaded FIFO arrangement, the write pointer has just written to FIFO #3and the flag defined by the f1 equation would be asserted at the half-full point.

Case 2: The FIFO array is half-full at arrow at Note 1, but f1 will not be asserted until thelast write into FIFO #3 or until the FIFO array is almost 3/4 full or at arrow 2.

Figure 4. The Behavior of the f1 Flag for Different Cases

512th WRITE

TN-09 drw 03

1,024th WRITE

W

XO (FIFO 1)

XO (FIFO 2)

R

512th READ 1,024th READ

43

21


TN-09 drw 04

READ POINTER

WRITE POINTER

WRITE POINTER

READ POINTER

#1 #1

#2#2

#3 #3

1

2

#4 #4


INTRODUCTIONThe performance requirements of today’s systems are continually

reaching to new heights. In response to needs for higher performance, IDThas introduced a family of First-In-First-Out (FIFO) buffers which are ideallysuited for system speeds of 25MHz or greater. The synchronous interfaceof this family of Clocked FIFOs offers several advantages over the tradi-tional IDT720X Series of FIFOs:a) speed (data transfer rates of up to 67MHz;b) free running clock control simplifies system design.

The Clocked FIFO family includes x8-bit, x9-bit, and x18-bit parts in awide range of densities. To accommodate system requirements beyondthis product family, the FIFOs can be easily expanded in width and depth.The purpose of this Application Note is to discuss design considerationsand recommendations when designing with SyncFIFOs (Clocked FIFOs) inWidth Expansion.

SKEW TIMINGThe inherent advantage of FIFO buffers is the ability to buffer data

between two mismatched systems or subsystems. Inherent to an interfacebetween two asynchronous systems is the issue of synchronizing events onone side with respect to events on the other.

For the Clocked FIFOs, internal logic is used to synchronize the statusflags to either the Write Clock (WCLK) or the Read Clock (RCLK). A skew

by Rob De Voto

NOTES:1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.

Figure 1. Skew Timing

DSC-2649

April 1999

Width Expansion Of SyncFIFOs (Clocked FIFOS)

ApplicationNote

AN-83

time is specified which deter-mines if sufficient time has been allowed for theflag to be updated in the current clock cycle. If the skew timing is not met,an extra cycle is required to update the flag.

WIDTH EXPANSIONWhen using the Clocked FIFOs in Width Expansion, the control signals

of all parallel FIFOs should be connected together to maintain concurrentoperations on all devices. The recommended flag output circuitry is shownin the following section.

DESIGN CONSIDERATIONSInherent to all Clocked FIFOs is the concept of skew timing. In reality, the

skew timing of individual devices may vary by a small amount. For example,the tSKEW1 minimum spec for the 20 ns speed grade of the IDT72211 (512x 9-Bit) equals 8ns. For two devices in width expansion, the actual tSKEW1of FIFO#1 may equal 7.2ns and the actual tSKEW1 of FIFO#2 may equal7.4ns.

This small variation in the actual timing of the devices may cause theflags of the parallel devices to be de-asserted in different cycles. Forexample, if the tSKEW1 timing of the system happens to be 7.3ns on theedge which is de-asserting the EF, then the EF of the two FIFOs will be de-asserted on different clock cycles.

tCLKH

WEN

DO - D7

tCLKL

tCLK

WCLK

DATA IN VALID

NO OPERATION

FF

RCLK

REN

tENStENH

tDS tDH

tSKEW(1)

tWFFtWFF

33

Figure 2. Block Diagram Showing the Control Signals of a SyncFIFO (Clocked FIFO) in a Width Expansion Configuration

In this situation, if REN is asserted to begin read operations when theEF of FIFO#1 is de-asserted but the EF of FIFO#2 is not de-asserted, thendata on the outputs (Q) of the two devices will not be aligned. In other words,data from FIFO#2 will have a one location lag behind data from FIFO#1.

SOLUTION AND RECOMMENDATIONThere are two solutions to the situation described.1. Composite Flag. Monitor the EF from all FIFOs in Width Expansion.

A read operation (REN = low) can begin only when the EF from all deviceshave been de-asserted. This is the recommended solution.

2. Use the Almost Empty Flag (AE) to begin read operations. De-assertion of AE may exhibit the same skew affect as the EF (see nextsection), however, using AE does not jeopardize data integrity.

OTHER FLAGSThis skew affect also applies to the Full Flags (FF) of all the Clocked

FIFOs (x8, x9 and x18 SyncFIFOs), the Almost-Empty Flag (AE) andAlmost-Full Flag (AF) for the IDT72XX0 family (x8 SyncFIFOs), and theProgrammable Almost-Empty Flag (PAE) and Programmable Almost-FullFlag (PAF) for the IDT72XX1 family (x9 SyncFIFOs). The solution forthese flags is identical to those outlined above. In summary, use compositeflag, i.e. monitor the flags from all devices.

x x2

RESET (RS) RESET (RS)

READ CLOCK (RCLK)

READ ENABLE (REN)

OUTPUT ENABLE (OE)

x DATA OUT (Q)

DATA IN (D)

WRITE CLOCK (WCLK)

WRITE ENABLE (WEN)

IDT Clocked FIFO

IDT Clocked FIFO

x2 xx

EXCEPTIONThe exception to the skew affect is the Programmable Almost-Empty

Flag (PAE), the Programmable Almost-Full Flag (PAF), and the Half-FullFlag (HF) on the IDT722X5 family (x18 SyncFIFOs). These flags are notsynchronized with respect to any one clock. In other words, they areasserted and de-asserted with respect to different clocks. In this case, thereis no skew timing (tSKEW1). The monitoring of only one device in WidthExpansion is adequate for these flags.


34

Figure 3. Skew Timing for FIFO#1

Figure 4. Skew Timing for FIFO#2


WEN

Data Input (D)

WCLK

tDS

D0 (first valid w rite)

EF

RCLK

REN

tENS

tSKEW 1

tOE

D1 D2 D3

tRE F

D1D0

tA tA

tOLZ

Data Output (Q)

OE

WEN

Data Input (D)

WCLK

tDS

D0 (f irst valid w rite)

EF

RCLK

REN

tEN S

tSKEW 1

tOE

D1 D2 D3

tRE F

D0

tA

tOLZ

Data Output (Q)

OE

35

Figure 5. Recommended Block Diagram of Width Expansion using Composite Flags

x x2

RESET (RS) RESET (RS)

READ CLOCK (RCLK)

READ ENABLE (REN)

OUTPUT ENABLE (OE)

x DATA OUT (Q)

DATA IN (D)

WRITE CLOCK (WCLK)

WRITE ENABLE (WEN)

IDT Clocked FIFO #1

IDT Clocked FIFO #2

x2 xx

EMPTY FLAG (EF) #1

EMPTY FLAG (EF) #2

FULL FLAG (FF) #1

FULL FLAG (FF) #2

Figure 6. Waiting Two Clock Cycles after Flag Assertion


WEN

Data Input (D)

WCLK

tDS

D0 (first valid write)

EF

RCLK

REN

tENS

tSKEW 1

tOE

D1 D2 D3

tREF

D0

tA

tOLZ

Data Output (Q)

OE

two cycles

tENS

36



www.idt.com

Figure 7. Programmable Flag Timing for the IDT722X5 Family (x18 SyncFIFOs)


WEN

WCLK

n words in FIFO

RCLK

REN

tPAE

tCLKH tCLKL

tENHtEN S

n + 1 words in FIFO

tPAE

tEN S

PAE


INTRODUCTIONThere are many applications in today’s high speed designs for a data

buffering device that will delay a parallel data stream for a known andconstant period of time.

In networking applications it is very common to pull addressing informa-tion (whether source or destination) from a header block and determine ifthat data packet should be kept, discarded, or passed on to the next node.In today’s emerging standard of ATM, VCIs (Virtual Channel Identifiers) andVPIs (Virtual Path Identifiers) must be assigned to set up the proper physicalconnection of a data path. To perform these operations, the incoming datastream must be delayed for a period of time. The magnitude of the delayis design-dependent and variable.

Digital filtering applications need the same type of delay function forprocessing pixel streams. The standard line contains 910 pixels. Bydelaying the data stream in increments of 910 and feeding these tap-offpoints to a digital filter, an effective vertical filter can be constructed.

These are only two brief examples of the many potential uses for aparallel data delay buffer. This application note will look at how IDT ParallelClocked FIFOs can be used to implement this function at high speeds.

GENERAL INFORMATIONWith the large selection of clocked FIFOs that IDT offers, many different

data delay applications can be realized. The IDT722x0 family provides 8-

By Gary Prelesnik and Kim Goldblatt

Figure 1. The IDT722x1 SyncFIFO used as a 9-bit delay element

DSC-3080

March 1994

Using IDT SyncFIFOs asParallel Data Delay Lines

Application Note

AN-122

bit wide buffering for delays of 59, 251, 507, 1019, 2043, and 4091 clockcycles. Even more flexible is the IDT722x1 family, which provides 9-bit widebuffering for delays from three to 4096 clock cycles. The new dual FIFOfamily, IDT728x1, can easily be configured as an 18-bit buffer for delaysfrom 3 to 4096 clock cycles. The IDT722x5LB is an 18-bit wide FIFO familythat, by virtue of its easy multiple device depth expansion capability, offerslonger delays than any lone SyncFIFO can provide. Delays achievable foreach device type are summarized in Table 1.

In all cases, the Read and Write Clock pins ( RCLK , WCLK ) are bothconnected to the clock source for incoming data. The ProgrammableAlmost Full Flag ( PAF ) or Almost Full Flag ( AF ) is tied to the Read Enable( REN ) pin as shown in Figure 1. For devices that have programmableflags, the value written to the Full Offset Register will determine the numberof clock cycles by which the data will be delayed, input to output.

During normal operation, the Write Enable pin(s) must be kept activeLOW continuously to achieve the desired constant data delay. It is importantto note that the Write Enable pin(s) cannot be tied directly to ground, asthere is a reset requirement for all the REN and WEN control lines to beactive HIGH for a minimum of one clock cycle after the rising edge of reset.

USING THE IDT722X0 FAMILYThe IDT722x0 family has 8-bit input and output ports. These devices

offer depths of m = 64, 256, 512, 1024, 2048, and 4096 words. These FIFOs

WEN1

SYSTEM CLOCK

DATA OUTDATAIN

WRITE ENABLE 1

WRITE ENABLE 2/LOAD

RESET

OUTPUT ENABLE

FULL FLAG

EMPTY FLAG

PROGRAMMABLE ALMOST EMPTY

WCLK RCLK

OE

WEN2/LD

D0 - D8 Q0 - Q8

IDT72421/72201/72211/72221/72231/72241

REN1

PAF

RS

REN2

PAE

EF

FF

3080 drw 01

38

CHARACTERISTICS OF IDT SyncFIFOS USED AS DELAY ELEMENTS

FIFO Size (MHz) (Clock CYC.) (Clock CYC.) (Clock CYC.)

Maximum Programmable Clock Rate1 Fixed Delay Delay Range Default Delay2

72420 64 x 8 83 59 — — 72200 256 x 8 83 251 — —

72210 512 X 8 83 507 — — 72220 1024 x 8 83 1019 — — 72230 2048 x 8 83 2043 — — 72240 4096 x 8 83 4091 — — 72421 64 x 9 83 — 3 to 63 59 72201 256 x 9 83 — 3 to 255 251 72211 512 x 9 83 — 3 to 511 507 72221 1024 x 9 83 — 3 to 1023 1019 72231 2048 x 9 83 — 3 to 2047 2043 72241 4096 x 9 83 — 3 to 4095 3970 72205 256 x 18 31 — 2 to 254 251 72215 512 x 18 31 — 2 to 510 507 72225 1024 x 18 31 — 2 to 1022 1019 72235 2048 x 18 31 — 2 to 2046 2043 72245 4096 x 18 31 — 2 to 4094 4091 72801 256 x 9 x 2 66.7 — 3 to 255 251 72811 512 x 9 x 2 66.7 — 3 to 511 507 72821 1024 x 9 x 2 66.7 3 — 3 to 1023 1019 72831 2048 x 9 x 2 66.7 3 — 3 to 2047 2043 72841 4096 x 9 x 2 66.7 3 — 3 to 4095 4091NOTES1. Applies only to the data delay application.2. Delay achieved with programmable flag default settings following reset.

3080 tbl 01

have AE and AF flags fixed at the Empty+7 and Full-7 locations, respec-tively. When used as a delay buffer, these FIFOs provide delays of m = 5clock cycles. For a greater choice of delays, the IDT722x1 family isrecommended.

USING THE IDT722X1 FAMILYThe IDT722x1 family has 9-bit input and output ports. These devices offer

depths of m = 64, 256, 512, 1024, 2048, and 4096 words. These FIFOs haveprogrammable AE and AF flags that give the designer the ability to programdelay values in increments of the clock cycle time. A PAF offset value of 3produces the longest delay.

The PAF will go LOW when the FIFO reaches the AF condition. This isdefined by the value in the Full Offset Register. Since the value in the registerdefines the number of locations from the flag assertion to the full condition,and the delay value is actually the number of locations from empty to flagassertion, a small calculation must be made to achieve the be used tocalculate the correct offset value. This is accomplished by taking themaximum FIFO size, subtracting the number of clock delays desired, thenadding two to this value. The two is added to account for the one cycle delayfrom last write to flag assertion, plus one cycle for REN set up time. Thefollowing equation can be used to calculate the Full Offset Register value forthe 722x1 and 728x1 families:

F = m - D + 2Where: F = Full Offset Register value

m = Maximum FIFO depthD = Desired delay value (in increments of clock periods)The FIFO can be configured for loading programmable offsets by

holding the Write Enable 2/Load (WEN2/LD) LOW at reset, then bringingit HIGH for normal operation. Following this operation, the LD function isactive. When the WEN1 AND WEN2/LD pins are held LOW on the risingedge of the write clock, the PAE and PAF offsets will be loaded on fourconsecutive Write Clock edges. Please refer to the relevant data sheets formore information on programming offset registers.

Following reset, the offset registers are set to default values; this maysimplify some designs. Table 1 shows the delays achieved for the defaultsettings of various IDT FIFOs. Perhaps the greatest advantage of usingthe 722x5LB as a delay element is that composite depths greater than4096 words can be achieved simply by daisy-chaining devices. Expand-ing depth allows longer delays than can be achieved with a singleSyncFIFO. Depth expansion is explained further in the 722x5 data sheet.By tying the corresponding control signals for the A and B FIFO together,a single 18-bit wide FIFO can be constructed with the same timing andfunctions as the 9-bit wide family. This device type, along with the IDT722x1,can operate as a delay element at higher frequencies than the IDT722x5family, which will be discussed in the timing analysis section.

USING THE IDT722X5 FAMILY:The IDT722x5 family of 18-bit wide FIFOs can be used in delay


39

Figure 2: The IDT784x1 Dual SyncFIFO used as an 18-bit delay element

applications at clock speeds of 31MHz or less. This family also hasprogrammable AE and AF flags that give the designer the ability toprogram delay values in increments of the clock cycle time. Compared to the722x0 and 722x1 families, the 722x5 PAF flag asserts one WCLK cycleearlier; therefore, delays achieved for a given PAF offset value will be oneclock cycle shorter. A PAF offset value of 2 produces the longest delay. Theminimum possible delay for the 722x5, when the Full Offset Register is setto all 1’s, is two clock cycles. Default values are also available as listed inTable 1.

USING THE IDT728X1 FAMILY:The latest addition to the IDT clocked FIFO family is the Dual SyncFIFO,

IDT728x1. This family is functionally equivalent to two IDT722x1 FIFOs ina space-saving TQFP package. The Full Offset Register value needed toproduce a given delay can be calculated using the same equation as for the

722x1 family. (See the preceding section.) Since all data and controllines for each nine bit slice are brought outside the part, these devices canbe configured for a variety of applications. Figure 2 shows the desiredconnections for an 18-bit wide delay buffer.

The following equation can be used to calculate the Full Offset Registervalue for a single 722x5:

F = m - D + 1Where: F = Full Offset Register valuem = Maximum FIFO depthD = Desired delay value (in increments of clock periods)Perhaps the greatest advantage of using the 722x5LB as a delay

element is that composite depths greater than 4096 words can be achievedsimply by daisy-chaining devices. Expanding depth allows longer delaysthan can be achieved with a single SyncFIFO. In order to ensure that oncethe PAF flag goes LOW, it will stay LOW, regardless of read and writepointer movement among the FIFOs, a flip-flop needs to be insertedbetween PAF and REN. Refer to Figure 3. Depth expansion is explainedfurther in the 722x5 data sheet.

The following equation can be used to calculate the Full Offset Registervalue for the 722x5 in depth expansion:

F = m - D + 2Where: F = Full Offset Register valuem = Maximum FIFO depthD = Desired delay value (in increments of clock periods)

TIMING ANALYSISWhen using the PAF or AF flag as the Read Enable control, the delay

from the write clock rising edge to the deassertion of the flag plus the readenable set up time must be less than one clock cycle. This will ensure thatone word of data will be read out for every clock cycle. In this way the datadelay will be accurate.

As an example, let’s look at the IDT72241L15 9-bit FIFO. The WriteClock to Programmable Almost Full (tPAF) parameter is specified at amaximum of 10ns, and the Read Enable Setup time (tENS) is specified ata minimum of 4ns. A 15 ns period will guarantee a valid read on every risingRead Clock edge with a one nanosecond margin. This scenario allows amaximum shift frequency of 66.6 MHz.

The IDT728x1 Dual SyncFIFOs have timing parameters similar to theIDT722x1 9-bit FIFOs. For all speed grades, The sum of tPAF and tENSdetermine the minimum clock cycle time for the delay element application.

As a second example, let’s consider the IDT72245LB15 18- bit wideFIFO. The t PAF parameter is specified at a maximum of 28 ns, and thetENS is specified at a minimum of 4ns. A 15ns speed grade device, runningat maximum frequency, would not be suitable since the 15ns cycle time isnot large enough to accomodate the PAF response time plus the REN setup time. However, at a 32 ns clock period or slower, this same device canmeet the timing constraints and offer predictable data delays.

BOUNDARY CONDITIONSFor those FIFOs possessing a programmable PAF, the shortest delay

can be achieved by programming the offset register with the largest

RESET

DATA IN

WRITE ENABLE

WRITE ENABLE/LOAD

CLOCK

OUTPUT ENABLE

READ ENABLE

DATA OUT

PROGRAMMABLE ALMOST FULL F LAG

18 9

18

9

9

9

FIFO B256 X 9512 X 9

1024 X 92048 X 94096 X 9

FIFO A256 X 9512 X 9

1024 X 92048 X 94096 X 9

RENB2

RENA1

RENB1

PFA

OEB

QA0 - Q A8 QA0 - Q A8

DB0 -DB8

RSBRSA

WCLKA

DA0 - DA8

RCLKA

WENA1

WENA2/LDA

OEA

2WENA2/LDB

WENB1

WCLKB

RCLKB

3080 drw 02

RENA2


40

Figure 3: A depth expansion of the IDT722x5 used as a delay element

possible value; i.e. all ones. Under this condition, the 722x1 family willproduce a three cycle delay, and the 722x5 will produce a two cycle delay.These delays can be accounted for as follows:

1) A one cycle delay from write to PAF flag (for 722x1 and 728x1families only), plus

2) A one cycle delay for REN set up time (for the 722x1, 728x1 and722x5 families), plus

3) A one cycle delay for data access time (for the 722x1, 728x1 and722x5 families).

Figure 4 details the minimum delay timing for the 722x1 and 728x1families.

Though it is possible to program the Full Offset Register with all zeros,the minimum permissible value to realize a delay line application is 3 for the722x1 and 7228x1 families, and 2 for the 722x5 family. This will account forthe three latency factors just explained, plus the time required to keep theFull Flag (FF) inactive. If 0, 1, or 2 is written in the offset register, FF will beactivated before the PAF flag is recognized, as shown in Figure 5. Anyattempted writes will be prohibited while FF is active, thus corrupting theincoming data stream.

SUMMARYIDT’s high-performance SyncFIFOs, comprising the 722x0, 722x1,

728x1 and 722x5 families, are most commonly used as elastic buffersmatching two busses operating at different data rates. The foregoingdiscussion show they may also be used to delay parallel data, an increas-ingly important function for many of today’s high speed designs. Up untilnow, devices designed for the exclusive purpose of delaying parallel datahave been unable to operate at frequencies much higher than 20MHz.

However, IDT SyncFIFOs have the capability to operate at clockfrequencies as high as 83MHz. Furthermore, these clocked FIFOs can beprogrammed to produce a wide range of parallel data delays. For a singledevice, anywhere from 2 to 4096 clock cycles of delay are realizable. Sincethe 722x5 family is readily depth-expanded, even larger delays can beattained. All IDT SyncFIFOs can be width-expanded, thus the data pathwidth that can be delayed has no upper limit. In conclusion, IDT SyncFIFOsprovide a higher level of performance for data line delay applications thanhas previously been available.

WXI

RSOE

LD

WCLK RCLKRXI

WENREN

RS

IDT

FLWXO RXO

PAF

722x5LB

QnDn

VCC

DATAOUTDATAIN

WRITE ENABLESYSTEM CLOCK

3080 drw 03

WXI

RS

OE

LD

WCLK RCLKRXI

WENREN

RS

IDT

FLWXO RXO

PAF

722x5LB

QnDn

WXI

RSOE

LD

WCLK RCLKRXI

WENREN

RS

IDT

FLWXO RXO

PAF722x5LB

QnDn

VCC

RESETLOAD RESET

OUTPUT ENABLE

READENABLECLR CLK

D Q

FIRSTLOAD

FIRSTLOAD

FIRSTLOAD




www.idt.com

Figure 4: The three cycle minimum delay as it applies to the 722x1 and 728x1 families.(WEN2 WEN2 WEN2 WEN2 WEN2 = HIGH, REN2 REN2 REN2 REN2 REN2 = LOW, OE OE OE OE OE = LOW)

(WEN2WEN2WEN2WEN2WEN2 = HIGH, REN2REN2REN2REN2REN2 = LOW, OEOEOEOEOE = LOW, m = maximum FIFO depth in number of words )Figure 5: Maximum data delay timing as it applies to the 722x1 and 728x1 families.

3080 drw 04

W0 W1

WCLK = RCLK

WEN1

D0 - D8

tENH

tENS

PAF = REN1

1 2CYCLE 3CYCLE CYCLE

W0 W1 W2 W3 W4

Q0 - Q8

tENS

tPAF

tAtDS

tA

3080 drw 05

W0 W1

WCLK = RCLK

WEN1

D0 - D8

tENH

PAF = REN1

m - 3 CYCLE m - 2 CYCLE

Wm -3 Wm - 2 Wm - 1 Wm Wm + 1

Q 0 - Q8

tENS

tPAF

tA

tW FF

LOW

FF

Assertion of FF if 0, 1, or 2programmed into Full Offset Register

CYCLE m - 1 CYCLE m m +1 CYCLE



INTRODUCTIONThis application note describes a state machine approach to serially

programming the partial flags on SuperSync FIFOs. Up until recently,programmable flags on most FIFOs were programmed using parallel datainputs. In systems where the FIFO data inputs share a common bus withother devices, this method is not always convenient since it can tie up thebus at the time of system reset. In such situations, serial programmingallows partial flags to be configured without having to use the bus. Recog-nizing this advantage, IDT is now offering serial programming on high speed,exceptionally deep First-In-First-Out memories called SuperSyncs. Thereare four SuperSyncs now available: the IDT72261 (16,384 words deep x9 bits wide), the IDT72271 (32,768 words deep x 9 bits wide), the IDT72255(8,192 words deep x 18 bits wide), and the IDT72265 (16,384 words deepx 18 bits wide).

The following discussion will show how a state machine can be de-signed that can serially load as many as 30 flag offset bits into a SuperSyncFIFO at a maximum shift frequency of 100MHz. The state machine isdesigned using the ABEL language and will fit into a single 20V10 PAL.

by Kim Goldblatt

Figure 1. The IDT72261/72271 SuperSync FIFO Architecture

THE SUPERSYNC SERIAL LOADFEATURE

Figure 1 shows the architecture of the IDT72261/72271 SuperSyncs.Figure 2 gives the architecture of the IDT72255/72265 SuperSyncs. Theonly differences between these two devices are the data path width (9 bitsfor the former, 18 bits for the latter) and the internal flag offset registerorganization. Figure 3 illustrates the IDT72261/72271’s four registers:PAE LSB (8 bits), PAE MSB (6 bits for the IDT72261, 7 bits for theIDT72271), PAF LSB (8 bits), and PAF MSB (6 bits for the IDT72261, 7bits for the IDT72271). Therefore, for the IDT72261, these registers amountto a total of 30 bits that can be serially loaded; for the IDT72271, the total is28 bits. Figure 4 illustrates the IDT72255/72265's two registers: PAE andPAF (each register is 13 bits for the IDT72255, 14 bits for the IDT72265).Therefore, for the IDT72255, these registers amount to a total of 26 bitsthat can be serially loaded; for the IDT72265, the total is 28 bits. (Consultthe respective SuperSync data sheets for further information).

Note that SuperSyncs have two programmable flags: the Program-mable Almost-Empty (PAE) flag and the Programmable Almost-Full (PAF)

Serial Programming of SuperSync FIFOFlag Offsets:A State Machine Approach

ApplicationNote

AN-130

INPUT REGISTER

OUTPUT REGISTER

RAM ARRAY16,384 x 932,678 x 9

FLAGLOGIC

FF/IR PAF EF/OR PAE HF

READ POINTER

READCONTROL

LOGIC

WRITE CONTROLLOGIC

RESET LOGIC

WEN WCLK D0-D8 LD

MRS

REN

RCLK

OEQ0-Q8

TIMINGFS

OFFSET REGISTER

PRS

FWFT/SI

SEN

RT

3144 d rw 01

WRITE POINTER

43

Figure 2. The IDT72255/72265 SuperSyncFIFO Architecture

flag. The switching threshold for each of these flags can be set for anydegree of fullness. Therefore, the deeper the FIFO, the greater the num-ber of offset bits necessary to specify the programmable flag threshold.

Selection of the flag programming mode, serial or parallel, takes placeduring Master Reset, according to the level of the Load (LD) line during thedeassertion of the Master Reset (MRS) line. A LOW on LD selects paral-lel loading. A HIGH on LD selects serial loading. The same LD line alsoselects one of two default flag offsets: 127 words from the empty boundaryfor PAE, from the full boundary for PAF; or 1,023 words from the emptyboundary for PAE, from the full boundary for PAF. After Master Reset,the programmable flags operate at the default values until programming (ifnecessary) takes place. Refer to Figure 5 for details on the Master Resettiming.

The SuperSync FIFO is capable of operating in two different modes oftiming: IDT Standard and First Word Fall Through. These modes are se-lected only during Master Reset, according to the level of the First WordFall Through/Serial In (FWFT/SI) line at the deassertion of MRS. A LOWon FWFT/SI selects IDT Standard Timing. A HIGH on FWFT/SI selectsFirst Word Fall Through Timing. Serial programming can be performed ineither mode. (Consult the data sheets for more information.)

Four SuperSync pins are used to carry out serial programming: SerialEnable (SEN), LD, FWFT/SI, and Write Clock (WCLK). Following MasterReset recovery, as long as SEN and LD are held LOW, flag offsets can beclocked into FWFT/SI, one bit for every rising edge of WCLK. SuperSyncserial load timing is shown in Figure 6.

A SINGLE PAL STATE MACHINESOLUTION

The question arises: How should the designer implement the serialload function in a real-world application.

To take full advantage of the serial programming feature’s benefits, aserial boot circuit should be interfaced to the SuperSync FIFO so as to becompletely independent of a system’s bus and processor, which are thenfree to perform other functions. Of course, the principal goal is to providea serial bit-stream. However, it would be convenient if the circuit couldperform other initialization tasks such as selecting serial programmingand choosing the timing mode (IDT Standard or First Word Fall Through).

What kind of external logic should be used? The implementationshould occupy as little board space as possible. Incorporating the re-quired serial loading functions into a single chip is desirable. Low devicecost and an ability to efficiently realize small state machines make pro-grammable logic an ideal choice. Of course, in order for such devices tooperate as synchronous machines, registered outputs are necessary. Themost demanding conditions of a SuperSync serial load application wouldrequire a programmable device to serially shift out the maximum pos-sible number of offset bits (30 bits for the IDT72271) at the highest allow-able frequency (100 MHz). The complete design example that followswill show how a single 20V10 PAL can be used to accomplish not onlythis task, but also generate signals to select serial loading and the timingmode during Master Reset.

INPUT REGISTER

OUTPUT REGISTER

RAM ARRAY8,192 x 18

16,384 x 18

FLAGLOGIC

FF/IR PAF EF/OR PAE HF

READ POINTER

READCONTROL

LOGIC

WRITE CONTROLLOGIC

RESET LOGIC

WEN WCLK D0-D17 LD

MRS

REN

RCLK

OEQ0-Q17

TIMINGFS

OFFSET REGISTER

PRS

FWFT/SI

SEN

RT

3144 d rw 02

WRITE POINTER


44

Figure 3. The IDT72261/72271 Offset Register Architecture

Figure 4. The IDT72255/72265 Offset Register Architecture

TIMING CONSIDERATIONSThe serial load design will be simpler if it can operate at the system

clock frequency without having to divide down the rate. Fortunately, 20V8PALs are now available that can run at 100MHz.

When selecting the appropriate PAL speed grade, another criterionneeds to be met: the maximum clock-to-output delay (tCO) of the PAL plusthe minimum data setup time (tDS) of the SuperSync FIFO must be lessthan the minimum cycle time of the clock:

tCO (max. for PAL) + tDS (min. for FIFO) < TWCLK (min.)

Since the minimum set up time for all SuperSync data and controlinputs is 3.5 ns (10 ns speed grade), the time remaining in a 10 ns clockperiod for the PAL clock-to-output delay is 6.5 ns. An example of a PALthat can meet these timing requirements is the Lattice GAL22V10C (7 nsspeed grade). This device has a clock-to-output time of 4.5 ns. Thisdevice can easily run at 100MHz clock frequency.

EMPTY OFFSET (LSB) REG.

DEFAULT VALUE07FH if LD is LOW at Master Reset3FFH if LD is HIGH at Master Reset

8 7 0

EMPTY OFFSET (MSB) REG.

00H

8 6 0

3144 drw 03b

FULL OFFSET (MSB) REG.

00H

8 6 0

72271 32,768 x 9-BIT

FULL OFFSET (LSB) REG.

8 7 0


EMPTY OFFSET (LSB) REG.

8 7 0


EMPTY OFFSET (MSB) REG.

00H

8 5 0

3144 drw 03a

FULL OFFSET (MSB) REG.

00H

8 5 0

72261 16,384 x 9-BIT

FULL OFFSET (LSB) REG.

8 7 0


EMPTY OFFSET REGISTER

17 0

07FH if LD is LOW at Master Reset,3FFH if LD is HIGH at Master Reset

DEFAULT VALUE

13

FULL OFFSET REGISTER

17 0

DEFAULT VALUE 07FH if LD is LOW at Master Reset,3FFH if LD is HIGH at Master Reset

13

3144 drw 04b

72265 16,384 x 18-BIT

EMPTY OFFSET REGISTER

17 0

07FH if LD is LOW at Master Reset,3FFH if LD is HIGH at Master Reset

DEFAULT VALUE

12

FULL OFFSET REGISTER

17 0

DEFAULT VALUE 07FH if LD is LOW at Master Reset,3FFH if LD is HIGH at Master Reset

12

3144 drw 04a

72255 8,192 x 18-BIT


45

Figure 5. SuperSync Master Reset Timing

DEFINING THE PAL�S FUNCTIONConsidering our present design goals and what we already know about

the SuperSync serial port, it is now possible to define the PAL signals(Figure 7) and how they connect to the FIFO.

In most applications, the flag offsets will be loaded once, shortly afterMaster Reset, in one, continuous stream of bits. Since the act of loadingoffsets logically follows the selection of programming method (serial or par-allel) and timing mode (IDT Standard or FWFT), it makes sense to incorpo-rate these Master Reset configuration activities together with a state ma-chine for the serially generating offsets–all in the same PAL.

First, consider what kind of signals need to be assigned to the PALpins. Since PALs are available that can operate at frequencies of 100MHz, the SuperSync WCLK line, even when running at maximum fre-quency, can be connected directly to the PAL clock input to synchronize

serial loading. The name for this PAL signal will be WCLK_IN. A LOW onMRS will be used to initialize the PAL to a known state. Another PALinput, can be set aside for this purpose and called MRS_IN.

One PAL output can be used to select the timing mode (IDT Standardor FWFT) and also to send out a serial train of offset bits, since both thesefunctions are multiplexed together on the same SuperSync input pin, FWFT/SI. This PAL output, called SER_OUT, will be connected directly to FWFT/SI. During Master Reset, the PAL can be programmed to present a HIGHon SER_OUT to configure the SuperSync for First Word Fall Throughmode, a LOW for IDT Standard Mode. After Master Reset, offset bits,likewise programmed into the PAL, will be clocked out on SER_OUT insequence, one bit for every rising edge of WCLK.

In many designs, offset registers are programmed once but neverread. In such cases, the SuperSync’s LD line is set HIGH during MasterReset to select the serial programming method and set LOW during serial

tRS

MRS

tRSR

REN

tRSS

FWFT/SI

tRSRtFWFT

tRSR

WEN

tRSS

LD

tRSRtRSS

tRSS

RT

tRSS

SEN

EF/OR

FF/IR

PAE

PAF,HF

Qn

tRSF

tRSF

tRSF

tRSF

tRSF

3144 drw 05

OE = HIGH

OE = LOW

If FWFT = HIGH, OR = HIGH

If FWFT = LOW, EF = LOW

If FWFT = LOW, FF = HIGH

If FWFT = HIGH, IR = LOW


46

Figure 7. Connections Between the PAL and the FIFO

NOTE:1. X = 4 for the IDT72255.

X = 5 for the IDT72265 and IDT72261.X = 6 for the IDT72271.

Figure 6. SuperSync Serial Load Timing (IDT Standard and FWFT modes)

loading to access the offset registers. It is not used for any other purpose.The PAL output called LD_OUT will be used to drive LD. The FIFO’sSEN also needs to be HIGH during Master Reset and LOW during serialloading; however, since these two lines have different hold time require-ments, a separate PAL output, called SEN_OUT, will be designated todrive SEN.

In the event an application requires it, the offset values can be ac-cessed once they have been programmed in by setting REN and LDLOW; then the contents of the offset registers will be displayed on thedata outputs, one register for every rising edge of RCLK, starting with thePAE LSB register and ending with the PAF MSB. In this case, LD andSEN must be driven separately–by dedicated PAL outputs. This is anadditional function that can be incorporated into the PAL if necessary.

Figure 8 shows that six registered outputs have been set aside for useas state variables. They are called U, V, W, X, Y, and Z. These lines,taken together, with U as the most significant bit and Z as the least signifi-cant bit, represent a binary code for identifying states. For example, statesS0, S1, and S2 correspond to 000000, 000001, and 000010 respectively.Using six variables, it is possible to design a state machine that has 26 =64 different states. The design illustrated in the next section uses only 33states, but still requires all six variables.

Counting all the PAL output functions assigned yields a total of nine.A 22V10 PAL, which has 10 registered outputs, would be a suitable devicefor this application.

WCLK

SEN

3144 drw06

tEN HtEN S

tLDH

(1)

(1)

tLD HtLD S

tDS

EMPTY OFFSET (LSB)

tENH

LD

SI

EMPTY OFFSET (MSB) FULL OFFSET (LSB) FULL OFFSET (MSB)

BIT 0 BIT 7 BIT 0 BIT X(1) BIT 0 BIT 7 BIT 0 BIT X(1)

tEN H

tLD H

3144 drw 06

LatticeGAL22V10

IDT72271

SupersyncFIFO

System Clock

System Reset

WCLK

LD

SEN

FWFT/SI

MRS

LD_OUT

SEN_OUT

SER_OUT

WCLK_IN

MRS_IN

CLK

Q

Q

Q

Q

Q

Q

Q

Q I

Q

V

W

X

U

Y

Z

StateVariables

3144 d rw 07


47

Figure 8. State Diagram for Serially Loading the IDT72271

NOTES:1. FORCE LD_OUT/SEN_OUT/SER_OUT specifies the output levels forced in the next

state. X = Don't care.2. At Master Reset: to select First Word Fall Through timing, set FWFT to 1, to

select IDT Standard timing, set FWFT to 0.3. For S0 through S32, if, at any time, MRS = 0, the machine will proceed to

S1 and force 1/1/FWFT. For the sake of clarity, these branches are notshown in the diagram.

4. The ABEL PAL program file provided in the appendix is based on this statediagram.

DESIGNING THE STATE MACHINEConfiguring the FIFO at Master Reset and serial loading of the pro-

grammable flag offsets are both accomplished in the state diagram shownin Figure 8. A working PAL program for this state machine, written in theABEL language, is provided at the end of this application note.

The first states, S0, S1, and S2 are required for FIFO configurationduring Master Reset. Following PAL power up, if MRS_IN is HIGH, themachine will begin operation in S0 and wait for the falling edge of a resetpulse. If MRS_IN is LOW, the machine will begin operation in S1 and waitfor a rising edge on MRS_IN. (Refer to the following section, entitled “PowerUp Considerations” for more information on PAL initialization.)

The combined function of S0 and S1 identifies the profile of a negative-going pulse on MRS_IN. These states set the PAL outputs, LD_OUT,SEN_OUT, and SER_OUT, at logic levels appropriate for configuring theSuperSync FIFO during Master Reset. LD_OUT (LD on the FIFO) is forcedHIGH to choose the serial programming method. Forcing SEN_OUT (SENon the FIFO) HIGH inhibits serial loading. During Master Reset, SER_OUT(FWFT/SI on the FIFO) selects the FIFO timing mode (HIGH for First WordFall Through mode, LOW for IDT Standard mode). The PAL program shouldbe adjusted so that SER_OUT is at the appropriate level during MasterReset.

For a Lattice GAL20V10 PAL (7 ns speed grade) operating at 100 MHz,the reset pulse (going to both the PAL and the FIFO) must stay LOW for atleast two cycles of WCLK. In this case, the state machine will stay in S1 fortwo cycles. This measure ensures meeting the reset setup time (tRSS) forLD, SEN, and FWFT/SI. (See Figure 9.) If the serial programming op-eration is carried out at a slower frequency with more relaxed timing, a onecycle reset pulse may be possible. (Modify the PAL program accordingly.)

Once in S1, when MRS_IN goes from LOW to HIGH, the state ma-chine changes to S2, which provides a one cycle delay while continuing tohold LD_OUT HIGH, SEN_OUT HIGH, and SI/FWFT at whichever levelcorresponds to the desired timing mode. The purpose of S2 is to holdthese PAL output levels for an additional cycle, so that the reset recoverytime (tRSR) is satisfied.

One cycle later, S2 passes on to S3 and the serial load function com-mences. The remaining states of the machine are used to clock out theoffsets–one bit per state. Since, on SuperSync FIFOs, both PAE andPAF can be set anywhere in memory, the deeper FIFOs require moreoffset bits to specify flag threshold locations. The deepest SuperSync isthe IDT72271 (32,768 words deep). The offsets for this device contain acombined total number of 30 bits. Therefore, the maximum number ofstates required for holding offset bits is 30. If a smaller size FIFO is used,then the number of states required to implement the machine will be corre-spondingly less.

Upon entering S3, each WCLK rising edge advances the machine onestate. Each state transmits one bit starting with the PAE offset LSB andending with the PAF offset MSB. During this period, SEN_OUT andLD_OUT are held LOW (the SEN and LD on the FIFO, respectively), andoffset bits are placed on SER_OUT (FWFT/SI on the FIFO).

After the last bit has been clocked out (S32 in the IDT72271 example),the PAL first deasserts SEN_OUT, then deasserts LD_OUT one cycle later.LD’s greater hold time requirement accounts for the different deassertiontime. Finally, the machine transitions to a wait state, S0 if MRS_IN is HIGHor to S1 if MRS_IN is LOW.

S0RESETHIGH

S1RESET

LOW

S2RESET

RECOVERY

S3PAE LSB

BIT 0

S10PAE LSB

BIT 7

S11PAEMSBBIT 0

S17PAEMSBBIT 6

NO OP

MRS = 1

MRS = 1, FOR CE 0/1/X

MRS = 0FO RCE 1/1/FWFT

MRS = 0

FO RC E 0/1/X

FO RCE 1/1/X FO RCE 1/1/FWFT

FO RCE 1/1/FWFT

FO RCE 1/1/FWFTMRS = 0

MRS = 1FO RCE 1/1/FWFT

FO RCE 0/0/SI

FO RCE 0/0/SI

FO RCE 0/0/SI

FO RCE 0/0/SI

S25PAF LSB

BIT 7

S32PAF MSB

BIT 6

S18PAF LSB

BIT 0

S26PAF MSB

BIT 0

MRS = 0

MRS = 1

FO RCE 0/0/SI

FO RCE 0/0/SI

FO RCE 0/0/SI

FO RCE 0/0/SI

3144 d rw 08


48

NO

TES:

1.tC

O =

Clo

ck-to

-out

put D

elay

, tSU

= S

etup

Tim

e. (t

CO

= 4

.5 n

s m

ax. a

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U =

5 n

s m

in. f

or th

e La

ttice

GAL

22V1

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ns

spee

d gr

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)2.

Follo

win

g po

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up,

the

stat

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gin

oper

atio

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S0

if M

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MR

S_IN

is L

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.3.

To e

nsur

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eetin

g th

e R

eset

Set

up T

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(tRSS

) for

LD

, SE

N a

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WFT

/SI,

MR

S_IN

mus

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held

LO

W fo

r at l

east

two

WC

LK c

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s. A

s a

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lt, th

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achi

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ay in

S1

for t

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cons

ecut

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CLK

cyc

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4.At

Mas

ter R

eset

: to

sele

ct F

irst W

ord

Fall

Thro

ugh

timin

g, s

et F

WFT

to 1

, to

sele

ct ID

T St

anda

rd ti

min

g, s

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WFT

to 0

.

Figu

re 9

. 20V

10 P

AL T

imin

g


49

POWER UP CONSIDERATIONSOn power up, some PALs are initialized to a known state, others can

begin operation in any one of the available machine states. To ensureproper initialization of the machine, a “go-to” command has been insertedinto every state listing of the ABEL program. For all functional states, thiscommand effectively says that any time a LOW is detected on MRS_IN, goto S1 and wait for completion of the reset pulse.

Note that if the PAL powers up in any state from S1 through S32 andMRS_IN is not LOW, the bit-loading function will proceed from that state.In this case, switching on SEN_OUT, LD_OUT, and SER_OUT may par-tially program the SuperSync FIFO before a Master Reset. This is of noconcern, since, once the system is properly reset (using the same pulse forMRS on the FIFO and MRS_IN on the PAL), the bit-loading function willstart from the beginning.

Since only 33 of the 64 states specified by U, V, W, X, Y, and Z are usedin the design, 31 non-operational states remain. During power up, it maybe possible for the PAL to wake up in one of these “NO-OP” states. There-fore, it is important to identify these states in the PAL program and assigngo-to commands, two for each NO-OP state. The first says that if MRS_INis LOW, go to S1 and wait for completion of the reset pulse. The secondsays that if MRS_IN is HIGH, go to S0 and wait for the beginning of a resetpulse.

PALS VERSUS SERIAL EEPROMSSerial EEPROMs are often used for serial boot operations. However,

when constructing an interface to SuperSync FIFOs, a PAL solution hascertain advantages. For example, on many serial EEPROMs, the only wayto control data operations is to use a header byte, which must precede dataon the serial input. This header byte sets start/stop, read/write, and ad-dress conditions. The serial boot application at hand would involve send-ing one header byte to an EEPROM for every row of data accessed. Sinceone important goal of the SuperSync serial boot circuit is keeping bus andprocessor free to perform other activities, sending these header bytes wouldrequire extra, dedicated logic, for instance, a PAL. However, since a single20V10 PAL can accommodate the entire serial boot function including off-set storage, the serial EEPROM becomes unnecessary. The single PALsolution costs less and saves board space.

Another factor to consider is maximum frequency of the SuperSyncWCLK operation, since currently available Serial EEPROMS run at abouta 5 MHz clock frequency. If the frequency that a SuperSync application isrunning at is higher, it will have to be divided down to the EEPROM operat-ing range, necessitating additional external logic. Again, the single PALsolution is preferable, since 20V10s capable of operating at 100MHz (4.5ns clock to data) are available at a reasonable cost.

USING A 16V8 PALThe solution offered meets the most stringent requirements of

SuperSync operation: programming the greatest number of offset bits (30bits into the IDT72271) at the highest frequency (100 MHz). For many lessdemanding applications, it is possible to use the smaller, cheaper 16V8PAL. For example, the present design uses 9 registered outputs; requiringa 22V10. If a particular application permits a design simplification that re-duces the number of outputs to 8, then a 16V8 can be used. One way toachieve this is to combine the LD_OUT and SEN_OUT functions by usinga single output that can drive both LD and SEN on the FIFO, while satis-fying the hold time for each signal.

There are still other approaches: Note that the present design uses atotal of 33 states for loading 30 offset bits into the IDT72271. If the num-ber of states can be reduced to 32 or less, the most significant state vari-able and its corresponding registered output (U) can be eliminated, thuspermitting a 16V8 to be used. For example, if any of the three smallerSuperSync FIFOs (IDT72255, IDT72265, or IDT72261) are used, the num-ber of offset bits required to program the flags will be less than that re-quired by the IDT72271. Fewer bits means fewer states.

Another way of achieving a 32-state machine is by eliminating thewait state, S2. It is possible that the timing of a particular application maynot require S2, yet still satisfy Master Reset recovery requirements.

CONCLUSIONAn important feature of IDT’s new SuperSync FIFO family is the abil-

ity to load programmable flag offsets in serial or parallel fashion. TheSuperSync FIFO family consists of four exceptionally deep FIFOs: theIDT72255 (8,192 words x 18 bits), the IDT72265 (16,384 words x 18 bits),the IDT72261 (16,384 x 9 bits), and the IDT72271 (32,768 words x 9 bits).

Serial programming can be especially useful since it does not need touse the FIFO’s parallel data bus, which is left free to perform other tasks.As has been shown, a single PAL can be used not only to serially load flagoffsets, but also to configure the FIFO during Master Reset (i.e. selectserial programming, and choose between IDT Standard mode and FirstWord Fall Through timing). The advantages of using programmable logicare manifold: low cost, high speed, low part count, small board areausage, and ease of reprogramming.

The design example discussed in this paper serially loads a total of30 offset bits (the maximum possible number) into the IDT72271 at afrequency of 100MHz (the maximum possible frequency). The serial load-ing function was implemented as a state machine, written in the ABELlanguage, and programmed into a Lattice GAL20V10 (7 ns speed grade).For many applications, timing requirements will be less stringent. For theIDT72255, the IDT72265, and the IDT72261, the total number of offsetbits is less. In such cases, a 16V8 PAL will be suitable.


50

APPENDIX: ABEL PROGRAM LISTINGMODULE SERLOADTITLE ‘IDT72271 100 MHZ SERIAL LOAD’

DECLARATIONS

SERLOAD DEVICE ‘P22V10’;

WCLK_IN PIN 1;MRS_IN PIN 2;

LD_OUT PIN 23, ISTYPE ‘REG’;SEN_OUT PIN 22, ISTYPE ‘REG’;SER_OUT PIN 21, ISTYPE ‘REG’;U PIN 20, ISTYPE ‘REG’;V PIN 19, ISTYPE ‘REG’;W PIN 18, ISTYPE ‘REG’;X PIN 17, ISTYPE ‘REG’;Y PIN 16, ISTYPE ‘REG’;Z PIN 15, ISTYPE ‘REG’;

ST_VAL = [U,V,W,X,Y,Z];

S0 = [0,0,0,0,0,0];S1 = [0,0,0,0,0,1]; “RESET, CONFIGURE FIFOS2 = [0,0,0,0,1,0]; “RESET RECOVERYS3 = [0,0,0,0,1,1]; “PAE LSB BIT0S4 = [0,0,0,1,0,0]; “PAE LSB BIT1S5 = [0,0,0,1,0,1]; “PAE LSB BIT2S6 = [0,0,0,1,1,0]; “PAE LSB BIT3S7 = [0,0,0,1,1,1]; “PAE LSB BIT4S8 = [0,0,1,0,0,0]; “PAE LSB BIT5S9 = [0,0,1,0,0,1]; “PAE LSB BIT6S10 = [0,0,1,0,1,0]; “PAE LSB BIT7S11 = [0,0,1,0,1,1]; “PAE MSB BIT0S12 = [0,0,1,1,0,0]; “PAE MSB BIT1S13 = [0,0,1,1,0,1]; “PAE MSB BIT2S14 = [0,0,1,1,1,0]; “PAE MSB BIT3S15 = [0,0,1,1,1,1]; “PAE MSB BIT4S16 = [0,1,0,0,0,0]; “PAE MSB BIT5S17 = [0,1,0,0,0,1]; “PAE MSB BIT6S18 = [0,1,0,0,1,0]; “PAE LSB BIT0S19 = [0,1,0,0,1,1]; “PAF LSB BIT1S20 = [0,1,0,1,0,0]; “PAF LSB BIT2S21 = [0,1,0,1,0,1]; “PAF LSB BIT3S22 = [0,1,0,1,1,0]; “PAF LSB BIT4S23 = [0,1,0,1,1,1]; “PAF LSB BIT5S24 = [0,1,1,0,0,0]; “PAF LSB BIT6S25 = [0,1,1,0,0,1]; “PAF LSB BIT7S26 = [0,1,1,0,1,0]; “PAF MSB BIT0S27 = [0,1,1,0,1,1]; “PAF MSB BIT1S28 = [0,1,1,1,0,0]; “PAF MSB BIT2S29 = [0,1,1,1,0,1]; “PAF MSB BIT3S30 = [0,1,1,1,1,0]; “PAF MSB BIT4S31 = [0,1,1,1,1,1]; “PAF MSB BIT5S32 = [1,0,0,0,0,0]; “PAF MSB BIT6

S33 = [1,0,0,0,0,1]; “NO OPS34 = [1,0,0,0,1,0]; “NO OPS35 = [1,0,0,0,1,1]; “NO OPS36 = [1,0,0,1,0,0]; “NO OPS37 = [1,0,0,1,0,1]; “NO OPS38 = [1,0,0,1,1,0]; “NO OPS39 = [1,0,0,1,1,1]; “NO OPS40 = [1,0,1,0,0,0]; “NO OPS41 = [1,0,1,0,0,1]; “NO OPS42 = [1,0,1,0,1,0]; “NO OPS43 = [1,0,1,0,1,1]; “NO OPS44 = [1,0,1,1,0,0]; “NO OPS45 = [1,0,1,1,0,1]; “NO OPS46 = [1,0,1,1,1,0]; “NO OPS47 = [1,0,1,1,1,1]; “NO OPS48 = [1,1,0,0,0,0]; “NO OPS49 = [1,1,0,0,0,1]; “NO OPS50 = [1,1,0,0,1,0]; “NO OPS51 = [1,1,0,0,1,1]; “NO OPS52 = [1,1,0,1,0,0]; “NO OPS53 = [1,1,0,1,0,1]; “NO OPS54 = [1,1,0,1,1,0]; “NO OPS55 = [1,1,0,1,1,1]; “NO OPS56 = [1,1,1,0,0,0]; “NO OPS57 = [1,1,1,0,0,1]; “NO OPS58 = [1,1,1,0,1,0]; “NO OPS59 = [1,1,1,0,1,1]; “NO OPS60 = [1,1,1,1,0,0]; “NO OPS61 = [1,1,1,1,0,1]; “NO OPS62 = [1,1,1,1,1,0]; “NO OPS63 = [1,1,1,1,1,1]; “NO OP

EQUATIONS

LD_OUT.CLK = WCLK_IN;SEN_OUT.CLK = WCLK_IN;SER_OUT.CLK = WCLK_IN;U.CLK = WCLK_IN;V.CLK = WCLK_IN;W.CLK = WCLK_IN;X.CLK = WCLK_IN;Y.CLK = WCLK_IN;Z.CLK = WCLK_IN;

STATE_DIAGRAM ST_VAL

STATE S0: “WAITING FOR MASTER RESETIF !MRS_IN THEN S1

WITHLD_OUT := 1;SEN_OUT := 1;SER_OUT := 0;ENDWITH;

ELSE S0WITHLD_OUT := 1;


51

SEN_OUT := 1;SER_OUT := 0;ENDWITH;

STATE S1: “MASTER RESET PULSE LOWIF !MRS_IN THEN S1


ELSE S2WITHLD_OUT := 1;SEN_OUT := 1;SER_OUT := 0;ENDWITH;

STATE S2: “MASTER RESET RECOVERYIF !MRS_IN THEN S1


ELSE S3WITHLD_OUT := 0;SEN_OUT := 0;SER_OUT := 1; “PAE LSB BIT0ENDWITH;

STATE S3:IF !MRS_IN THEN S1WITHLD_OUT := 1;SEN_OUT := 1;SER_OUT := 0;ENDWITH;


STATE S4:IF !MRS_IN THEN S1



SEN_OUT := 0;SER_OUT := 1; “PAE LSB BIT2ENDWITH;














52

SEN_OUT := 0;SER_OUT := 1; “PAE LSB BIT6ENDWITH;






ELSE S11WITHLD_OUT := 0;SEN_OUT := 0;SER_OUT := 1; “PAE MSB BIT0ENDWITH;







SEN_OUT := 0;SER_OUT := 0; “PAE MSB BIT2ENDWITH;














53

SEN_OUT := 0;SER_OUT := 0; “PAE MSB BIT6ENDWITH;



ELSE S18WITHLD_OUT := 0;SEN_OUT := 0;SER_OUT := 1; “PAF LSB BIT0ENDWITH;










SEN_OUT := 0;SER_OUT := 0; “PAF LSB BIT3ENDWITH;














54

SEN_OUT := 0;SER_OUT := 0; “PAF LSB BIT7ENDWITH;



ELSE S26WITHLD_OUT := 0;SEN_OUT := 0;SER_OUT := 1; “PAF MSB BIT0ENDWITH;










SEN_OUT := 0;SER_OUT := 1; “PAF MSB BIT3ENDWITH;














55


STATE S33: “NO OPIF !MRS_IN THEN S1


























56




























57




























58



www.idt.com












WITHLD_OUT := 1;SEN_OUT := 1;

SER_OUT := 0;ENDWITH;











END SERLOAD



By Kim Goldblatt

• Independent use of FIFOs• Two-level prioritization of data• Network switching• Width expansion• Depth expansion• Bidirectional application• Bus matching

INTRODUCTIONIDT offers two families of dual FIFOs. Each device contains two

independent FIFO functions in one package. The IDT728x1 family consistsof five members: the 72801, the 72811, the 72821, the 72831, and the72841. The FIFOs contained in each of these dual products are 9 bits wide,synchronous, as well as electrically and functionally compat-ible with thewidely-used 722x1 FIFO family, the 72201, the 72211, the 72221, the72231, and the 72241, respectively. Table 1 lists the basic attributes of the7278x1 family.

The IDT728x5 family consists of three members: the 72805, the 72815,and the 72825. The FIFOs contained in each of these dual products are 18bits wide, synchronous, as well as electrically and functionally compatiblewith the well-known 722x5 FIFO family, (the 72205, the 72215, and the72225, respectively). Table 2 lists the basic attributes of the 728x5 family.

The most important advantage of Dual FIFOs is board space savings.A dual 728x1 (or 728x5) FIFO can perform any function two individual722x1 (or 722x5) FIFOs can, and, at the same time, occupies only half theboard space. The 728x1 family is available in a 64-lead Thin Quad Flat Pack(TQFP) which has an area of 248 mm 2 . The 728x5 family is available in a

Table lI: 728X5 Family Attributes

Table I: 728X1 Family Attributes

72805LB72815LB72825LB

Dual 256 x 18 Dual 512 x 18Dual 1024 x 18

Two 72205LBTwo 72215LBTwo 72225LB

50 50

50

121-pin BGA 121-pin BGA121-pin BGA

Part Number

Part Number

Organization

Organization

FunctionallyEquivalent

To

FunctionallyEquivalent

To

Max Clock Frequency

(MHz) Package

Package Max Clock Frequency

(MHz)

64-pin TQFP64-pin TQFP64-pin TQFP64-pin TQFP64-pin TQFP50

5050

67 67

Two 72201Two 72211Two 72221Two 72231Two 72241

Dual 256 x 9Dual 512 x 9

Dual 1,024 x 9 Dual 2,048 x 9 Dual 4,096 x 9

72801L72811L72821L72831L72841L

Dual SyncFIFO Applications Using the728x1 and 728x5 Families

Application Note

AN-134

DSC-3164

February 1995

121-lead Ball Grid Array (BGA) which has an area of 225 mm2 .The two-FIFO-per-package arrangement lends itself to a wide variety of

useful applications. Such as: Using FIFOs independently, two-level dataprioritization, network switching, width expansion, depth expansion, bidi-rectional configuration, and bus matching. While it is true that any of theseapplications can be implemented using individual FIFOs (i.e. one FIFO perpackage), the Dual FIFOs facilitate the process in designs where boardspace is at a premium.

INDEPENDENT FIFOSThe only lines shared in common between the two FIFOs of a dual

device are VCC and GND. All control and data inputs, as well as status anddata outputs operate independently for each FIFO. Therefore, no functionperformed by one FIFO can adversely affect the operation of the otherFIFO. The designer is free to use the two FIFOs for completely unrelatedfunctions.

TWO-LEVEL PRIORITIZATION OF DATAThe two-FIFO-per-package arrangement is useful for sort-ing two

different kinds of data that share the same bus. This application is particu-larly useful for multi-media computing. Figure 1 shows how a 728x1 FIFOcan be used to sort image and voice data. A processor places both kinds ofdata on a 9- bit bus. One FIFO (designated A) is assigned the functionofrelaying image data from the processor bus to an image processing card,the other FIFO (designated B) is assigned the function of sending voice datato a voice processing card. The processor’s address and data lines aredecoded to enable writing to either FIFO A or FIFO B.

60

Figure 1: IDT728x1 Two-level Data Prioritization

Though, members of the 728x1 family all have redundant read enables(RENA1 and RENA2 , RENB1 and RENB2), as well as redundantwrite enables ( WENA1 and WENA2 , WENB1/ LDB and WENB2/LDB), only one read enable and one write enable is required from each FIFO.As shown in Figure 1, RENA1 and RENB1 are used to perform the readenable function. The unused RENA2 and RENB2 lines are grounded.WENA1 and WENB1 are used to perform the write enable function.WENA2/LDA and WENB2/LDB act as write enables if HIGH during reset,flag offset load enables if LOW during reset. Since these lines areunecessary , they should be hard-wired to Vcc.

In the event partia l flag programming is desired, WENA2/ LDA andWENB2/LDB may be configured for the flag offset load enable functionmay be selected; however, following Master Reset, care should be takento disable loading until the time of programming.

This kind of application is effective not only for sorting different kinds ofdata, but also, different priority levels of data; in this way, it can be describedas two-level data prioritization. By adding more Dual FIFOs, any number ofdifferent priority levels or data types can be sorted.

Figure 2 shows how the 728x5 can be used for sorting two different kindsof data on an18-bit bus. The connections are similar to the 728x1 example–only the 728x5 does not have redundant read and write enables. Since, forthis application, the 728x5 operates in single device mode (as opposed todepth expansion mode), the first load inputs (FLA , FLB ), as well as theread and write expansion inputs ( RXAI and RXIB , WXIA and WXIB) should be tied to GND.

NETWORK SWITCHINGNetwork switching products commonly employ large quantities of

FIFOs to switch data from one network destination to another. Dual FIFOsprove invaluable for this type of application since they can cut the boardarea used by a one-FIFO-per- package implementation in half.

The network switchbox design illustrated in Figure 3 shows how FIFOscan be used to switch data between any combina-tion of available input andoutput buses. Data flow is unidirectional. Dual FIFOs are used not only to

buffer the data, but also to manage address usage for a central data storagememory. In the present example, four input paths and four output paths areshown;however, the design architecture can be easily expanded toaccomodate as many buses as desired. Such a network switchbox usingthe 728x1 is capable of switching 9-bit wide buses; a switchbox using the728x5 is capable of switching 18-bit buses.

One bank of FIFOs is used to buffer incoming data–one FIFO for eachinput bus. (In the diagram, these “Source FIFOs” are labeled A, B, C, andD.) Another bank of FIFOs is used to buffer outgoing data–one FIFO foreach output bus. (In the diagram, these “Destination FIFOs” are labeled 1,2, 3, and 4.)

An SRAM data storage block is used to hold cells of information alreadyreceived via the Source FIFOs and awaiting transfer to the DestinationFIFOs. For example, ATM cells, typically consist of a five byte header(containing address information) and a 48-byte string of data. A networkswitch box will handle these components differently. The SRAM may bepartitioned into a header section and a data section for more efficientprocessing of cell components.

The “Free Address” FIFO keeps track of vacant address locations in theSRAM storage block.

A final set of FIFOs, called “Available Cell” FIFOs, keep track of cellsstored in SRAM, waiting to be channeled to the Destination FIFOs. Each“Available Cell” FIFO is associated with one of the output data buses andholds the SRAM addresses of cells bound for that particular bus. (Thediagram shows four “Available Cell” FIFOs, designated 1, 2, 3, and 4.)

A microprocessor monitors the switch box status, assigns addresses,and controls data movement.

The network switch box functions as follows: The ProgrammableAlmost Full ( PAF ) flags of the Source FIFOs are set to switch LOW afterreceiving at least one cell of data. The processor periodically checks thePAF flag of each Source FIFO. As soon as a cell gets written to one ofthe Source FIFOs, the associated PAF flag goes LOW indicating data isavailable. The processor responds by obtaining an available SRAM ad-dress from the Free Address FIFO, then reading the cell from the Source

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ImageProcessing Card

Address

Contro l

Da ta

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VoiceProcessing Card

Address

Contro l

Da ta

ClockFIFO B

FIFO A

I/O Data

WENB1RENB1

W CLKBRC LKB

OEB

DB0-DB8

I/O Data

WENA1 RENA1

W CLKA

RC LKA

OEA

DA0- DA8QA0-QA8

9

728x5

9

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Contro l

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9

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WENB2 RENB2

WENA2 RENA2VCC

VCC

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NOTE:1. Tie FLA , FLB , WXIA , WXIB , RXIA , and RXIB to GND.

Figure 2: IDT728x5 Two-level Data Prioritization

FIFO and writing it into SRAM at the chosen free address. Once this hasbeen accomplished, the processor accesses the cell’s header from SRAMand identifies which Destination FIFO the data is bound for by interpretingand updating the eader. Then, the processor writes the cell’s SRAM addressto that Destination FIFO’s corresponding Available Cell FIFO.

The Programmable Almost Empty ( PAE ) flags of the Destination FIFOsare set to switch LOW as soon as sufficient space is available to accomodateone cell of data.The processor periodically checks the PAE flag of eachDestination FIFO. As soon as space is available in one of theDestinationFIFOs, the associated PAE flag goes LOW. The processorresponds by obtaining an address from the Destination FIFO’s correspond-ing Available Cell FIFO and using it to look up a cell stored in the SRAMmemory. Finally, the processor transfers the cell to the appropriate Destina-tion FIFO and enters the newly-freed cell address into the Free AddressFIFO.

WIDTH EXPANSIONExpanding the data bus width beyond the capacity of a single FIFO is

simply a matter of connecting FIFOs in parallel. In this way, one 728x1device can handle an 18-bit data bus (Figure 4), one 728x5 can handle a 36-bit bus (Figure 5). One half of the data lines is directed through the first FIFO,the other half is directed through the second FIFO. Data is written tobothFIFOs simultaneously and in parallel. In similar fashion, data is read fromboth FIFOs simultaneously and in parallel.

It is possible, due to normal variation of the tskew threshold between FIFOs,that EFA and EFB will deassert one cycle apart. Consider the case wherea word is written to an empty FIFO. The empty flag, which is synchronizedto the read clock, is LOW. If the time from the rising WCLK edge that wrotethe word to the next rising read clock edge is less than tskew (min.), thenempty flag deassertion requires a second rising read clock edge.

Note that this tskew effect can only occur on flag deassertion, never on flagassertion. To prevent the two FIFOs from getting out-of-step, EFA and

EFB should be AND-gated together to form a composite empty flag. Onlywhen both FIFOs have data available to be read, (both EFA and EFB areHIGH) will the composite empty flag go HIGH.

For similar reasons, the FFA and FFB should be AND-gated togetherto form a composite full flag. Consult the 728x1 and 728x5 datasheets formore information on tskew behavior.

Since, on the 728x1 family devices, PAEA , PAEB , PAFA , andPAFB are all synchronous, the skew issue applies. If a design calls fortheir use, PAEA and PAEB should be AND-gated together to make acomposite programmable almost empty flag; also, PAFA and PAFBshould be AND-gated together to make a composite programmable almostfull flag.

Since, on the 728x5 family devices, PAEA , PAEB , PAFA , andPAFB are all asynchronous, the skew issue does not apply. If a designcalls for their use, it is sufficient to monitor PAE and PAF on a singleFIFO. (Any FIFO in the width expansion may be chosen for this purpose.)

As shown in Figure 1, RENA1 and RENB1 are used to perform theread enable function. The unused RENA2 and RENB2 lines aregrounded. Unless WENA2/LDA and WENB2/LDB will be used to loadprogrammable flag offsets, they should be hard-wired HIGH since WENA1and WENB1 alone are sufficient to enable writes. If the flag offset loadenable function is selected, the lines should be LOW during reset, thenHIGH until the time of flag programming.

DEPTH EXPANSIONIn the event the deepest member of a FIFO family lacks sufficient depth

for a particular application, multiple FIFOs can be connected together toform a “depth expansion” whose total word capacity is the sum of theindividual FIFO depths. All Dual FIFO families can be depth-expandedusing at least one of the methods about to be described.

Since the goal of depth expansion is to increase the word storagecapacity beyond what is available for single FIFOs, it makes sense to talk

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Address

Control

Data

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Address

Control

Data

ClockFIFO B

FIFO A

I/O Data

WENBRENB

W CLKBRCLKB

OEB

DB0-DB17

QB0-QB17

I/O Data

WENA RENA

W CLKA

RCLKA

OEA

DA0-DA17

QA0-QA17

1818

728x5

18 18

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ADDRESSDECODER

FIRMWAREPOLLING O R INTERRU PT CONTROL

AVAILABLE CELL FIF O 1




FREEADDRESS FIFO

READ/WR ITE CONTROL

READ/WRITE CONTROL

READ/WRITE CONTROL

READ/WRITE CONTROL

READ/W RITECONTROL

READ/WRITE CONTROL

FIFO A

FIFO B

FIFO C

FIFO D

READ CONTRO L A

READ CON TROL B

READ CONTROL C

READCONTROL D

SOURCE FIFO s DESTINATIO N FIFOs

FIFO 1

FIFO 2

FIFO 3

FIFO 4

WRITECONTROL 1

WRITECONTROL 2

WRITECONTR OL 3

WRITECONTROL 4

728x1 or 728x5

728x1 or 728x5

PAF D

PAF C

PAF B

PAF A PAE 1

PAE 2

PAE 3

PAE 4

728x1 or 728x5

728x1 or 728x5

SRAMCELL STORAGE

HEADER DATA

728x1 or 728x5

728x1 or 728x5

MICR O-PROCESSOR

DATA A IN

DATA B IN

DATA C IN

DATA D IN

DATA 1 O UT

DATA 2 O UT

DATA 3 OUT

DATA 4 OUT

9-(o

r 18

)BIT

INT

ER

NA

L D

AT

A

AD

DR

ES

S B

US

Figure 3: Network Switch Box (9-bit version uses the 728x1, 18-bit version uses the 728x5).

63

Figure 4: IDT728x1 18-bit Width Expansion

about employing thedeepest Dual FIFOs in this way.If an application requires a data path width of 9-bits and a word depth in

excess of 4,096, then the two FIFOs contained in a 72841 can be configuredas a depth expansion with an overall organization of 8,192 x 9. For aboutthe same foot-print, this application offers twice the maximum availabledepth of the compatible 722x1 family. Figure 6 shows shows the connec-tions.

Because the 728x1 devices are not equipped with a daisy-chain feature,depth expansion is achieved by using a ping-pong-approach instead.The basic idea is to alternate writes between FIFOs A and B. Data is readout in the same order as was written, back and forth between FIFOs A andB. The data inputs (DAn, DBn) are connected in parallel, as are the dataoutputs (QAn, QBn). The system write clock drives both WCLKA andWCLKB. The system read clock drives both RCLKA and RCLKB.

The 728x1 lends itself to the ping-pong implementation, since each ofits two FIFOs has dual write enables and dual read enables. WENA2/LDAand WENB2/LDB are wired in parallel to start and stop the Dual FIFO writesequence. A flip-flop divides the system write clock frequency by a factor oftwo, creating two180° out-of-phase enable signals which synchronize theinterleaving of data writes. One of these lines drives WENA1 , the otherdrives WENB1.

RENA2 and RENB2 are wired in parallel to startand stop the DualFIFO read sequence. A flip-flop divides the system read clock frequency bya factor of two, creating two 180° out-of-phase enable signals whichsynchronize the interleaving of data reads. One of these lines drivesRENA1 and is also gated with the system read clock to produce an outputenable pulse which drives the OEB line. The other drives RENB1 and isalso gated with the system read clock to produce an output enable pulsewhich drives the OEA line. Using an OR gate to shape the output enablepulses eliminates contention on the outputs.

EFA and EFB are OR -gated together to form a composite empty flagwhich will go LOW only when both FIFOA andFIFO B are empty. FFA andFFB are OR-gated together to form a composite full flag which will go LOW

only when both FIFO A and FIFO B are full.If an application demands a data path width of 18-bits and a word depth

in excess of 1,024 then the two FIFOs contained in a 72825 can beconfigured as a depth expansion with an overall organization of 2,048 x 18.Figure 7 demonstrates this application.

The 728x5 devices are capable of daisy chain depth expansion. For thispurpose, they are equipped with write expansion input and outputs ( WXIA, WXIB and WXOA , WXOB , respectively) and read Expansion inputand outputs ( RXIA , RXIB and RXOA , RXOB , respectively). Thedaisy chain approach employs less external logic than the ping-pongapproach. To implement the chain, the Write Expansion Out line of eachFIFO is connected to the Write Expansion In line of the next FIFO insequence; the Read Expanion Out line of each FIFO is connected to theRead Expansion In line of the next FIFO.Thedatainputs (Dn)areconnectedinparallel,as are the data outputs (Qn). The system write clock drives bothWCLKA and WCLKB . The system read clock drives both RCLKA andRCLKB.

EFA and EFB are OR-gated together to form a composite empty flagwhich will go LOW only when both FIFO A and FIFO B are empty. FFA andFFB are OR-gated together to form a composite full flag which will go LOWonly when both FIFO A and FIFO B are full.

BIDIRECTIONAL CONFIGURATIONFor applications that require two-way communication, say from a

processor to a peripheral and from the peripheral back, Dual FIFOsconveniently permit bidirectional data flow all within a single package: oneof the FIFOs is used to transmit information in one direction, the other FIFOis used to transmit in the reverse direction.

Figure 8 uses a member of the 728x1 family to transfer 9-bit-wide datain two directions. The data bus on the processor side is connected to thedata inputs (DAn) of FIFO A and the data outputs (QBn) of FIFO B. The databus on the peripheral side is connected to the data inputs (DBn) of FIFOB and the data outputs (QAn) of FIFO A. The processor’s address and

RESET

DATAIN

WRITE ENABLE

WRITE ENABLE/LOAD

WRITE CLOCK

OUTPUT ENABLE

READ ENABLE

DATA OUT

9

18 9

18

9

FIFOB

256 X 9512 X 9

1024 X 92048 X 94096 X 9

RENB2

RENA 2

RENB1

OEB

QA0 - QA8

QB0 - QB8

DB0 - DB8 RSBRSA

WCLKA

DA0 - DA8

RCLKA

WENA1

WENA2/LDA

OEA

WENB2/LDB

WENB1

WCLKB

RCLKB

3164 d rw 04

FIFOA

256 X 9512 X 9

1024 X 92048 X 94096 X 9

FULL FLAG

RENA1

9

EFB

EFA

FFA

FFB

READ CLOCK

EMPTY FLAG


64

NOTE:1. Tie FLA , FLB , WXIA , WXIB , RXIA , and RXIB to ground.

Figure 5: IDT728x5 36-bit Width Expansion

control lines are decoded to enable writes to FIFO A, as well as, enablereads and activate data outputs on FIFO B. The peripheral’s address andcontrol lines are decoded to enable writes to FIFO B, as well as, enablereads and activate data outputs on FIFO A. For each FIFO, only one of theredundant write enables ( WENA1 and WENB1 ) are required. WENA2/LDA and WENB2/LDB should be configured as secondary write enablesand tied to Vcc. Likewise, only one of theredundant read enables ( RENA1and RENB1 ) are required. The unused read enables are grounded.

The processor monitors FFA of FIFO A and EFB of FIFO B. Theperipheral monitors FFB of FIFO B and EFA of FIFO A.

Figure 9 uses a member of the 728x5 family to transfer 18-bits of datain two directions.

BUS-MATCHINGThese days, microprocessor-based systems employ a wide variety of

bus widths: 9-bit, 16-bit, 32-bit, and even 64-bit. Communicating betweenbuses of different width is known as bus-matching. The Dual FIFO is an idealdevice for implementing the bus-matching function, since two FIFOs can beconfigured to match various bus widths.

Figure 10 shows how a 728x1 device can be used to perform 18-to-9 bitbus-matching. The data inputs (Dn) of both FIFOs are used side-by-side fora full 18-bit-wide input data path. Data is written to both FIFOs simulta-neously and in parallel.

Though the 728x1 comes with redundant write enables, only one writeenable is required from each FIFO. This example only requires the use ofWENA1 and WENB1. WENA2/LDA and WENB2/LDB should be configuredas secondary write enables and tied HIGH. The corresponding data outputs(QAn, QBn) of both FIFOs are tied together to produce a 9-bit-wide outputdata path. RENA2 and RENB2 are wired in parallel to start and stop the DualFIFO read sequence. A flip-flop divides the system read clock frequency bya factor of two, creating two 180° out-of-phase enable signals which

synchronize the interleaving of data reads onto the 9-bit bus. One of theselines drives RENA1 of FIFO A and OEB of FIFO B, the other drives RENB1of FIFO B and OEA of FIFO A. Therefore, the same time data is beingaccessed from FIFO A , FIFO B’s outputs are enabled with valid data–readyto be captured. In the next cycle, FIFO A’s outputs are enabled with validdata, and FIFO B's outputs are disabled in preparation for another dataaccess. Note that a brief period of contention between FIFO A’s and FIFOB’s outputs will occur at the moment outputs are enabled on one FIFO anddisabled on the other. Such short contention is considered acceptable, andwill in no way compromise the reliable performance of the Dual FIFO.

As an optional measure, two OR gates can be added to completelyeliminate the output contention. An example of this practise is shown in theping-pong application, described in the section entitled “Depth Expansion”.

EFA and EFB are OR gated together to form a composite empty flagwhich will go LOW only when both FIFO A and FIFO B are empty.

Whether or not the tskew specification is met could conceivably causeone of the full flags to deassert a cycle ahead of the other. This is normal.To prevent the FIFOs from getting out-of-step, FFA and FFB should beAND-gated together to form a composite full flag. Then, only when bothFIFOs have space available for writing (i.e. both FFA and FFB are HIGH)will the composite full flag go HIGH. See the “Width Expansion” section fora more detailed description of how the tskew parameter effects flagperformance.

Figure 11 shows how a 728x5 device can be used to perform a 36-to-18 bit bus-matching function. In this case, the data inputs (DAn, DBn) ofboth FIFOs are used side-by-side for a full 36-bit-wide input data path. Datais written to both FIFOs simultaneously and in parallel. The data outputs(QAn, QBn) of both FIFOs are tied in parallel to produce an 18-bit-wideoutput data path. Data is read, alternating between FIFOs.

The 728x5 comes with neither redundant write enables nor redundantread enables. Only WENA and WENB are available to implement parallel

RESET

DATAIN

WRITE ENABLE

WRITE CLOCK

OUTPUT ENABLE

READ ENABLE

DATA OUT

18

36 18

36

18

FIFOB

256 X18512 X18

1024 X18

RENB

OEB

QA0 - QA17

QB0 - QB17

DB0 - DB8 RSBRSA

WCLKA

DA0 - DA17

RCLKA

WENA

OEA

WENB

WCLKBRCLKB

3164 d rw 05

FIFOA

256 X18512 X18

1024 X18FULL FLAG

RENA

18

EFB

EFA

FFA

FFB

READ CLOCK

EMPTY FLAG


65

Figure 6: IDT728x1 8K x 9 Depth Expansion Using the Ping-Pong Approach

writes to FIFO A and FIFO B. However, accessing data for a 36-to-18 bit busmatching application requires control of the reading process on two differentlevels: alternating reads between FIFO A and FIFO B, and the ability to startand stop the Dual FIFO read sequence. Interleaved reads are accom-plished by creating two 180° out-of-phase “internal” read enable signals todrive RENA and RENB , just as was done in the preceding 728x1 bus-matching application. Initiating and terminating the read process is handledby OR-gating each of the internal enables independently to the externallydriven read enable.

As in the 728x1 design, EFA and EFB are OR-gated together to forma composite empty flag, FFA and FFB are AND-gated together to form acomposite full flag.

For matching larger bus widths, more than one Dual FIFO can be usedtogether. Figure 12 shows how two 728x1 devices can be used toperform 36-to-9 bit bus-matching. The data inputs (DAn,DBn) of all fourFIFOs are used side-by-side for a full 36-bit-wide input data path. Data iswritten to all four FIFOs simultaneously and in parallel.

In this example, two pairs of WENA1 and WENB1 are used to enablewrites to the four FIFOs. WENA2/LDA and WENB2/LDB , are not needed.Unless the partial flags need program-ming, these lines should be config-ured as redundant write enables and tied to VCC. The data outputs (QAn,QBn) of all four FIFOs are tied in parallel to produce a 9-bit-wide output datapath. A PAL uses the system read clock signal to create four read enablesignals, each running at a quarter of the original frequency, each separatedfrom its neighbors by a 90° phase difference. These signals are used tocycle through the four FIFOs, executing reads in sequence. Following adata access from the last FIFO in line, reading continues with the first FIFO.Each signal is connected to the output enable line ( OEA or OEB ) of oneFIFO and also to a read enable line ( RENA1 or RENB1 ) on the nextFIFO in the read sequence. In this way, each signal enables the outputs of

the first FIFO for data capture at the same time it enables a new data accesson the next FIFO in line. One PAL input serves as a system-level readenable which initiates and terminates the read process. Internal to the PAL,this signal exercises control over all four of the 90° out-of-phase PALoutputs. The redundant read enable pins RENA2 and RENB2 areunecessary and should be grounded.

EFA and EFB of both Dual FIFOs are all OR-gated together to forma composite empty flag which will go LOW only when both FIFO A and FIFOB are empty.

FFA and FFB of both DualFIFOs should be AND-gated together toform a composite full flag. Then, only when all four FIFOs have spaceavailable for writing (i.e. both pairs of FFA and FFB are HIGH) will thecomposite empty flag go HIGH.

Figure 13 shows how two 728x5 devices can be used to perform 72-to-18 bit bus-matching. The data inputs (DAn, DAn) of all four FIFOs are usedside-by-side for a full 72-bit-wide input data path. Data is written to all fourFIFOs simultaneously and in parallel. In this example, two pairs of WENAand WENB are used to enable writes to the four FIFOs.

The data outputs (QAn, QBn) of all four FIFOs are tied in parallel toproduce an 18-bit-wide output data path. As in the preceding example, aPAL uses the system read clock signal to create four read enable signals,each running at a quarter of the original frequency, each separated from itsneighbors by 90° phase difference. These signals are used to cyclethrough the four FIFOs, executing reads in sequence. Each signal isconnected to the output enable line ( OEA or OEB ) of one FIFO and alsoto the read enable line ( RENA or RENB ) on the next FIFO in the readsequence. In this way, one signal enables the outputs of the first FIFO fordata capture at the same time it enables a new data access on the nextFIFO in line. One PAL input serves as a system-level read enable whichinitiates and terminates the read process.

DATAIN

READENABLE

WRITECLO CK

DATA OUT

9

9

FIFOB

QA 0 - QA8 QB 0 - QB8

DB0 - DB8

RSBRSA

WCLKA

DA0 - DA8

RCLKA

WENA1

OEA

WENB

WCLKB

3164 drw 06

FULLFLAG

EFAEFB

FFA FFB

EM PTY FLAG

FIFOA

RENA2

9

9 9

9

4096 x 9 4096 x 9

RENA1

WENA2/LDA WEN B2/LDB

OEB

RENB2

RENB1

728x1

RCLKB

READ R EF

TFF

TFF

2

Q

Q

T

2

Q

Q

T

.

.

.

.

WRITE ENABLE/LOAD

WRITE REF

READ CLOCK

RESET


66

Figure 7: IDT728x5 2K x 18 Depth Expansion Using the Daisy Chain Approach

Figure 8: IDT728x1 Bidirectional Configuration

Co

ntr

ol

L

og

ic

DMAClock

Address

Control

DataFIFO B

FIFO A

I/O Data

WENB1RENB1

WCLKB

RCLKB

OEB

DB0:DB8

WENA1RENA1

WCLKA RCLKA

OEA

DA 0:DA 8

QA0:

QA8

9

728x1

9

Co

ntr

ol

L

og

ic

ClockProcessor

Data

Address

Control

RAM

3164 drw 08

9

9

9

9

QB0:

QB8

RENB2 WENB2

WENA2 RENA2VCC

VCC

Peripheral Controller

99-b

it b

us

9-b

it b

us


FLB

RXIAWXIA

FFBEFA

1024 x 18

FIFO A

WXOA RXOA

WRITE CLOCK

DATA IN (D)

(WCLK)

3164 drw 07

FFB

RXIBWXIB

FLB EFB

1024 x 18

WXOB RXOB

FIFO B

LOAD (LD)

WRITE ENABLE(WEN)

RESET (RS)

VCC

FF

72825

EF

DATAOUT (Q)

READ CLOCK(RCLK)

READ ENABLE

(REN)

OUTPUTENABLE (OE)

67

Figure 9: IDT728x5 Bidirectional Configuration

NOTE:1. Tie FLA , FLB , WXIA , WXIB , and RXIA , RXIB to ground.

EFA and EFB of both Dual FIFOs are all OR-gated together to forma composite empty flag which will go LOW only when both FIFO A and FIFOB are empty.

FFA and FFB of both Dual FIFOs are all AND-gated together to forma composite full flag, which will go HIGH only when all four FIFOs havespace available for writing.

CONCLUSIONThe IDT728x1 family of nine-bit-wide Dual FIFOs offer two, indepen-

dent synchronous FIFOs in a 64-pin Thin Quad Flat Pack (TQFP) package.Each FIFO is functionally equivalent to the 722x1 FIFO family.

The IDT728x5 family of 18-bit-wide Dual FIFOs offer two, independentsynchronous FIFOs in a 121-pin Ball Grid Array (BGA) package. Each FIFOis functionally equivalent to the 722x5LB FIFO family.

The primary benefit of these new Dual FIFO families is to cut board areaoccupied by FIFOs in half. Therefore, the new families lend themselvesparticularly well to designs that require numerous FIFOs. Intensive data-buffering applications such as data sorting and network switching gain themost from using dual devices. However, other common ways of connectingmore than one FIFO, such as width expansion, depth expansion, bidirec-tional data flow, and bus matching also benefit.

Co

ntr

ol

L

og

ic

DMAClock

Address

Control

DataFIFO B

FIFO A

I/O Data

WENBRENB

WCLKB

RCLKB

OEB

DB0:DB17

WENARENA

WCLKARCLKA

OEA

DA0:DA17

QA0:

QA17

18

IDT728x5

18

Co

ntr

ol

L

og

ic

ClockProcessor

Data

Address

Control

RAM

3164 drw 09

18

18

18

18

QB0:

QB17

Peripheral Controller

1818

-bit

bu

s

18

-bit

bu

s


68

Figure 11: IDT728x5 36-to-18 Bit Bus-Matching

NOTE:1. Tie FLA , FLB , WXIA , WXIB , RXIA , and RXIB to GND.

Figure 10: IDT728x1 18-to-9-Bit Bus-Matching

RESET

DATAIN

WRITE ENABLE

WRITE CLOCK

READ ENABLE1

DATA OUT

18

9

FIFOB

RENB2

OEB

QA0 - QA8 QB0 - QB8

DB0 - DB8

RSBRSA

WCLKA

DA0 - DA8

RCLKA

WENA1

OEA

WENB1

WCLKB

RCLKB

3164 drw 10

FULL FLAG RENA2

EFA

EFB

FFA

FFB

READ CLOCK

EMPTY FLAG

FIFOA

WENA2/LDA WENB2/LDWRITE ENABLE/LOAD

728x1

RENA1

9

9 99

READ ENABLE2

RENB1

READ REF

Q

Q2

T

_..

RESET

DATAIN

WRITE ENABLE

WRITE CLOCK

DATA OUT

36

18

FIFOB

OEB

QA0 - QA17 QB0 - QB17

DB0 - DB17

RSBRSA

WCLKA

DA0 - DA17

RCLKA

WENA

OEA

WENB

WCLKB

RCLKB

3164 drw 11

FULL FLAG

EFA

EFB

FFA

FFB

READCLOCK

EMPTY FLAG

FIFOA

RENA

18

18 1818

RENB Q

Q

+2

T

READ REF

256 X18512 X18

1024 X18

256 X18512 X18

1024 X18

READ ENABLE


69


DA

TAIN

36

9

WR

ITE

ENAB

LE

WR

ITE

CLO

CK

FIFO

B

256

X18

512

X18

1024

X18

REN

B1O

EB

QA

0 -Q

A8

QB

0-Q

B 8

DB

0 - D

B8

RSB

RSA

WC

LKADA

0 - D

A8

RC

LKA

WE

NA

1

OEA

WE

NB

1

WC

LKB

RC

LKB

256

X18

512

X18

1024

X18

FU

LLFL

AG

R

ENA1

EFB

FFA

EFA

728x

1

FIFO

A

WEN

A2/

LDA

WR

ITE

EN

AB

LE/L

OAD

REN

A2

WE

NB2

/LD

B

FIFO

B

256

X18

512

X18

1024

X18

OEB

QA

0 -Q

A8

DB

0 - D

B8

RSB

RSA

WC

LKADA

0 - D

A8

RC

LKA

WEN

A1

OEA

WEN

B1

WC

LKB

256

X18

512

X18

1024

X18

R

ENA1

EFB

FFA

EFA

728x

1

FIFO

A

WEN

A2/

LDA

R

ENA2

WE

NB2

/LD

B

DAT

A O

UT

99

RES

ET

REN

B2

QB

0-Q

B 8RC

LKB

3164

drw

12

EMPT

Y

FLA

G

99

FFB

REN

B1

P

AL

22V1

0

R

EA

DE

NAB

LE

R

EAD

CLO

CK

FFB

R

ENB2

99

9

9

Figu

re 1

2: ID

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6-to

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70



www.idt.com



Since most of the electrical energy consumed by microelectronicdevices eventually appears as heat, poor thermal performance of thedevice or lack of management of this thermal energy can cause a variety ofdeleterious effects. This device temperature increase can exhibit itself asone of the key variables in establishing device performance and long termreliability; on the other hand, effective dissipation of internally generatedthermal energy can, if properly managed, reduce the deleterious effects andimprove component reliability.

A few key benefits of IDT's enhanced CMOS process are: low powerdissipation, high speed, increased levels of integration, wider operatingtemperature ranges and lower quiescent power dissipation. Because thereliability of an integrated circuit is largely dependent on the maximumtemperature the device attains during operation, and as the junction stabilitydeclines with increases in junction temperature (T

J), it becomes increas-

ingly important to maintain a low (TJ).

CMOS devices stabilize more quickly and at greatly lower temperaturethan bipolar devices under normal operation. The accelerated aging of anintegrated circuit can be expressed as an exponential function of thejunction temperature as:

tA = t

O exp [ Ea/ k ( 1/ T

O - 1/ T

J ) ]

wheretA

= lifetime at elevated junction (TJ) temperature.

tO

= normal lifetime at normal junction (TO) temperature.

Ea = activation energy (eV)k = Boltzmann's constant (8.617 x 10-5 ev/ k)

i.e. the lifetime of a device could be decreased by a factor of 2 for every10°C. increase temperature.

To minimize the deleterious effects associated with this potential in-crease, IDT has:

1. Optimized our proprietary low-power CMOS fabrication process toensure the active junction temperature rise is minimal.

2. Selected only packaging materials that optimize heat dissipation,which encourages a cooler running device.

3. Physically designed all package components to enhance theinherent material properties and to take full advantage of heattransfer and radiation due to case geometries.

4. Tightly controlled the assembly procedures to meet or exceed thestringent criteria of MIL-STD-883, to ensure maximum heattransfer between die and packaging materials.

When calculating junction temperature (TJ), it is necessary to know the

thermal resistance of the package (θJA) as measured in "degrees celsiusper watt". With the accompanying data, the following equation can be usedto establish thermal performance, enhance device reliability and ultimatelyprovide you, the user, with a continuing series of high speed, low-powerCMOS solutions to your system design needs.

θJA = [ TJ

- TA ] / P

TJ

= TA + P[ θJA ] = T

A + P[ θJC + θCA ]

where

θJC = ( TJ

- TC

) / P and θCA = ( TC

- TA ) / P

θ = Thermal resistanceJ = JunctionP = Operational power of device (dissipated)T

A= Ambient temperature in degrees celsius

TJ

= Temperature of the junctionT

C= Temperature of case/ package

θCA = Case to Ambient, thermal resistance - usually a measure ofthe heat dissipation due to natural or forced convection,radiation and mounting techniques.

θJC = Junction to Case, thermal resistance - usually measuredwith reference to the temperature at a specific point on thepackage (case) surface. (Dependent on the package materialproperties and package geometry).

θJA = Junction to Ambient, thermal resistance - usually measuredwith respect to the temperature of a specified volume of stillair. (Dependent on θJC + θCA, which includes the influenceof areas and environmental condition).

THERMAL PERFORMANCE CALCULATIONSFOR IDT'S PACKAGES

FIFOAPP

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