EE415 VLSI Design

Field Trip to Harris Harris SemiconductorSemiconductor

•Monday (February 28th)

•Leave at 9:00 AM from Stocker

•There will be a class on the 25th!!

•Will discuss Quiz 3

•Tour from ~1:30 PM to 4 PM

•Arrive in Athens after 8PM

•Bring cash for food

•No MAKE-UP please

EE415 VLSI Design

Read 4.1, 4.2

Start Reading 4.3

(dynamic CMOS)

COMBINATIONAL LOGIC

EE415 VLSI Design

As long as Fan-out Capacitance dominates

• Progressive Sizing:

CL

In1

InN

In3

In 2

Out

C1

C2

C3

M1 > M2 > M3 > MN

M1

M2

M3

MN

Distributed RC-line

Can Reduce Delay by more than 30%!

Example 4.3:

no sizing: tpHL = 1.1 nsec

with sizing: tpHL = 0.81 nsec

Fast Complex Gate - Design Techniques

EE415 VLSI Design

Fast Complex Gate - Design Techniques

•Transistor Ordering

In1

In3

In2

C1

C2

CL

M1

M2

M3

In3

In1

In2

C3

C2

CL

M3

M2

M1

(a) (b)

critical pathcritical path

EE415 VLSI Design

Fast Complex Gate - Design Techniques

•Improved Logic Design

EE415 VLSI Design

Fast Complex Gate - Design Techniques

•Buffering:• Isolate Fan-in from Fan-out

CLCL

Read Example 4.5

EE415 VLSI Design

Ratioed Logic

VDD

VSS

PDN

In1

In2

In3

F

RLLoad

ResistiveN transistors + Load

• VOH = VDD

• VOL = RDN

RDN + RL

• Asymmetrical response

• Static power consumption

•

• tpLH= 0.69 RL

CL

VDD

LPDNLpHL CRRt ||69.0

EE415 VLSI Design

Ratio Based Logic

Problems with Resistive Load

•IL = (VDD – Vout) / RL

•Charging current drops rapidly once Vout

starts to rise

Solution: Use a current source!

•Available current is independent of voltage

•Reduces tpLH by 25%

EE415 VLSI Design

Load Lines of Ratioed Gates

0.0 1.0 2.0 3.0 4.0 5.0Vout (V)

0

0.25

0.5

0.75

1

I L(N

orm

aliz

ed)

Resistive load

Pseudo-NMOS

Depletion load

Current source

EE415 VLSI Design

Active Loads

VDD

VSS

In1In2In3

F

VDD

VSS

PDN

In1In2In3

F

VSS

PDN

Depletion

LoadPMOSLoad

depletion load NMOS pseudo-NMOS

VT < 0

EE415 VLSI Design

Active Loads

Depletion mode NMOS load

•VGS = 0

•IL ~ (kn, load / 2) (|VTn|)2

•Deviates from ideal current source

•Channel length modulation

•Body effect

•VSB != VDD

•varies with Vout

•reduces |VTn|, hence IL for increasing Vout

EE415 VLSI Design

Active Loads

Pseudo-NMOS load

•No body effect, VSB = 0V

•VGS = - VDD , higher load current

•IL = (kp / 2) (VDD - |VTn|)2

•Larger VGS causes pseudo-NMOS load to leave

saturation mode sooner than NMOS

EE415 VLSI Design

Pseudo-NMOS

VDD

A B C D

FCL

VOH = VDD (similar to complementary CMOS)

kn VDD VTn– VOL

VOL2

2-------------–

kp

2------ VDD VTp– 2=

VOL VDD VT– 1 1kpkn------–– (assuming that VT VTn VTp )= = =

SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

For Vin = VDD:

NMOS linear

PMOS saturated

Read PP 206, 207, Example 4.6

EE415 VLSI Design

Pseudo-NMOS NAND Gate

VDD

GND

Out

EE415 VLSI Design

Improved Loads

A B C D

F

CL

M1M2 M1 >> M2Enable

VDD

Adaptive Load

Standby mode reduces power dissipation

EE415 VLSI Design

Improved Loads (2)

VDD

VSS

PDN1

Out

VDD

VSS

PDN2

Out

AABB

M1 M2

Dual Cascode Voltage Switch Logic (DCVSL)

EE415 VLSI Design

Example

B

A A

B B B

Out

Out

XOR-NXOR gate

EE415 VLSI Design

Pass-Transistor LogicIn

puts Switch

Network

OutOut

A

B

B

B

• N transistors

• No static consumption

EE415 VLSI Design

NMOS-only switch

A = 5 V

B

C = 5 V

CL

A = 5 V

C = 5 V

BM2

M1

Mn

Threshold voltage loss causesstatic power consumption

VB does not pull up to 5V, but 5V - VTN

EE415 VLSI Design

Solution 1: Transmission Gate

A B

C

C

A B

C

C

B

CL

C = 0 V

A = 5 V

C = 5 V

EE415 VLSI Design

Resistance of Transmission Gate

(W/L)p=(W/L)n =

1.8/1.2

0.0 1.0 2.0 3.0 4.0 5.0Vout

0.0

10000.0

20000.0

30000.0

R (

Ohm

)

Rn

Req

Rp

EE415 VLSI Design

Pass-Transistor Based Multiplexer

AM2

M1

B

S

S

S F

VDD

GND

VDD

In1

In2

S S

S S

EE415 VLSI Design

Transmission Gate XOR

A

B

F

B

A

B

B

M1

M2

M3/M4