Field Programmable Gate Array (FPGA) Designrmason/elec4706/fpgaDesign.pdf · • Logic Gate –...
Transcript of Field Programmable Gate Array (FPGA) Designrmason/elec4706/fpgaDesign.pdf · • Logic Gate –...
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Field Programmable Gate Array (FPGA)
Design
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Design ProcessDesign ProcessDesign Compilation Simulation VerificaDesign Compilation Simulation Verificationtion
(Graphical or (Compiler) (Timing diagram (Graphical or (Compiler) (Timing diagram (DE2 board)(DE2 board)HDL entry) or anHDL entry) or analysis)alysis)
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Definitions
• Logic Gate – discrete component performing a single logic function (i.e. 7400)
• PLD – a programmable device allowing functionality of several to few tens of devices
• GA – Gate Array, prefabricated, regular layout collections of transistor clusters allowing building complex logic functions through adding top metal layers (half-finished IC)
• FPGA – as above but allowing hundreds to hundreds of thousands devices
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Definitions (cont.)
• Custom (Digital) IC – an IC put together by digital designers gate by gate; standard cells may be used
• ASIC – a digital circuit created fully by silicon compiler (synthesis tool); most of the layout is automated as well; often includes specialized blocks
• Structured ASIC – either standard cell ASIC with macro cells or FPGA with large IP blocks
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Discrete_LOGIC, PLD, FPGA
Performance
PLD
FPGA
Logic Gates
Design Time
Cost
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ASIC, DSP and FPGA
Performance
FPGA
ASIC
DSP
Cost
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ASICs• Standard-cell based design (synthesis)• Physical layout (P&R) and timing closure
(signal integrity) • Flexible die size/shape• High performance at high cost
I/OPads
RAM DSP
Std-Cell
I/OPads
RAM
DSP
Std-Cell
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DSP Processors
• Software programmable • Single-cycle multiply-accumulate
operations• Real-time performance, simulation and
emulation
Source: TI Source: ADI
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FPGAs• Field programmable• Fixed resources (metal-configured logic arrays,
memories, PLLs, I/Os, DSP blocks, test circuitry)• Designed for worse-case
Altera Stratix device architecture
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FPGA I/O Block
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Embedded DSP Blocks
Implementation of a 180-Tap FIR Filter
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Design Flows
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ASIC Design: expense
• Definition, technology selection and planning• RTL generation and synthesis, with verification• Place, route, clock, test and power insertion,
with verification• Rule checking, data preparation, etc.• Sample turn-around and testing
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Device Selection Criteria• Usable gates• Memory structures• High speed interfaces• Performance and flexibility (relative to cell-based
ASIC design)• Availability of specialized IP: CPUs, DSPs, etc. • Total price• Turn-around time• Easy design flow and tools
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New Technologies Changing the ASIC Landscape
• Hardcopy FPGAs– HardCopy devices consist of a common set of base arrays
implemented with the lower-level layers, and the top-level metal layers reserved for the customer’s design.
– Reduce development costs and shorten time-to-market by eliminating ASICs’ long design cycles
• Structured ASICs– Base wafer defines logic cells, embedded functions and I/O– Customer design defines upper metal layers– Vendor provides clock, power, DFT routing
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Altera Hardcopy Technology• HardCopy provides considerable smaller size,
performance and power consumption improvements over the FPGA counterparts
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Altera Stratix GX Architecture