Field-Effect Transistors

1. Understand MOSFET operation.

2. Understand the basic operation of CMOS logic gates.

3. Make use of p-fet and n-fet for logic gate implementation

NMOS AND PMOS TRANSISTORS

The MOS Transistor

n+n+

p-substrate

Field-Oxyde

(SiO2)

p+ stopper

Polysilicon

Gate Oxyde

DrainSource

Gate

Bulk Contact

CROSS-SECTION of NMOS Transistor

Cross-Section of CMOS Technology

MOS transistors Types and Symbols

D

S

G

NMOS Enhancement

G

D

S

PMOS Enhancement

NMOS

Threshold Voltage: Concept

n+n+

p-substrate

DSG

B

VGS

+

-

Depletion

Region

n-channel

PMOS

Mode of Operation

• Cut off

• Liner

• Saturation

Operation in the Cutoff Region

toGSD Vvi for 0

Operation in the Linear Region

2)(2 DSDStoGSD vvvvKi

2

KP

L

WK

toGSDSto VVVV

Operation in the Saturation

toGSDS VVV

2toGSD vvKi

2DSD Kvi

Transistor in Saturation

n+n+

S

G

VGS

D

VDS > VGS - VT

VGS - VT+-

MOSFET Summary

CMOS Inverter

MOS transistors logic input

D

S

G

NMOS Enhancement

G

D

S

PMOS Enhancement

G =‘1’ then turn on the n-fet as Vgs > V threshold

G = ‘0’ then turn on the p-fet as Vgs is negative as Vs > Vg

CMOS NAND Gate

CMOS NOR Gate

The Ideal Gate

Vin

Vout

g=

Ri =

Ro = 0

Delay Definitions

tpHL

tpLH

t

t

Vin

Vout

50%

50%

tr

10%

90%

tf

CMOS INVERTER

The CMOS Inverter: A First Glance

VDD

Vin Vout

CL

CMOS Properties

• Full rail-to-rail swing• Symmetrical VTC• Propagation delay function of load capacitance

and resistance of transistors• No static power dissipation• Direct path current during switching

Voltage TransferCharacteristic

CMOS Inverter VTC

Vout

Vin1 2 3 4 5

12

34

5

NMOS linPMOS off

NMOS satPMOS sat

NMOS offPMOS lin

NMOS satPMOS lin

NMOS linPMOS sat

Simulated VTC

0.0 1.0 2.0 3.0 4.0 5.0Vin (V)

0.0

2.0

4.0

Vo

ut (V

)

Where Does Power Go in CMOS?

• Dynamic Power Consumption

• Short Circuit Currents

• Leakage

Charging and Discharging Capacitors

Short Circuit Path between Supply Rails during Switching

Leaking diodes and transistors

Dynamic Power Dissipation

Energy/transition = CL * Vdd2

Power = Energy/transition * f = CL * Vdd2 * f

Need to reduce CL, Vdd , and f to reduce power.

Vin Vout

CL

Vdd

Not a function of transistor sizes!

CMOS Logic Implementation

A CMOS logic gate consists of

p-tree for pull-up

n-tree for pull-down. P-tree

N-tree

Vdd

Output

Inputs

CMOS Logic Implementation• Dualityf = A+B’C if A = ‘1’ , or B=‘0’ and C=‘1’ , then f = ‘1’if the logic function is in the form as f, then use Direct Implementation, for the P-tree implementation

and logic function series connection so the term B`C is in seriesor logic function parallel connectionso A, B`C is in parallel

use complement of the input signalsThat is, A`, B and C` are used as inputs

CMOS Logic Implementationf = A+B’C A = ‘1’ A`= ‘0’, P1 onB’= ‘1’ B = ‘0’ P2 onC = ‘1’ C`= ‘0’, P3 oneither P1 on or P2 and P3 are on then f = ‘1’

Since ‘0’ is need to turn on the use A`, B and C` as the inputs to the P- tree, instead of the original input variables.

Both p-tree and n-tree have the same set of inputs.

A`

B

C`

P1

P2

P3

CMOS Gate Implementation

Once P-tree is designed, use duality for the N- tree

• DualitySeries connection in P – tree parallel for N- treeParallel connection in P-tree series for N-tree

f = A+B’C if A = ‘1’ , A`=‘0’, B’=‘1, B=‘0’and C=‘1’ , C`=‘0’, then f = ‘1’ pull up the output through the p-tree net

if A = ‘0’ , A`=‘1’, B’=‘0’, B=‘1’and C=‘0’ , C`=‘1’, then f = ‘0’pull down the output through n-tree net

A`

B

C`

f

P1

P2

P3

A`

B C`

N1

N2 N3

CMOS Gate Implementationf = A+B’C A = ‘1’ , A`=‘0’, P1 turn on or B’=‘1, B=‘0’, P2 turn on and C=‘1’ , C`=‘0’, P3 turn on then f = ‘1’ pull up the output through the p-tree net through P1 or P2 and P3

if A = ‘0’ , A`=‘1’, N1 turn onB’=‘0’, B=‘1’, N2 turn on or C=‘0’ , C`=‘1’, N3 turn on then f = ‘0’pull down the output through n-tree netthrough N1 and N2 , or N1 and N3

A`

B

C`

f

P1

P2

P3

A`

B C`

N1

N2 N3

CMOS Gate ImplementationCBAf `

If f is in this form, there are two ways to implement the logic gate forthe logic function. 1. expand the logic function through de Morgan rule and direct implementation on the expanded function.

f = (A+B`C)` = A`(B`C)`= A`(B``+C`) = A`(B+C`)

Implement the logic gate with the previous method, the input signals are A, B` and C

A

B` C

P1

P2 P3

f

CMOS Gate ImplementationCBAf `

Use duality to complete designfor the n-tree

A

B` C

P1

P2 P3

f

A B`

C

N1 N2

N3

CMOS Gate ImplementationCBAf `

gf 2. Take then , g = A+B`C

Use g to define the n-tree configuration. If g is true f = ‘0’ Same implementation rule apply, and logic function series connection so the term B`C is in seriesor logic function parallel connection, andinput variables remain un-change

A = ‘1’, g is true, N1 onB`= ‘1’, and C = ‘1’, g is trueN2 and N3 are on

B`

C

N1 N2

N3

f

CMOS Gate ImplementationCBAf `

Use the dualityto complete design forthe p-tree.

A

B` C

P1

P2 P3

f

A B`

C

N1 N2

N3

Comparison of Design Method

f = (A+B`C)`, f =g`, g = A+B`C

Use g to define the circuit configuration for the N-tree, and the input variables are those of the logic function, g; that is, A, B` and C

By de Morgan rule on f, f = A`(B+C`), and use the expended form to define the circuit configuration for the P-tree, and the inputvariables are the complementary of the variables of the expended form.As f = A`(B+C`), the input variables are A`, B, and C`, the complementary of these signals are A, B` and C.

Comparing the two approach, there is conflict between the two as the input variables are the same as A, B` and C. And the circuit configurationof P-tree and N-tree are in fact observe the de Morgan rule or duality.

CMOS Gate Implementation

P-tree

N-tree

Vdd

Output

Inputs

It has to remind thatthe p-tree has to be connectedto Vdd for pull-up the outputandthe n-tree has to be connected to GND for pull-down theoutput.

It cannot use n-tree for the pull-up and p-tree for the pull-down as the full-swing property will not be maintained. i. e. logic ‘0’ ≠ zero volt logic ‘1’ ≠ Vdd volts