Fibonnaci Sequence Generator and Testbench in VHDL Michael Larson.

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Fibonnaci Sequence Generator and Testbench in VHDL Michael Larson

Transcript of Fibonnaci Sequence Generator and Testbench in VHDL Michael Larson.

Page 1: Fibonnaci Sequence Generator and Testbench in VHDL Michael Larson.

Fibonnaci Sequence Generator and Testbench in VHDL

Michael Larson

Page 2: Fibonnaci Sequence Generator and Testbench in VHDL Michael Larson.

1,1,2,3,5,8,…Each output is the sum of the two previous outputs

Fibonnaci Sequence

A B C outputclk clk

A=B+C

reset: 1 reset: 0

(combinational)

Page 3: Fibonnaci Sequence Generator and Testbench in VHDL Michael Larson.

Fibonnaci Sequence Generator in VHDL

Page 4: Fibonnaci Sequence Generator and Testbench in VHDL Michael Larson.

Testbench in VHDL

Page 5: Fibonnaci Sequence Generator and Testbench in VHDL Michael Larson.

Output

-After the reset the C output is 0-On ever falling clock edge C gets a new value

shifted in-The clock input could be a button input with some

debouncing logic-the output is in hexadecimal (1,1,2,3,5,8,d,15,22…)

Page 6: Fibonnaci Sequence Generator and Testbench in VHDL Michael Larson.

Fibonnaci Generator: from Digital Electronics and Design with VHDL, Pedroni, 2008http://booksite.elsevier.com/9780123742704/casestudies/Samples_of_VHDL_codes_presented_in_the_examples.pdf

General TestbenchVHDL RAM example in EDA playground

Clocking Testbench: blog post by VHDL coding tips and trickshttp://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html

Examples Used


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Secrets of fibonnaci numbers

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