Hierarchical Reinforcement Learning Amir massoud Farahmand [email protected].
FF-1 9/30/2003 UTD Practical Priority Contention Resolution for Slotted Optical Burst Switching...
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9/30/2003 UTD FF-1
Practical Priority Contention Practical Priority Contention Resolution for Slotted Optical Resolution for Slotted Optical
Burst Switching NetworksBurst Switching Networks
Farid FarahmandFarid Farahmand
The University of Texas at DallasThe University of Texas at Dallas
9/30/2003 UTD FF-2
Overview Overview
OBS Overview Major issues in OBS Switch node architecture of the
OBS Hardware prototyping of the
scheduler unit Hardware simulation results
9/30/2003 UTD FF-3
Optical Burst Switching (OBS)Optical Burst Switching (OBS)
Assemble IP packets into data bursts Transmit bursts following their headers by an offset
Separated in space and time Headers are processed electronically Data bursts are passed through the optical switches
OBS CoreSwitch Node
IngressEdge
Router
EgressEdge
Router
OBSEdgeNode
OBSEdgeNode
DCG
CCG
Legacy Interfaces(PoS, GE, IP/ATM)
CCG: Control Chanel GroupDCG: Data Channel Group
DWDM
Link
9/30/2003 UTD FF-4
OBS Switching IssuesOBS Switching Issues
Burst scheduling scheme Channel selection and reservation for the
arriving data burst First-Fit Latest Available Unscheduled (with and without
Void Filling) Contention resolution technique
Resolution of contention between data bursts Buffering Deflection routing Wavelength conversion Burst dropping
9/30/2003 UTD FF-5
OBS Switching IssuesOBS Switching Issues
Burst transmission schemes Slotted: Bursts are transmitted on slot boundaries
Unslotted: Bursts can be transmitted at any time
N-1 0
N-1
2
1
0 Offset time
N
Time
Data Burst Data Channel(DB0)
Link
DB(N-1)
DB2
DB1
S BHP
(b)
2 1
(a)
N-1 2 1 00
N-1
2
1
0 Offset time =
TS(i)
Control Slot = SCC
N
Time TS(i+1)
BHPs
Data Burst Data Channel
Data Slot = SDC
(DB0)
DB1
DB2
DB(N-1) BHPSlot
Link
time slots
TS(+i)
SBHP
1Control Channel Control Channel
BHPSlot
9/30/2003 UTD FF-6
Switch Node ArchitectureSwitch Node Architecture
Optical Signal
DE
/M
UX
MU
X
0...N+Q-1IngressPort 0
0...N+Q-1IngressPort P-1
EgressPort 0
EgressPort P-1
DE
/M
UX
Optical SwitchFabric
0...N+Q-1
0...N+Q-1
0
N-1
0
N-1
N+Q-1
Am
plifier
A
lign
emen
t
Optical Monitor
FDL
FDL
Wavelength Converter
Optical Signal
Optical Signal
Optical Signal
DCG
CCG
MU
X
E/O Electr-Opt Converter
BHP Processor-Regenerator
BHPRegenControl Packet
Processor(CPP)
BHPRegen
O/EO/E
O/EO/E
E/OE/O
E/OE/OScheduler
DEMUX/MUX
and Phase Alignment
Switch Fabric
BHP PROCESSOR
SCHEDULER
9/30/2003 UTD FF-7
Hardware Implementation of the Hardware Implementation of the Control Packet ProcessorControl Packet Processor
Fast processing time Must be fast Minimize software
Scalable with a generic design Can be used for any burst reservation scheme
Low cost Implementable in an off-the-shelf programmable
component (FPGA)
Our main emphases:Practical approach to designing the
Control Packet Processor
9/30/2003 UTD FF-8
Control Packet Processor ArchitectureControl Packet Processor Architecture
Architectures Centralized Distributed
Centralized architecture Similar to input queuing Single scheduler
ReceiverBlock
(0)
ReceiverBlock(P-1)
To theSwitchFabric
BHP
BHP
PriorityQueue
(0)
PriorityQueue(P-1)
SwitchControl(P-1)
SwitchControl
(0)
Scheduler
(a)
9/30/2003 UTD FF-9
Control Packet Processor ArchitectureControl Packet Processor Architecture
Distributed architecture Similar to virtual output queuing Parallel scheduling
One per destination
Advantages Minimizing head-of-queue blocking Higher reliability Allowing concurrent scheduling
Disadvantage High memory requirement
Each Destination Queue must be sized for the worst case
To theSwitchFabric
ReceiverBlock
(0)
BHP
ReceiverBlock(P-1)
BHP
SwitchControl
(0)
Scheduler(0)
SwitchControl(P-1)
Scheduler(P-1)
Des. Q (0)
Des. Q(P-1)
Des. Q (0)
Des. Q(P-1)
9/30/2003 UTD FF-10
Scheduling Mechanisms in the Scheduler BlockScheduling Mechanisms in the Scheduler Block
Scheduling mechanism Latest Available Unscheduled
Contention resolution technique Latest Drop Policy (LDP)
With offset-time-based QoS Shortest Drop Policy (SDP)
Supports unlimited service differentiation Performs better than the Latest Drop
Policy
9/30/2003 UTD FF-11
1.00E -05
1.00E -04
1.00E -03
1.00E -02
1.00E -01
1.00E +00
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Utilization (G)B
LR LDPSDP
SEG
(a)
Comparing SDP and LDP Performance Comparing SDP and LDP Performance
Single switch with 4 edge nodes
Each port has 4 channels
Full utilization of wavelength converters
Max data burst duration is 20 slots / Exponentially distributed
3 levels of service differentiation
Performance metric: Burst Loss Rate (BLR)
1.00E -06
1.00E -05
1.00E -04
1.00E -03
1.00E -02
1.00E -01
1.00E +00
0.05 0.25 0.45 0.65 0.85
Utilization(G)
Unslotted/VarSlotted/VarSlotted/Fix
(b)
9/30/2003 UTD FF-12
Hardware Prototyping of the Hardware Prototyping of the Control Packet ProcessorControl Packet Processor
To theSwitchFabric
ReceiverBlock
(0)
BHP
ReceiverBlock(P-1)
BHP
SwitchControl
(0)
Scheduler(0)
SwitchControl(P-1)
Scheduler(P-1)
Des. Q (0)
Des. Q(P-1)
Des. Q (0)
Des. Q(P-1)
Basic assumptions Slotted transmission of BHPs Shortest Drop Policy (SDP) Parallel scheduling
Receiver Block All BHP are verified for correct
parity and framing Each request is reformatted, time
stamped, and passed on to the proper Destination queue
Destination Queues Scheduler
BHP Processor-Regenerator
BHPRegenControl Packet
Processor(CPP)
BHPRegen
O/EO/E
O/EO/E
E/OE/O
E/OE/OScheduler
9/30/2003 UTD FF-13
Hardware Prototyping of the SchedulerHardware Prototyping of the Scheduler
Arbiter
Scheduler Core Section
Processor Channel Manager Update Switch
Setup
Statistics Accumulator
To theSwitchFabric
ReceiverBlock
(0)
BHP
ReceiverBlock(P-1)
BHP
SwitchControl
(0)
Scheduler(0)
SwitchControl(P-1)
Scheduler(P-1)
Des. Q (0)
Des. Q(P-1)
Des. Q (0)
Des. Q(P-1)
To theSwitch
Control block
ChanQueue 2
ChanQueue 0
ChanQueue 1
ChanQueue N-1
Channel Manager
Search
Eng
ine
UpdateS
wS
etup
Statistics Accumulator
Arbiter
Requests fromDest Queues
0
1
2
P-1
RequestProcessor
To the BHPregenerator
Scheduler Core SectionCS_CNT
From the Receiver
9/30/2003 UTD FF-14
Hardware Prototyping of the SchedulerHardware Prototyping of the Scheduler
To theSwitch
Control block
ChanQueue 2
ChanQueue 0
ChanQueue 1
ChanQueue N-1
Channel Manager
Se
arch
En
gin
e
UpdateS
wS
etup
Statistics Accumulator
Arbiter
Requests fromDest Queues
0
1
2
P-1
RequestProcessor
To the BHPregenerator
Scheduler Core SectionCS_CNT
From the Receiver
P inputs along with the counter signal
Flow Control; QoS control
Checks Start and End times; Reserve
Requests
One per channel
If reservation was successful regenerate
BHP
9/30/2003 UTD FF-15
Illustration of the Scheduler OperationIllustration of the Scheduler Operation
Three Channels Assuming all Channel
Queues are empty initially
1213141516171819202122 CS_CNT
Chan 0
Chan 1
Chan 2B3
B1
B2B4
B5
Time
HoQ
CQ0 CQ1 CQ2
B1Time = i B2Time = i+1
B3
B4B5Time = i+6
Time = i+7
9/30/2003 UTD FF-16
Scheduler PrototypeScheduler Prototype
Implemented on Altera EP20k400E FPGA 2.5 million gates Maximum clock rate of 840 MHZ
Core section modeled by Celoxica DK design suite Initially modeled using C-language Modified into Handel-C language Compiled and translated into a gate level VHDL code
Other blocks were designed using VHDL code Tested, verified, and synthesized
Cadance (NcSim) Quartus II
9/30/2003 UTD FF-17
Hardware Simulation ResultsHardware Simulation Results
0
5
10
15
20
25
30
35
40
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
Reservations in the Channel Queue
Max. Ch=31Max. Ch=15
Max. Ch=7
Number of clock cycles required to processes packets Number of clock cycles required to processes packets in the Destination Queuein the Destination Queue
9/30/2003 UTD FF-18
Hardware Simulation ResultsHardware Simulation Results
0.00E+00
2.00E+07
4.00E+07
6.00E+07
8.00E+07
1.00E+08
1.20E+08
1.40E+08
1.60E+08
1.80E+08
7 15 31 63
Number of Channels
P=4 P=8P=16 P=64
Number of NAND gates requires to design the scheduler unitNumber of NAND gates requires to design the scheduler unit
9/30/2003 UTD FF-19
So in Conclusion……So in Conclusion……
A key issue in implementing the OBS is designing a fast and efficient BHP processor
We presented alternative architectures for the BHP packet processor
We discussed several scheduling algorithms and their performance
We presented hardware results in terms of the cost and scalability
9/30/2003 UTD FF-20
So in Conclusion……So in Conclusion……
Interested?
Looking for something to do?
or just Curious?
9/30/2003 UTD FF-21
End of Slides!End of Slides!
9/30/2003 UTD FF-22
Practical Priority Contention Practical Priority Contention Resolution for Slotted Optical Resolution for Slotted Optical
Burst Switching NetworksBurst Switching Networks
Farid Farahmand, Vinod M. Vokkarane, Jason P. JueFarid Farahmand, Vinod M. Vokkarane, Jason P. Jue
The University of Texas at DallasThe University of Texas at Dallas
9/30/2003 UTD FF-23
Control Packet Processor ArchitectureControl Packet Processor Architecture
Architectures Centralized Distributed
Centralized architecture Similar to input queuing All BHP are verified for correct
parity and framing Single scheduler Each request is time stamped
ReceiverBlock
(0)
ReceiverBlock(P-1)
To theSwitchFabric
BHP
BHP
PriorityQueue
(0)
PriorityQueue(P-1)
SwitchControl(P-1)
SwitchControl
(0)
Scheduler
(a)
QoS(1 bits)
Dest(2 bits)
Ing DCG(2 bits)
Ing DC(4 bits)
Length(4 bits)
Offset(5 bits)
Parity(8 bits)
Header(8 bits)
QoS(1 bits)
Ing DCG(2 bits)
Ing DC(4 bits)
Length(4 bits)
Offset(5 bits)
T(8 bits)
RX BLOCK
9/30/2003 UTD FF-24
OBS Switching IssuesOBS Switching Issues
Burst transmission schemes Slotted: Bursts are transmitted on slot
boundaries Unslotted: Bursts can be transmitted at any
time Simpler to implement ?????Higher loss (due to unpredictable burst
characterization)
N-1 0
N-1
2
1
0 Offset time
N
Time
Data Burst Data Channel(DB0)
Link
DB(N-1)
DB2
DB1
S BHP
(b)
2 1
(a)
N-1 2 1 00
N-1
2
1
0 Offset time =
TS(i)
Control Slot = SCC
N
Time TS(i+1)
BHPs
Data Burst Data Channel
Data Slot = SDC
(DB0)
DB1
DB2
DB(N-1) BHPSlot
Link
time slots
TS(+i)
SBHP
1Control Channel Control Channel
BHPSlot
9/30/2003 UTD FF-25
So in Conclusion……So in Conclusion……
A key issue in implementing the OBS is designing a fast and efficient BHP processor
We presented alternative architectures for the BHP packet processor
We discussed several scheduling algorithms and their performance
We presented hardware results in terms of the cost and scalability