FPGA High Speed IO Trends and FPGA High Speed IO Trends and Signal Integrity ChallengesSignal Integrity ChallengesJohn WeiMember of Technical StaffHigh Speed Technology Specialist

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Agenda High Speed IO Trends Signal Integrity Terms Signal Integrity Terms Signal Integrity Challenge Minimize Jitter GenerationMinimize Jitter Generation Improve Jitter Tolerance Transceiver Equalizationq On-Die Instrument

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High Speed IO TrendsHigh Speed IO TrendsHigh Speed IO TrendsHigh Speed IO Trends

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HSIO Link Architecture Advancement PathHSIO Link Architecture Advancement Path

1 GbpsA h i d

Tx RxCoded data

te

Asynchronized

~0.1 Gbpsglobal clock

Tx RxStrobe

~0.8 Gbpssource synchronized

Gigabit EthernetCEI/OIFPCI Express40G/100G Ethernet

Dat

a ra

t

Tx RxData

Tx RxData

40G/100G Ethernet

Time

Clock

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Time

Traditional Parallel Bus

PCI, PCI-X, Telecombus, SPI-3, XGMII… Single-ended busSingle ended bus Low speed, usually less than 150Mbps/pin High pin count

Short distance Short distance Simultaneous Switching Noise (SSN)

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High-Speed Source-Synchronous

SFI-4, SPI-4, RapidIO (Parallel)… Parallel LVDS bus Data rate up to 1.6Gbps Source-Synchronous clock required to sample data

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High-Speed Source-Synchronous

Skew is an issue Bit Period Is Short, 0.6 ns at 1.6 Gbps

Sk I L P t f th P i d Skew Is Large Percentage of the Period Skew Makes It Difficult to Sample in Middle of Bit Period

Sources of SkewTrace Length Variations Trace Length Variations

Capacitive & Inductive Loading Transmitter Channel-to-Channel Skew

Clk’

D0’D0

D1’

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Sample Too Close to Edge

High-Speed SSIO Consideration

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Serialization

Transceiver introducedS i li Serializer

Clock and Data Recovery Deserializer

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Transceiver FunctionalityHigh-Speed Data Slower-Speed DataHigh-Speed Data

b2

b3

SERDES

CDRCDRb0

b1

b3

High-SpeedClock

Slower-Speed DataT itt SERDES

/Receiver

Slower-Speed Clock

High-Speed Data

Slower-Speed Data

b0

b1

Transmitter SERDES

b2

b3

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PLL

Serialization

Serialization solves most of parallel bus problemsproblems CDR based

Skew is not a problem any more Skew is not a problem any more

Faster data rate, shorter bit rate Simple Timing Calculation Not Sufficient to Determine System

R li bilitReliabilityMust Examine Uncertainty in Digital Data Communications

Signal Integrity is the keyg g y y

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Signal Integrity TermsSignal Integrity TermsSignal Integrity TermsSignal Integrity Terms

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Key Measurement Components for Serial I/O Signal IntegritySignal Integrity

Bit error rate performance (BER)p ( ) Measures number of errors over the total number of bits transferred from

transmitter (Tx) to receiver (Rx)

Eye diagram Eye diagram Shows the data valid window with timing and voltage margins

Jitter Reduces data valid window Increases with more transceiver, FPGA core and regular I/O switching

Good Signal Integrity is the Key to Reliable High Speed Sol tions

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High-Speed Solutions

What’s an Eye Diagram

Waveform Represents a Logical ‘1’

Waveform Represents a Logical ‘0’Waveform Represents a Logical 0

Ideal Eye Diagram with No Noise

Eye Diagram with Voltage Noise

Eye Diagram with Timing Noise

Eye Diagram with Voltage & Timing Noise

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Data-valid window

Definitions of Jitter

Time Difference Between When a Pre-Defined Event Should Occur &When a Pre Defined Event Should Occur & When It Actually Occurs

Event Could Be: Clock Rising & Falling Edges

O ti S li I t t f Si l Optimum Sampling Instant of Signal Differential Zero Crossing of Electrical Signal Threshold Power Crossing of Optical Receiver

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Jitter Pictorial Representation

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Jitter Generation

Used to define a transmitter

The amount of period variation (jitter) (j )due to the driver

Total jitter (TJ) consists of a bounded portion (DJ) and an unboundedportion (DJ) and an unbounded portion (RJ)

TJ = DJ + RJ

is a function of bit error rate (BER)

BER defined by spec i.e. BER of 1E-12 = 1E12 bits without an

error = +/-7 = 14 TJ = DJ + 14*RJ +/- 3 = 99% error-free = 1E-2 BER

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TJ DJ + 14 RJ+/- 7 = 1e-12 BER

Jitter Tolerance

Used to define a CDR Definition: Amount of jitter the receiver can handle withoutDefinition: Amount of jitter the receiver can handle without

registering a bit error Specification defines the frequency range of jitter

Altera Stratix® II GX jitter tolerance over jPVT @ 6.25 Gbps

Jitter Tolerance Mask

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S-Parameters

Used to define a channelSingle ended

S11S12S21S22Single ended

Energy in vs. energy out S11, S21, S12, S22

Port 1 Port 2

Differential 4 parameters for each conversion Differential differential (SDD) Port 1 Port 4 Differential differential (SDD) Differential common mode (SDC) Common mode differential (SCD) Common mode common mode (SCC)

Port 2Port 3

Diff Port 1 Diff Port 2Co o ode co o ode (SCC)

SDD21 = Differential insertion loss

Diff Port 1 Diff Port 2

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S-Parameters

As Data Rate (Frequency) Increase, we see higher insertion loss (attenuation )

SDD21 Curve for XAUISDD21 Curve for XAUI Backplane vs. Frequency

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Signal Integrity ChallengeSignal Integrity ChallengeSignal Integrity ChallengeSignal Integrity Challenge

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Serial Protocols Get Faster

10 OC192 10GE CEI-10G

FC16

og s

cale

XAUICEI-6G

FC4

3.072GPCIe 1.0

PCIe 2.0

PCIe 3.0Interlaken 6G

FC8

SATA 2.0SRIO 2 5SRIO 3.125

In 2002, serial protocols entered mainstreamte

(Gbp

s) in

l

1

OC48

FC1GigE

3G SDIFC21.2288G2.4576G

3.072G

OBSAI 768M

1.536G GPON

SATA 1.0SRIO 1.25

SRIO 2.5

mainstream

Dat

a ra

t

OC12

HD-SDI

SDI

CPRI 614MOBSAI 768M

1985 1990 1995 2000 2005 20100.1

OC3

P t l t d d l ti d t

SDI

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Protocol standard completion date

Move to 28 Gbps

For the highest data rate and bandwidth applications

100 Gigabit Ethernet Optical interface is moving to 4x25G and 4X28G Size and cost reduced optical module Power efficiency (per Gbps)

200mW / channelStandards: 100 GbE, OTU-4

Electrical specs: CEI 28G100G CFP Optical Module

Electrical specs: CEI-28G

10 @ 11.3 Gbps 4 @ 28 Gbps

28 Gbps Enables Greater System Integration and Lower System Cost© 2010 Altera Corporation—Public

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28 Gbps Enables Greater System Integration and Lower System Cost

Signal Integrity Challenge Electrical signal from point A needs to be delivered to point B Point A: TX - transmitter, we refer to signal @ near-endg @ Point B: RX - receiver, we refer to signal @ far-end: either inside device (RX output) or right before RX pins

Vi I t t Li k (IO d b k l IO d) Via Interconnect: Link (IO card+back-plane+IO card)

receive device

A Bnear-end eye

far-end eyeTX RX

RX outputtransmit device

I/O card

backplane

connector

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p

Why the Challenge? Inside interconnect:

Incident Attenuation + Reflection + Radiation + Coupling Transmitted

A B

TX RXTX RX

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Degradation is Proportional to Data Rate

-5 dB is 56%-10 dB is 32%

0 dB is 100%

Collection of customer backplanetransfer functions

10 dB is 32%

3.125 Gbps-40 dB is 1%

6.25 Gbps

8.5 Gbps

10 Gbps-60 dB is 0.1%

p

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Examples: 800mV FR4 6.375 Gbps

2-inch trace 10-inch trace 52-inch trace

NC

K PA

TTER

N

CLO

CBS

PRB

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Minimize Jitter GenerationMinimize Jitter GenerationMinimize Jitter GenerationMinimize Jitter Generation

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Power Supply Optimization

Precision and dedicated voltage supplies are provided for timing-critical PLL components

VccLVccT VccH

critical PLL components Voltage noise to timing jitter

conversion is minimized < -55 dB reduction in power supply

TX

Clock pathTx VccH

Tx pathserializer

GndGndGndGnd

rejection ratio (PSRR) Separated and isolated power

supply No power supply coupling

Clock pathPLLs

Band gapVCOs

Linearregulator

GndGnd

No power supply coupling Prevent uncorrelated noise pick-up

On-package decoupling (OPDs) sed appropriatel

VCOsCharge pumps

Protected analog

Gnd

used appropriately To keep the transceiver immune from the

external power supply noise PLL

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Ring Oscillator (RO)

Most widely used oscillator architecture for CMOS ICs

Wide frequency tuning range: from 10-100 MHz to 1-10 GHzy g g

Because of the high gain: Sensitive to power supply and substrate noises Requires a high power supply rejections ratio q g p pp y j Offers good substrate isolation

A 3-GHz CMOS VCRO (65 nm) achieves: A phase noise of -91 dBc/Hz at 1 MHzA phase noise of 91 dBc/Hz at 1 MHz An RMS jitter (1-80 MHz) at 1.1 ps

A 6-GHz VCRO in the same process achieves:A phase noise of -86 dBc/Hz at 1 MHz A phase noise of -86 dBc/Hz at 1 MHz

An RMS jitter (1-80 MHz) at 1.24 ps

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LC Oscillator (LCO)

Existed in RF applications for a long time, only recently becoming more common in mixed-signal IC design

One reason: with shrinking technology inductors are becoming small enough to be One reason: with shrinking technology, inductors are becoming small enough to be integrated on the die (still bigger than a ring oscillator, however)

Superior phase noise performance because of its highly selective and high-quality LC tankhigh quality LC tank

Limited frequency-tuning range: typically ~ 20%

A 6-GHz LC in the same process has a phase noise of -110 dBc/Hz at 1 MHz and an RMS jitter (1-80 MHz) of only 100 fs

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Programmable LC PLL

LC PLL frequency tuning range extension

PFD CP / LF

LCVCO0

/LDiff Ref -Clock Input

Outputdiv/2

LCVCO1 div/2

/M

Data Rate(Gbps)12.53.250.6

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Jitter and Eye Performance for RO and LC

LC at 6.5 Gbps RO at 6.5 Gbps

RJ =605 fs RJ =1.228 ps© 2010 Altera Corporation—Public

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RJ 605 fs RJ 1.228 ps

Improve Jitter ToleranceImprove Jitter ToleranceImprove Jitter Tolerance Improve Jitter Tolerance

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Hybrid Clock and Data Recovery (CDR)

CDR has lock-to-clock and lock-to-data modes CDR has lock to clock and lock to data modes CDR is first locked to the reference clock, then switched to lock the data, providing fast

locking time No unlocked or out-of-lock problems when the received data has excessive jitter Reference clock jitter does not affect CDR jitter performance© 2010 Altera Corporation—Public

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Reference clock jitter does not affect CDR jitter performance

Phase Interpolator CDR

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Jitter Tolerance Comparison<-40 dB/decade

tude

Mag

nit

PLL/hybrid CR-20 dB/decade

PI CR

Receivers have a hybrid phase-locked loop (PLL)-based CDR technology that has the best jitter generation and jitter tolerance performance

FrequencyfPLLfPl

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has the best jitter generation and jitter tolerance performance

Transceiver EqualizationTransceiver EqualizationTransceiver EqualizationTransceiver Equalization

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Electrical Channel Characteristics0 dB

-20 dB

$$

20 dB

-40 dB

$

$$-60 dB

80 dB 0 GHz 5 GHz 10 GHz 15 GHz-80 dB

Tx/Rx Tx/Rx

Channel

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Physics for Electrical Channel LossElectrical loss function

00 2 4 6 8 10 12

15

-10

-5

0

Skin

30

-25

-20

-15

Loss

(dB

)

Dielectric

-40

-35

-30

Skin + dielectric

-50

-45

Frequency (GHz)

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Mechanisms for Equalization

0dB 0dB 0dB

f f f

0dB 0dB 0dB

Channel Equalizer =+ Flat overall response

Tx equalizer: Rx equalizer:

M k th l h l l h l

pre-emphasis, de-emphasis

linear (CTLE or FFE) or adaptive (DFE)

Make the lossy channel a non-lossy channel so the overall “effective channel” is an “all-pass” function or has a flat response

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Tx Pre-emphasisChannel/medium

Tx RxEQ

Work up to 28Gbps in 28-nm CMOS process node Simple easy to implement relatively less power Simple, easy to implement, relatively less power Good control and testing Not suitable for fine-tuning adaptive/dynamic equalization

C lif th i© 2010 Altera Corporation—Public

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Can amplify the noise

Pre-emphasis Opens Eye on 40” PCB @ 6 Gbps

3” PCB trace (FR-4 material)

40” PCB trace (FR-4 material)

Increasing pre-emphasis levels

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Equivalent to driving a backplane @ 6g

6.25-Gbps Signal Degrades Over 40” of PCB

Short trace (5”)no pre emphasis

3 ones, 5 zeroes 1 3 4

no pre-emphasis

2

Short trace (5”)1

4Long trace (40”)no pre-emphasisNot DC balanced 2

34

Long trace (40”)© 2010 Altera Corporation—Public

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44

g ( )

6.25-Gbps Signal Improves With Pre-emphasis

3 ones, 5 zeroes 1 3 4

Short trace (5”)with pre emphasis

2with pre-emphasis

Short trace (5”)13

2

3 4Long trace (40”)with pre-emphasisDC balanced

Long trace (40”)© 2010 Altera Corporation—Public

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45

g ( )

Rx Equalization

TxData

l

Channel/medium

Eq.

Rx

Tx sample

Well suited for fine-tuning adaptive/dynamic equalizationFinite impulse response (FIR) infinite impulse response (IIR) and Finite impulse response (FIR), infinite impulse response (IIR), and analog filters (such as FFE, DFE, and CTLE) are possible

Lack of observability and relatively higher power consumption

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Continuous Time Linear Equalizer (CTLE)

Continuous time, non-sampled Easy to implement, low power consumptiony p p p Many equalizer stages can be added to increase the order and

the maximum boost in a given frequency interval

Parasiticpole

Equalizerpole

Gai

n

E li

Frequency

Equalizerzero

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Four-Tap Linear Equalizer (CTLE)

30

32

16

18

20

22

24

26

28

30

DC gain dj t t

High-frequency gain adjustment

4

6

8

10

12

14

16

dB(S

(2,1

))adjustment

[0dB-12dB]

g j

[0dB-20dB]

1E8 1E91E7 6E9

-6

-4

-2

0

2

-8

freq HzSlope adjustmentfreq, HzSlope adjustment [20dB-80dB]

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Equalizer Transfer Function

combined frequency response

Medium

Highcombined frequency response

Low

Bypass EQ

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Equalization Simulation Example Optimize equalizer settings Simulate channel with transceiver

Channel ModelReceive Eye, No EqualizerChannel Model q

Receive Eye With Equalizer

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CTLE Bandwidth

Gain

Programmable bandwidth CTLE to support 12.5G backplane

0 db

p 20dB high-frequency gain

0 db

Freqq

6.25 GHz(12.5 Gbps)

3.25 GHz(6.5 Gbps)

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Adaptive Equalization Example

RL1 RL2

M1 M2INP INN

OUTN OUTP

VEQ[1:4]

VVARM3 M4

RS

CV1 CV2

VEQ2

RXin

HPF

RGEN CTRL

RGENEQ_OUT RGEN_OUT

LPF HPF LPFLPF[1:0]HPF[1:0]

RRGEN_BW[1:0]

EQstage

1

EQstage

2

EQstage

3

EQstage

4

VEQ1 VEQ4VEQ3

VVAR

VRGEN

Plug-and-play solution

Ad ti ( l d l )Rect Rect Rect Rect

G _C

UP_DNN_LF

UP_DNN_HF

D2AsState Machine

Controls

D2As

ADCE(adaptive dispersion compensation engine)

Adaptive (plug and play)changes over time,enabling link monitoring

AdaptiveEngine

CLK

ate

Mac

hine

cont

rols

D2A

con

trols

LF_O

FFS

ET[

2:0]

HF_

OFF

SET[

2:0]

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StaD

Flexible PLD interface enables link monitoring usage

5-Tap Decision Feedback Equalizer_From Linear

EqualizerTo CDR

Z-1

Z-1

C1

Z 1

Z-1

C2

C3

Work up to 12.5Gbps Improves signal-to-noise ratio (SNR)

Z-1

Z-1

C4

p g ( ) With CTLE, addresses

pre-cursor and post-cursor ISI Mitigates the effects of crosstalk

C5

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Automatically adapts to PVT conditions

On-Die InstrumentOn-Die InstrumentOn Die InstrumentOn Die Instrument

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Why On-Die Instrument?

On-Die Instrument can test/verify critical IC blocks within the Rx that are not possible from anwithin the Rx that are not possible from an external instrument CTLE gain and DFE coefficients Data and clock signal properties/jitter before the

sampler System debuggingSystem debugging

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On-Die Instrument

View receiver signal margin up to 12.5 Gbps Complete vertical and horizontal reconstruction of eye opening Uninterrupted datapath for live debug capability

EyeQ

Lossy Medium

Pre-Emphasis EQ CDR

Minimize Board Bring Up / Debug Time With D i R fi ti d E Q

Tx Rx

Lossy Medium

© 2010 Altera Corporation—Public

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.56

Dynamic Reconfiguration and EyeQ

On-Die Instrument CircuitOn-Die Instrument CircuitEQ: Equalizer

S l A

RX

Q qPD: Phase DetectorCP: Charge PumpVCO: Voltage Controlled OscillatorPI: Phase Interpolator

RXInput EQ PD

Sampler A

CDR

Multi -

plexer

o

1

DeserializerRecovered Data

OUT

64 ertical threshold le els

CP VCO

CDR

EYE

64 vertical threshold levels 32 horizontal phase-

interpolator steps 3ps / steps (@ 10 Gbps)

PILogicMulti -plexer

o

1

Recovered Clock

VREF_G

User-selectable threshold / PI setting

Sampler B

EN

BIT Checker

BitErr

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New in SV

Altera’s 28 nm Transceivers are Working!

Die Layoute ayou

12.5 Gbps

Eye Diagram

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Summary

Advanced oscillator and hybrid CDR enables 28Gbps at the 28-nm CMOS process node in FPGAs

Comprehensive equalizations for 12.5Gbps backplane

On-Die instrument for system debugy g

© 2010 Altera Corporation—Public

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.59