Fault Simulation

Fault Simulation TechniquesFault Simulation Techniquesy Basicsy Faultsimulationalgorithms

Serial Parallel Deductive Concurrent Differential

y RandomFaultSampling

Wh t i f lt i l ti ?What is fault simulation?

Faulty outputsF lt Ci i FaultyoutputsUndetectedfaultsFaultcoverage

Fault Simulator

CircuitTestpatternsFaultmodel

Time Complexity

Proportional to Proportional to n: Circuit size, number of logic gates p: Number of test patterns f : Number of modeled faults

Complexity=P*F*G~O(G3)withsinglesafaults Complexityishigherthanlogicsimulation,O(G2),butismuchlower

hthantestpatterngeneration. Inreality,thecomplexityismuchlowerduetofaultdroppingand

advancedtechniques.

DefinitionsDefinitionsy FaultSpecification Definingasetofmodeledfaultsand

performing fault collapsingperformingfaultcollapsingy FaultDropping The removal of detected, hyperactive and

hypertrophic faults during the run (Inverseoffault insertion)faultinsertion)

y FaultInsertion Selectingasubsetoffaultstobesimulatedandcreatinganetlistwiththesefaults

PropagationoffaulteffectsAfaultcanbetermeddetectediff:y Itisactivatedbythetestvectory Itsfaultyvalueistransferredfromtheeffectednet(internal)ontothe

primaryoutputpinsp y p p

F lt D i gFault Droppingy Numberoffaultsrequiringsimulationdecreasesastherunproceeds

because the main goal is to determine the fault coverage of a givenbecausethemaingoalistodeterminethefaultcoverageofagiventestpattern

y Detectedfaultscanbeimmediatelyremoved,drasticallyreducingtheaverage list length and thus the computing loadaveragelistlengthandthusthecomputingload

y Some faults must be removed in any case for the sake of efficiency. These belong to two main classes: hyperactive and hypertrophic faults

H t hi f lt h k i i k l y Hypertrophic fault causes the network to remain in an unknown status on almost all the nodes

e.g., a fault on a reset line

It t b d t t d d t CPU ti d It cannot be detected, and wastes CPU time and memory.

y Hyperactive fault produces very high activity, e.g., a group of elements starts to oscillate. It, too, is undetectable and very CPU-time consuming

Referred from S.Gai, P.L.Montessoro, Fabio Somenzi, MOZART, a Concurrent Multilevel Simulator, IEEE Transactions on Computer-Aided Design, vol. 7, no. 9, September 1988, pp. 1005-1016

Fault InjectionFault Injection

Fault Simulator FlowFault Simulator Flow

Logic simulation on both d (f lt f ) d good (fault-free) and faulty circuits

Need for Fault SimulationNeedforFaultSimulationy Toevaluatethequalityoftestset;intermsoffaultcoveragey ToincorporateintoATPGfortestgenerationy Toconstructfaultdictionary

Serial Fault SimulationSerial Fault Simulationy First,performfaultfreelogicsimulationontheoriginalcircuit G d (f lt f ) Good(faultfree)response

y Foreachfault,performfaultinjectionandsimulatetheerrornetlist Faultycircuitresponse

Test vectors Fault-free circuit Comparator f1 detected?

Circuit with fault f1

Circuit with fault f2

Comparator f2 detected?

Circuit with fault fn

Comparator fn detected?

Circuit with fault fn

Each one of these computations are done one by one sequentially

ExampleExample

Parallel Fault SimulationParallel Fault Simulation

y Good and faulty ckts say W are simulated togethery Goodandfaultyckts,say W aresimulatedtogethery AsetofFfaultsrequire[F/W]passes

l d d h d b h ( )y Compiledcodemethod;bestwithtwostates(0,1)y Exploitsinherentbitparallelismoflogicoperationsoncomputer

wordsS d li f i l iy Storage:onewordperlinefortwostatesimulation

y Multipasssimulation:Eachpasssimulatesw1 newfaults,wherew isthemachinewordlengthS d i l h d 1y Speedupoverserialmethod~w1

y NotsuitableforcircuitswithtimingcriticalandnonBooleanlogic

Parallel Fault Sim ExampleParallel Fault Sim. Example

Bit 0: fault-free circuit

Bit 1: circuit with c s-a-0

Bit 2 i it ith f 1

1 1 1

c s-a-0 detected

Bit 2: circuit with f s-a-1

a

b c

e

1 1 1 1 0 1

1 0 1

1 0 1s-a-0

d f

g 0 0 0

s-a-1

s a 0

0 0 1d f s-a-1 0 0 1

Deductive Fault SimulationDeductive Fault Simulationy Onepasssimulationy Each line k contains a list L of faults detectable on ky Eachlinek containsalistLk offaultsdetectableonky POfaultlistsprovidedetectiondata

Some Simple GatesSome Simple Gates

Gate Input output o/p fault listGate Input output o/pfaultlist

a b Z

AND 0 0 0 {La Lb }UZ10 1 0 {La Lb' }UZ11 0 0 { L ' L } U Z1 0 0 {La Lb }UZ11 1 1 {La ULb } Z0

OR 0 0 1 {LaULb } Z10 1 1 {La' Lb }UZ01 0 1 { L L ' } U Z1 0 1 {La Lb' }UZ01 1 0 {La Lb }UZ0

Deductive Fault Sim. Examplep

Notation Lk is fault list for line k

1 { } L = L U L U {e0}

kkn is s-a-n fault on line k

a

b e

1

1 11

{a0}

{b0 , c0}

Le La U Lc U {e0}

= {a0 , b0 , c0 , e0}

c

d f

g

0

1{b0}

{b0 , d0} {b0 , d0 , f1}

Faults detected by

Lg = (Le Lf ) U {g0}= {a0 , c0 , e0 , g0}

Faults detected bythe input vector

Concurrent Fault SimulationConcurrent Fault Simulationy Eventdrivensimulationoffaultfreecircuitandonlythosepartsofthe

faulty circuit that differ in signal states from the faultfree circuit.faultycircuitthatdifferinsignalstatesfromthefault freecircuit.y Alistpergatecontainingcopiesofthegatefromallfaultycircuitsin

whichthisgatediffers.ListelementcontainsfaultID,gateinputandoutputvaluesandinternalstates,ifany.

y Alleventsoffaultfreeandallfaultycircuitsareimplicitlysimulated.y Faultscanbesimulatedinanymodelingstyleordetailsupportedin

truevaluesimulation(offersmostflexibility.)y Fasterthanothermethods,butusesmostmemory.

Some Basic DefinitionsSome Basic Definitionsy Goodevent Events that happen in good circuit Eventsthathappeningoodcircuit Affectbothgoodgatesandbadgates

y Badevent Eventsthatoccurinthefaultycircuitofcorrespondingfault Affectonlybadgates

y Diverge Additionofnewbadgatesg

y Converge Removal of bad gates whose I/O signals are the same as corresponding RemovalofbadgateswhoseI/Osignalsarethesameascorrespondinggoodgates

Conc Fault Sim ExampleConc. Fault Sim. Example

0 1 1 1a0 b0 c0 e0

a 1

11

0

10

1

00

1

00

1

10

b c

e

g

1

0

111

1

01

d f 1 0

0

00

0

11

0

00

0

00

a0 b0 c0 e0

1

00

1

11

1

11

0 1 0 1 1 1

b0 d0d0 g0 f1

f10 1 0 1 1 1 0

f1