Fast Timing Workshop Krakow, Nov 29 - Dec 1 st 2010 Part 2a.

Fast Timing WorkshopKrakow, Nov 29 - Dec 1st 2010

Part 2a

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Gary Varner

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Gary Varner

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ANITA

• RF Transient (impulsive) Events (200‐1200 MHz) (200 1200 MHz) • 324 chan. @ 2.6GSa/s • Completely solar powered Completely solar powered (tight demands on power, few hundred W total) • Need full waveforms

Gary Varner

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Gary Varner

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Gary Varner Design Choices

• Input coupling – Differential versus single-ended input – Needed analog bandwidth – Gain needed?

• Sampling Options – On‐chip PLL/DLL – External DLL – Analog transfer vs interrogate in situ

• ADC and readout options • ADC and readout options – Sequential output select vs random access – On‐chip vs. off‐chip ADC – Serial, parallel, massively parallel

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Gary Varner Constraints

- Analog Bandwidth - Switching noise- Leakage current- Deeper sampling

Extensive radio array for UHE neutrinos- Super B Factory

PID Upgrade – precision timing

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Gary Varner

Design Choices

- Input coupling: diff-s ended, ABW, Gain ?- Sampling options: On-chip PLL/DLL, analog transfer decision

ADC and readout options: On/off-chip, serial/parallel

ABW: C sampling is killing (typ (50 fF x 4k=50pF=10 ns)kT/C noise: 78 fF = 12 bitsLeakage current: Increase C or reduce conversion time: fA → nANDR: even worse in Deep Sub-Micron

Sampling depth: application dependent

ANITA-I

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Gary VarnerANITA

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Gary Varner

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Gary Varner

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Gary Varner

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Gary Varner

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Gary Varner

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Gary Varner

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Gary Varner IRS/Blab3 chips

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Gary Varner

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Gary Varner Blab 1

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Gary Varner Blab1 chip

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Gary Varner (IRS chip)

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Gary Varner (Belle2 Upgrade)

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Gary Varner HPK SL10

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Gary Varner

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Gary Varner

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Miroslav Firlej, Jakub Moron, Marek IdzikAGH University, Poland

(University for Mining)

Development of fast transceivers for serialcommunication and general purpose PLLblock

Possible applications :

– Fast data transmission for the luminosity detector readout at the ILC

Multiplexed readout of multi-channel ADC PLL or DLL based timing for HEP experiments CMOS 350nm

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Miroslav Firlej, Jakub Moron, Marek Idzik

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• Second order Phase Locked Loop • “Current starved” VCO

PLL: 1st PLL: – 120MHz, 240MHz, 480MHz and 960MHz 2nd PLL: – One mode (~1GHz), wide frequency range

Low power ~4 mW

Clock and Data Recovery Burst mode CDR (two extra VCO steered by data signal

levels) Every change on data signal line restarts clock generation

with fixed phase shift Data recovery – removes noise and sharpens data slopes

Simple decision circuit with D flip- flop

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• Short term plans:

– DLL based transmitter for multichannel ADC in AMS 0.35 μm

– Low power fast (about 1GHz) transceiver in AMS 0.35 μm for

LumiCal data transmission

• Longer term plans:

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Gary Varner, Kurtis Nishimura, Matt AndrewFirst detector and DAQ test results from

the Univ Hawaii picosecond xray beamline

FEL = very tight bunch specs ~ 1ps timing probe

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Gary Varner, Kurtis Nishimura, Matt Andrew

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Summary

Access to multi‐project infrastructure (radio‐neutrino, FEL x‐rays, Super KEKB upgrade...) • Test beamline in Watanabe Hall commissioned Fall 2010 • intense flux ~1ps timing • Run ~ 8hrs/week, very easy access • Very nice facilities for • GHz ASIC input coupling, toward 1ps timing studies • ps vacuum, solid‐state detector studies • Integrated (~100 GB/s sustained, TB/s inst.) readout • Fast feature/processing/histogramming • Very easy “Experiment Proposal” procedure...

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Phase II:Tunable, mono‐chromatic x‐ray Source

Stabilized optical storage cavity

Tests of new detectors: 3D, new chips

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IRS input couplingPilas pulsed laser, gain with a mini-circuit amp, 20 GS/sTek digital scopeTest HPK SL10 MCP + baseCrosstalk tests

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Fast Timing Workshop Krakow, Nov 29 - Dec 1 st 2010 Part 2a.

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Transcript of Fast Timing Workshop Krakow, Nov 29 - Dec 1 st 2010 Part 2a.