Fast Single-Phase All Digital Phase-Locked Loop for Grid...

1523

https://doi.org/10.6113/JPE.2018.18.5.1523

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

JPE 18-5-21

Journal of Power Electronics, Vol. 18, No. 5, pp. 1523-1535, September 2018

Fast Single-Phase All Digital Phase-Locked Loop for

Grid Synchronization under Distorted Grid

Conditions

Peiyong Zhang†, Haixia Fang*, Yike Li*, and Chenhui Feng**

†,*College of Electrical Engineering, Zhejiang University, Hangzhou, China

**College of Physics and Information Engineering, Fuzhou University, Fuzhou, China

Abstract

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications.

In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and

good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a

result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency,

improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results

in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter

optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy.

The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer

(CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a

FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump,

frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response

and good robustness of the ADPLL.

Key words: ADPLL, CORDIC, DDS, Distorted grid, Single-phase

I. INTRODUCTION

Grid synchronization is a crucial aspect in grid-tied power

electronic applications, such as distributed generation (DG)

units, uninterruptible power supplies (UPS), grid power

converters, and so on. The key to this synchronization is how

to quickly and accurately obtain information on the utility

voltage, namely the phase, frequency and amplitude. Various

methods have been produced to achiever this. Phase-locked

loop (PLL) techniques have drawn a lot of attention owing to

their simplicity, robustness and effectiveness [1]-[3].

A PLL, which is a nonlinear negative feedback control

system, synchronizes its output in terms of frequency and

phase with its input [4]. It is composed of three parts: a phase

detector (PD), loop filter (LF) and voltage controlled

oscillator (VCO). The PD generates a phase error between the

input signal and the feedback signal. The LF filters the error

and provides a control reference for the VCO. Then the VCO

outputs the in-phase signal once the PLL is locked [5], [6].

Many different kinds of PLLs for grid synchronization

have been proposed. Depending on the application, these

PLLs can be divided into two major categories: single-phase

PLLs and three-phase PLLs. In general, the design of single-

phase PLLs is more complicated than that three-phase PLLs.

This is due to the fact that single-phase PLLs lack multiple

independent inputs to extract the phase error while three-

phase PLLs can easily obtain the error by an abc→dqo

transformation [7], [8]. The power- based PLL (pPLL) can

better illustrate this fact. It has the simplest structure but

suffers from obvious double-frequency oscillations [9]-[11].

Hence, synchronous rotating reference frame phase-locked

© 2018 KIPE

Manuscript received Jul. 16, 2017; accepted Apr. 6, 2018 Recommended for publication by Associate Editor Young-Doo Yoon.

†Corresponding Author: [email protected] Tel: +86-571- 8795-1679, Zhejiang University *College of Electrical Engineering, Zhejiang University, China

**College of Physics and Information Eng., Fuzhou University, China

1524 Journal of Power Electronics, Vol. 18, No. 5, September 2018

Fig. 1. Schematic diagram of the proposed ADPLL.

loops (SRF-PLLs) as a solution for this drawback have drawn a lot of attention in recent years [12]. They have been developed from three-phase PLLs and they use an orthogonal signal generator (OSG)-based PD to detect the phase error. According to the OSG, various SRF-PLLs have been designed, such as the delay-based PLL and the differential-based PLL. The inverse-park transform-based PLL (Park-PLL) and the second-order generalized integrator-based PLL (SOGI-PLL) are also SRF-PLLs. Both of them show a relatively fast transient response and a high disturbance rejection capability [13].

However, the complex grid environment poses higher requirements to traditional single-phase PLLs. Firstly, the PLLs must be able to remove dc offset, which leads to phase-locked inaccuracies. Even if the system is well designed, a dc component may arise due to temporary system faults, measurement devices and conversion processes [14]- [16]. By adding an in-loop low-pass filter (LPF), a dc feedback loop and a dc error compensation algorithm have been proposed in [14], [15]. They are always undesirable due to their bad influence on the dynamic response. Secondly, the PLLs must track the power frequency and achieve frequency self-adaption or the frequency variations brings errors. Feeding back the estimated frequency to the PD is always used [17]. However, such a frequency feedback loop decreases the system bandwidth and makes tuning sensitive, which reduces the stability margins and dynamic response [17], [18]. Thirdly, the PLLs must have enough filtering capability for harmonics to improve robustness. A good phase-locked accuracy and a fast response speed are the pursuit of PLLs. However, there is always a tradeoff between steady-state accuracy and transient response. Adding a feedback loop, like frequency and dc feedback loops, means introducing an additional tradeoff and deteriorating the dynamic performance [19], [20]. In addition, the traditional implementation of PLLs using microprocessors or DSPs is subjected to sequential operation. The sample rate of PLLs is limited, which impedes the improvement of the dynamic and steady-state performances.

In this paper, a new single-phase all digital PLL (ADPLL) is proposed to ensure a fast dynamic response. It is designed for Field Programmable Gate Array (FPGA) implementation

with a sampling frequency of 1MHz, which leads to potential improvements in the transient response and steady-state accuracy. The PD and VCO are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. Therefore, the detection of phase errors with a data width of 24 bits and a frequency control with a step size of 0.0596Hz can be acquired. Moreover, the ADPLL proposes a new method to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it is based on an open-loop method, which avoids the addition of an extra feedback loop. In this case, a new kind of parameter design method is used to obtain a large bandwidth and a fast response speed.

The rest of this paper is organized as follows. Section II introduces the basic structure of the ADPLL. Section III talks about the ADPLL implementation, including the discretization, configuration and parameter design. Section IV discusses a performance analysis of the ADPLL. In Section V experimental results are presented to validate the robustness and effectiveness of the ADPLL. Finally, some conclusions are given in the final section.

II. STRUCTURE OF THE ADPLL

In this section, a brief overview of the ADPLL is presented. As shown in Fig. 1, the ADPLL includes five parts: OSG, PD, LF, VCO and OUT. Each of the components is described in detail in the following.

A. OSG

The OSG includes a cascaded frequency-adaptive SOGI (CFA SOGI) and a parallel frequency detector (PFD). The CFA SOGI is based on adjustable parameters and designed with sufficient removal capabilities in terms of the harmonics and the dc offset. The PFD is adopted to detect the input frequency and to provide a frequency reference for the CFA SOGI to realize frequency self-adaption.

1) CFA SOGI Module:

The standard SOGI structure as an OSG is shown in Fig. 2, and the close-loop transfer functions are given in (1), where ω0 is the center frequency and k is the gain factor.

Fi

Fi

un

th

0,

m

st

or

w

ig. 2. Structure o

ig. 3. Bode diagr

G

G

α

β

⎧⎪⎪⎨⎪⎪⎩

Assuming that

nder a frequenc

he SOGI can be

, then k is les

momentary comp

ate its output

rthogonal signa

⎨

where:

of the SOGI.

(a)

(b)

rams of the SOG

2

( )( )

( )

( )( )

( )

s

s

in

s

s

in

V ss

V s s

V ss

V s s

α

β

= =

= =

t the input volta

cy-locked cond

e derived as (2).

ss than 2 (k<2

ponents of the S

s include an

l Vβs.

( ) cos(

( ) sin(

s

s

V t A

t AV

α

β

ω

ω

=

=

⎧⎨⎩

Fast Single-P

)

)

GI. (a) Gαs(s). (b)

0

2 2

0 0

2

0

2 2

0 0

k s

k s

k

k s

ω

ω ω

ω

ω ω

+ +

+ +

age is Vin=Acosθ

dition (ωin=ω0),

. Since 4-k2 mus

2). In addition,

SOGI. Therefor

in-phase signa

) ( )

) ( )

in s

in s

t v t

t v t

α

β

ω +

+

Phase All Digita

Gβs(s).

(1)

θin= Acos(ωint),

the outputs of

st be more than

vα and vβ are

e, in the steady

al Vαs and an

(2)

al Phase-Locke

f

n

Fig. 4. St

Gβs(s).

( )

( )

s

s

v

v

t

t

α

β

= −

= −

⎧⎪⎪⎨⎪⎪⎩

Fig. 3

diagrams

is fixed t

characteri

a) Gαs w

of ω0 whi

ω0. In add

However,

SOGI is s

b) If ω

The outp

orthogona

input freq

by -0.214

are chang

center fre

the accura

ed Loop for �

tep response di

0

0

1

2

0

1

2

0

cos(

sin(

k t

k t

A

A

e

e t

ω

ω

λω

λωλ

−

−

⎛⎜⎝

and Fig. 4 are

of the SOGI w

to 100π. From

istics can be obs

works as a ban

le Gβs is a low-p

dition, Gβs exhib

, it cannot provi

sensitive to dc o

in≠ω0, phase sh

puts of the SO

al. In the case

quency is 46(54

(-0.118) dB and

ged by 11.6° (-1

quency of the O

acy of the PLL.

(a)

(b)

iagrams of the

0 0) sin( )

2

)

kt t

t

λωλ

−

e Bode diagram

with different k v

m Fig. 3 and F

served.

nd-pass filter wi

pass filter with

bits a better filte

ide zero dc gain

offset.

hift and amplitu

OGI are impac

of the CGI OS

4) Hz, the amp

d 0.516(-0.881)

10.4°) and -78.4

OSG must be a

SOGI. (a) Gαs

)⎞⎟⎠ and

4λ =

ms and step re

values. In addit

Fig. 4, the fol

ith a center freq

a corner freque

ering feature th

n. This means t

ude attenuation

cted and inacc

SG in [16], wh

plitudes are atte

) dB, while the

4° (-100°). Hen

adjustable to gua

1525

(s). (b)

24

2

k−

esponse

ion, ω0

llowing

quency

ency of

han Gαs.

that the

occur.

curately

hen the

enuated

phases

nce, the

arantee


Fig. 5. Structure of the proposed CFA SOGI.

Fig. 6. Structure of the PFD.

c) The value of k can determine the bandwidth, response speed and filtering performance of the SOGI. A larger k makes a higher bandwidth, which offers a faster dynamic response with a bigger oscillation. It also means less immunity to the effects of harmonics in the grid voltage. On the other hand, a smaller k gives a narrower bandwidth and a better filtering capability to improve steady-state accuracy. However, it also results in a slower dynamic speed with a smaller overshoot. Therefore, the parameter k imposes a tradeoff between dynamic response and steady-state accuracy. A compromise must be made to obtain optimal performance.

In this paper, the modified SOGI structure shown in Fig. 5 is proposed. It is based on a cascaded SOGI structure. The first SOGI is used to remove dc offset, the second SOGI is used to improve attenuation capabilities of harmonics and the last SOGI works as an OSG. Moreover, they are all adaptive for the variation of the input frequency to guarantee phase- locking accuracy under frequency-varying conditions.

Note that the second SOGI uses Gβs instead of Gαs to obtain better attenuation capabilities in terms of harmonics. Meanwhile it introduces a 90° phase shift. Assuming an input grid voltage of Vin=Acosθin, the OSG outputs can be derived by:

( )

( )

cos 90 sin

coscos 180

in in

inin

V A A

V AA

α

β

θ θ

θθ

− °

= =

−− °

⎡ ⎤⎡ ⎤ ⎡ ⎤⎢ ⎥⎢ ⎥ ⎢ ⎥

⎣ ⎦⎣ ⎦ ⎣ ⎦ (3)

If the outputs are directly transmitted to PD, PD fails to work. Hence, a switch (W), like the one shown in Fig. 1, is needed and new assignments are given in (4). As a result, the proposed OSG achieves the same outputs as other OSGs.

cos

sin

in

in

V AX

Y AV

β

α

θ

θ

−

= =

⎡ ⎤ ⎡ ⎤⎡ ⎤⎢ ⎥ ⎢ ⎥⎢ ⎥

⎣ ⎦ ⎣ ⎦⎣ ⎦ (4)

2) PFD Module:

As shown in Fig. 6, the PFD is based on a parallel frequency detecting technology. In addition, a SOGI, which is used to reject dc offset, harmonics and other interferences in the grid voltage, is required to ensure high-accuracy frequency detection. Note that the parameter ω0 must be fixed, so that the fixed-parameter SOGI can still accurately transmit frequency information to the frequency detector and avoid a new feedback loop.

B. PD

Unlike previous PDs, the proposed PD can extract the phase error of sine and cosine signals. It is based on a CORDIC and a selector switch (SW) as follows.

1) CORDIC Module:

In the conventional SRF-PLL, a park transformation (5) is always employed as a PD. The outputs Vq and Vd carry the phase error and amplitude information, respectively.

qcos -sin

sin cosd

V V

VV

β

α

θ θ

θ θ=

⎡ ⎤ ⎡ ⎤⎡ ⎤⎢ ⎥ ⎢ ⎥⎢ ⎥

⎣ ⎦ ⎣ ⎦⎣ ⎦ (5)

In this paper, a CORDIC algorithm is used. It generates either a vector rotation or a vector translation. A vector translation rotates a vector (X, Y) to the x-axis and returns the angle θ. A vector rotation rotates a vector (X, Y) by the angle θ and yields a new vector (X’, Y’), as illustrated in (6).

'

'

cos( ) sin( )

cos( ) sin( )

X X Y

Y Y X

θ θ

θ θ

= × − ×

= × + ×

⎧⎪⎨⎪⎩

(6)

Thus, the CORDIC algorithm in the vector rotation mode essentially achieves the same result as a Park transformation. Moreover, it can be easily implemented on a digital platform by means of a simple shift-adder structure and it can obtain a good performance by the optimum use of computation resources.

2) SW Module:

In general, the OSG is directly connected to the PD. There is no problem when the input signal is a cosine signal. However, for a sine signal Vin=Asinθin, the PD fails to work and its outputs are derived as (7).

cos( )

sin( )

q out in

out ind

V A

AV

θ θ

θ θ

− −

=

− −

⎡ ⎤ ⎡ ⎤⎢ ⎥ ⎢ ⎥

⎣ ⎦⎣ ⎦ (7)

Apparently, Vq no longer reflects the phase error. This means that the PLL fails to lock the phase of sinθin. In this paper, a SW is used to deal with this issue. As shown in Table I, it works as a selector switch to produce different outputs by judging the output value of the PD (X’). XJD is a boundary value to distinguish between sine and cosine input signals.

C. LF

In this paper, a proportional-integral (PI) controller is chosen to implement the LF. The transfer function is shown in (8), where kp and ki are the proportional and integral parameters, respectively. Considering its direct influence on the PLL performance, a parameter optimization design is adopted and discussed in the following section.

( ) i

PI p

k

sG s k += (8)

Fast Single-Phase All Digital Phase-Locked Loop for � 1527

TABLE I

PRINCIPLE OF THE SW

Judging

condition

Judging

result

Outputs

Vq Vd Vout Voutq

X’< XJD Vin=Asinθin Y

’ -X

’ Asinθout Acosθout

X’> XJD Vin=Acosθin X

’ Y

’ Acosθout Asinθout

(a)

(b)

Fig. 7. Principle of the DDS: (a) DDS diagram; (b) phase wheel.

D. VCO

The VCO works as an integrator to generate the output phase angle. In this paper, it is realized by a DDS which has been widely used in practice due to its good frequency turning agility and high accuracy.

A DDS can produce a frequency-tunable and phase-tunable output signal according to a fixed-frequency clock. The relationship between the output frequency (fclk) and the input frequency tuning word (FTW) is expressed as (9), where Bθ is the width of the DDS and Δf is the frequency resolution. The FTW is an unsigned decimal number with no units.

2

clk

out B

f FTWf f FTW

θ

×= Δ × = (9)

A simplified diagram of the DDS is presented in Fig. 7(a). It consists of a phase accumulator (PA) and a phase-to- amplitude look-up table (LUT). The PA works as a phase wheel (PW), as shown in Fig. 7(b), and the LUT, basically a ROM, converts the digital phase into a digital amplitude. A cycle of the PW represents 360° and the points on the PW correspond to the content of the PA. At each system clock, the PW spins anticlockwise by an angle of the FTW points on

its current value. It is exactly the output phase of the DDS at this moment. Thus, the relation between two consecutive output phases, namely θout(n) and θout(n+1), can be expressed as (10). Then the discrete transfer function of the DDS can be deduced as (11).

( )( 1) ( ) 2

2

clk

out out sB

f FTW nn n T

θ

πθ θ×

+ = +

(10)

1 1

1 1

( ) 2( )

( ) 2 (1 ) 1

out clk s VCO s

VCO B

z f T z k T zD z

FTW z z zθ

θ π− −

− −

= = =

− −

(11)

The DDS works as an integrator as well. Therefore, it achieves the same result as other VCOs and outputs an in-phase angle. Moreover, it can export an in-phase waveform and is suitable for hardware implementation.

III. IMPLEMENTATION OF THE ADPLL

A. OSG

1) Discretization of the SOGI:

In this paper, the ADPLL is discretized by the zero-order hold (ZOH) method. Its transfer function ø(s) is (1-e-Ts)/s, where Ts is a sampling time. Therefore, the discrete results of the SOGI are:

( )

( ) ( ) ( ) 1

( ) ( ) ( ) ( )

s

s s

s s s

G s

D z s G s z sZ Z

D z s G s G sz

s

α

α α

β β β

φ

φ

−

= = ×

⎡ ⎤⎢ ⎥⎡ ⎤ ⎡ ⎤⎢ ⎥⎢ ⎥ ⎢ ⎥⎢ ⎥⎣ ⎦ ⎣ ⎦⎢ ⎥⎣ ⎦

(12)

By replacing k with √2 and bringing it to a canonical form, the discretization of the SOGI can be derived as follows:

1 2

1

1 2

1

1 2

1 2

1 2

1

( ) ( )( )

( ) 1

( )( )

( ) 1

s

s

in

s

s

in

D

D

V z A z zz

V z C z Dz

V z B z B zz

V z C z Dz

α

α

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β

− −

− −

− −

− −

=

=

−

=

− +

+

=

− +

⎧⎪⎪⎨⎪⎪⎩

(13)

where:

( )

( )

1

1

2

2

2

0

2 sin( )

2 2 cos( ) sin( )

2 2 cos( ) sin( )

2 cos( )

0.5 2=

s

A e

B e

B e e

C e

D e

T

µ

µ

µ µ

µ

µ

μ

μ μ

μ μ

μ

ωµ

=

= − +

= − −

=

=

−

⎧⎪⎪⎪⎪⎨⎪⎪⎪⎪⎩

2) Parameter Design of the SOGI:

Based on the analysis in section II, an optimal compromise between the dynamic speed, overshoot and harmonic rejection is crucial to determining the k value. As a result, the parameter k is selected as√2 to achieve a good comprehensive

PA

FTW

clk

LUT

+ +

sinθout

cosθout

θout

Phase

RegisterROM

15

pe

fo

Th

10

in

3

an

m

fr

m

ce

cy

m

B

1

di

ga

ve

ar

de

to

2

st

Th

eq

C

ac

tu

fr

re

D

1

2

us

m

th

528

erformance of t

our SOGI block

he parameter ω

00π. However,

nitial value is se

3) Parameter D

The PFD is b

nd the counter

measurement pr

equency signal

measured by de

enter frequency

ycle. Consideri

more than half a

. PD

1) Configurati

The CORDIC

iscrete transfer f

ain of the PD an

In this paper,

ector rotation m

rchitectural to

etection with a

o 1.

2) Parameter D

As shown in (

ate, while the

herefore, the b

qual to -0.5 in th

C. VCO

In this paper,

ccumulator and

uning word (FT

equency resolu

espectively.

D. LF

1) Discretizati

The PI is discr

(PI

D

2) Optimizatio

In the digital

sually a side e

mechanisms. Ea

he stability regio

the SOGI. Mor

ks are all set in

ω0 in the PFD

in the CAF S

t to 100π as we

Design of the PF

ased on a zero

r clock freque

recision is up

ls. Thus, the in

tecting every z

y of the CFA S

ing the settling

cycle, the adjus

on of the CORD

C block works

function is disp

nd is equal to th

( )PD

D z k=

the CORDIC is

mode and it is

reduce latenc

data width of 2

Design of the SW

(7), the output X

normal value i

oundary value

his paper.

the DDS is e

a 1MHz interna

TW0) is set at

ution are equa

on of the Pi:

retized by the Z

'

( )

( )( )

pPIkX z

X zz ==

n Design of the

circuits, loop

effect to pipeli

ch delay increa

on and deteriora

Journal of

reover, the valu

n this optimal

is a constant a

SOGI it is adju

ell.

FD:

o-crossing detec

ency is set a

to 0.0001Hz

nput frequency

zero-crossing o

SOGI can be ad

g time of the

sting time is eno

DIC:

s as a compa

played in (14), w

he input amplitu

PDk A=

s configured to

implemented w

cy. It features

24 bits. The ga

W:

X’ is equal to -A

is a relatively b

XJD can be set

equipped with

al clock. The ce

839. Therefore

al to 0.3745 a

OH method and

1

1

( )

1

p i s pkT k z

z

−

−

+ −

−

e Pi:

delays are un

ining, filtering

ases the system

ates the transien

f Power Electro

ues of k in the

tradeoff value.

and is equal to

ustable and the

cting technique

at 1MHz. The

for the power

can be exactly

of Vαr, and the

djusted twice a

SOGI, usually

ough.

arator and the

where kPD is the

ude.

(14)

o operate in the

with a parallel

s phase error

ain kPD is equal

A in the steady

big value (≈0).

t at -0.5A. It is

a 24-bit phase

entral frequency

e, its gain and

and 0.0596Hz,

d the result is:

(15)

navoidable and

or inner-loop

m order, limits

nt performance.

onics, Vol. 18, N

a

Fig. 8. Dis

Fig. 9.

ki=10.2012

kp=229376

Hence, a

necessary

OSG and

separate.

loop. The

as z-D1

and

equal to

known. T

ADPLL lo

(

( )

out

in

z

z

θ

θ

Since k

diagrams

be obtaine

Note th

achieve a

No. 5, Septemb

screte-time mode

Root-locus dia

2×106, and kp v

6, and ki alters fr

system analysi

y. As designed,

d the PLL loo

Fig. 8 shows th

e delays from th

d z-D2

, respectiv

3. In addition,

Then the discret

oop can be dedu

7 6

)=

) 2

VCO sk T

z z z− +

kVCO and Ts are

of the ADPLL

ed by MATLAB

hat the ADPLL

fast response s

ber 2018

el of the ADPLL

(a)

(b)

agrams of the

varies from 229

rom 10.2012×10

s with consider

, there is no f

op. Therefore,

he discrete-time

he CORDIC an

ely. In fact, D1

, DPD(z), DPI(z)

te close-loop tr

uced as (16).

4

5

(p VCO s i

VCO s p

k z k T k

z k T k z

+

+ +

known, based

loop with varia

B as Fig. 9(a)-(b

is stable on a l

speed, choosing

L loop.

e ADPLL loo

937.6 to 229375 to 10.2012×10

ration of the de

feedback betwe

their designs c

model of the A

nd DDS are de

is equal to 2 an

) and DVCO(z)

ansfer function

3

)

(

s p

VCO s i s p

T k z

k T k T k

−

−

on (16), a roo

ations of kp and

b).

arge scale. In o

g good kp and ki

op: (a)

760, (b) 10.

elays is

een the

can be

ADPLL

scribed

nd D2 is

are all

n of the

)

(16)

ot-locus

d ki can

order to

values

Fi

in

PI

di

gu

A

ba

ac

lo

a

re

sm

A

pr

tra

th

fr

ar

al

w

ig. 10. Step respo

n the unit circle

I are selected

irectly results

uaranteeing syst

IV. PERFOR

. Dynamic An

As analyzed a

andwidth via a

ccording to (16

oop can be plott

fast response

esponse is about

mall. This mea

ADPLL is mai

roposed OSG i

ansfer functions

(

(

G s

G s

α

β

⎧⎪⎪⎨⎪⎪⎩

Unlike the fre

he center freque

equency ωin. Th

⎧⎨⎩

vα and vβ are

re functions of

lgorithm (5) to

where vd and vq a

d

q

V

V

⎧⎨⎩

In the steady

onse diagram of

is crucial. As a

as kp=229376

in a high sy

tem stability.

RMANCE ANA

alysis

above, the ADP

an optimize par

6), a step respo

ted as Fig. 10. N

speed. A 5%

t 17us. In additi

ans that the d

nly determined

s a sixth-order

s are as follows

2

2

( ))

( ) (

( ))

( ) (

in

in

V ss

V s s

V ss

V s s

α

β

= =

= =

equency-locked

ency ω0 of the O

herefore, Vα and

( ) cos

( ) sin

V t A

V t A

α

β

θ

θ

=

=

⎧

⎩

momentary com

A, k, ω0 and t.

(18) yields the

are also moment

( ) cos(

( ) sin(

d in

q in

t A

t A

θ

θ

=

=

state, Vq conve

Fast Single-P

f the ADPLL loo

a result, the par

and ki=10.20

ystem bandwid

ALYSIS OF THE

PLL loop has

rameter design

onse diagram o

Note that the AD

% settling time

ion, the oversho

dynamic perfor

d by the OSG

integrator and

s:

3 5

0

2 2 3

0 0

3 4 2

0

2 2 3

0 0

-

)

)

k s

k s

k s

k s

ω

ω ω

ω

ω ω

+ +

+ +

d assumption in

OSG can alway

d Vβ can be deri

( )

( )

in

in

v t

v t

α

β

θ

θ

+

+

mponents of th

. Then applying

e Vd and Vq si

tary component

) ( )

) ( )

out d

out q

v t

v t

θ

θ

− +

− +

erges to zero. T

Phase All Digita

op.

rameters of the

12×106, which

dth while still

E ADPLL

a high system

n. In this case,

of the ADPLL

DPLL loop has

e for the step

oot is also very

rmance of the

G block. The

the close-loop

(17)

n other papers,

ys lock the grid

ved as:

(18)

he OSG, which

g the CORDIC

ignals as (19),

ts.

(19)

This means the

al Phase-Locke

Fig. 11. St

ADPLL s

the dynam

ADPLL.

whose dy

complexit

their step

11, and th

11. Note

zero. For

both equ

converges

The 5% s

is about 3

0.8 p.u..

big muta

performan

B. Robus

The pro

PD and w

and othe

diagrams

The pl

filtering f

The 3th, 5

with slop

and -75.

capabilitie

compared

Simula

ADPLL.

order, 0.0

componen

40% dc o

A harmon

Fourier Tr

reduced a

ed Loop for �

tep response diag

uccessfully lock

mic response of

In addition, Vd

ynamic reflects

ty of the math

response diagra

he correspondin

that the steady-

the step signal,

al zero in the

s to zero. Final

settling time of

30ms. In additio

The whole pro

ation. Thus, th

nce.

st Analysis

oposed OSG ge

works as a pre-fi

r interferences

of the OSG can

ots show that

feature. The dc

5th and 7th harm

es of -38.9dB

.6dB and -58

es of dc offset

d with the SOGI

tion results als

When the input

5p.u fifth-order

nts (8.12% Tota

ffset, the ADPL

nic analysis of

ransform (FFT)

and that only 0.0

grams of Vd, Vq a

ks the phase of

Vq is the phase-

Vd yields the gr

the dynamic of

hematical expre

ams are obtaine

ng response of V

-state value of

, according to (

e steady state.

lly, the PLL ten

f the ADPLL fo

on, the maximu

ocess is relative

he ADPLL sho

enerates an orth

ilter to eliminat

s. Thus, accor

be draw by MA

the proposed O

offset has been

monics for Gα an

and -29.3dB, -

8.6dB, respect

and harmonic

I.

o demonstrate

t voltage (Acos

r and 0.04p.u se

al Harmonic D

LL still achieve

f the ADPLL o

) shows that its

06% harmonics

and Vout.

the grid voltage

locked dynamic

id voltage amp

f Vout. Consider

ession for Vd a

ed by Simulink

Vout is also given

Vq, Vd and Vout

17) and (6), Vd

Therefore, Vo

nds to a steady

or the unit step

um overshoot is

ely smooth wit

ows a good tr

hogonal signal

e harmonics, dc

rding to (17),

ATLAB as Fig.

OSG exhibits a

n completely rem

nd Gβ are also d

-60.9dB and -4

tively. Its re

s are improved

the robustness

sθin) has 0.05p.u

eventh-order ha

istortion/ THD)

s good signal-tr

output Vout via

THD has been

remain. The de

1529

e. Thus,

c of the

plitude,

ing the

and Vq,

as Fig.

in Fig.

are all

and Vq

out also

y state.

p signal

s about

thout a

ansient

for the

c offset

, Bode

12.

a good

moved.

decayed

46.9dB,

ejection

d when

of the

u third-

armonic

) and a

racking.

a Fast

greatly

etected

15

Fi

m

V

be

ha

im

A

Th

Sl

RA

Fi

vo

sa

co

po

at

PD

fr

ef

ac

ex

in

di

ca

th

th

th

er

Th

Th

em

di

Vo

ph

530

ig. 12. Bode diag

maximum phase

Vector Error (TV

elow 0.57°) [2

armonics and dc

V.

The ADPLL

mplemented on

As mentioned abo

he total FPGA r

lice Registers 2

RAMB36E1 1, R

ig. 13 shows

oltage, which h

ampled by hall

onverters.

A FFT analysi

ower signal and

ttenuated. The d

D output Vq as

equency fout are

ffectiveness an

ctual grid voltag

In order to ful

xperiments un

ncluding voltage

istortion, dc of

arried out. Con

hese distortions

he distortional g

he input phase

rror can be exa

he power freq

herefore, the f

mulated grid vo

irectly fed to th

Vout, PI output s

hase error θe an

grams of the pro

error is about 0

VE) 1% standa

21]. Therefore

c offset.

EXPERIMENT

is designed an

a Nexys4 DDR

ove, the samplin

resources used o

320, Slice LUT

RAMB18E1 1,

experimental r

has distortion

sensor and tran

is demonstrates

d that the harmo

detected phase

θe) converges t

e also zero erro

nd practicability

ge.

lly evaluate the

nder various

e sag, phase jum

ffset and comb

nsidering the

on grid voltag

grid voltage has

angle θin can b

actly determine

quency voltage

following exper

oltage, which is

e ADPLL. The

signal XPI, dete

d detected mag

Journal of

posed OSG.

0.184°. This sat

ard (a maximu

e, the ADPLL

TAL RESULTS

nd coded using

R™ FPGA Boar

ng frequency is

on this impleme

Ts 7856, Occupi

DSP48E1s 136

results under th

and the THD

nsferred to the F

s that the output

onic component

error θe (in thi

to zero. The am

ors. They all d

y of the ADP

e performance o

distorted gri

mp, frequency s

bined disturban

difficulties of

ge, using a FPG

s great meaning

be obtained so

ed via a subtra

e V50 can also

riments are all

s generated by

input signal Vin

ected frequency

gnitude Am are al

f Power Electro

tisfies the Total

um phase error

L is robust to

S

g Verilog and

rd from Xilinx.

fixed to 1MHz.

entation include

ied Slices 2496

6 and BUFG 3.

he actual grid

is 1.7%. It is

FPGA via A/D

t wave Vout is a

ts are markedly

is case, use the

mplitude Am and

demonstrate the

PLL under the

of the ADPLL,

d conditions,

step, harmonics

nces, must be

implementing

GA to emulate

gs. In this case,

that the phase

action (θin-θout).

o be acquired.

l based on the

the FPGA and

n, output signal

y fout, detected

ll monitored by

onics, Vol. 18, N

,

a

d

Fig. 13. E

(a) Vin, Vou

Fig. 14. Ph

an oscillo

shows the

A. Dyna

1) Volt

response

there is a

overshoot

attains a

overshoot

2) Pha

response t

No. 5, Septemb

Experimental resu

ut, XPI and Am sig

hoto of the exper

oscope through

e experimental s

mic Experimen

tage Sag: Fig.

to a 40% volta

deviation of 0.

t of 8.6° in the

new steady sta

t.

ase Jump: Fig.

to a 90° phase j

ber 2018

(a)

(b)

ults of the ADP

gnals, (b) θe, fout a

rimental set-up.

two 16-bit D/A

set-up.

nts

15 shows ex

age sag in the g

1Hz in the dete

e detected pha

ate in 18ms w

16 shows ex

jump in the gri

PLL under grid v

and Am signals.

A converters. F

xperimental res

grid voltage. Al

cted frequency

ase error, the A

without any am

xperimental res

id voltage. Due

voltage:

Fig. 14

sults in

lthough

and an

ADPLL

mplitude

sults in

to this

Fi

Vi

Fi

Vi

ig. 15. Experime

Vin, Vout, XPI and A

ig. 16. Experime

Vin, Vout, XPI and θ

(a)

(b)

ental results of t

Am signals, (b) θe

(a)

(b)

ental results of th

θin signals, (b) θe

Fast Single-P

)

)

the ADPLL for

e, fout and Am sign

)

)

he ADPLL for a

e, fout and Am sign

Phase All Digita

voltage sag: (a)

nals.

phase jump: (a)

nals.

al Phase-Locke

Fig. 17. Ex

(a) Vin, Vou

disturbanc

amplitude

overshoot

condition

3) Freq

in respons

the detec

steady-sta

detected p

respective

frequency

internatio

4) Com

Park-PLL

PLL are

have been

this paper

quoted fr

PLLs aga

in Table I

Under

Park-PLL

speed. T

frequency

which sim

the other

ed Loop for �

xperimental resu

ut, XPI and fout sig

ce, there is a

e overshoot of 0

t of 20.1°. Note

is roughly 39m

quency Step: Fi

se to a frequenc

cted frequency

ate value in 27m

phase error an

ely. In fact, the

y variation fro

nal grid-tied sta

mparison: In th

L, SOGI-PLL,

selected. Cons

n researched in

r, the correspo

om paper [6].

ainst various dis

II.

a voltage sag c

, SOGI-PLL an

he Park-PLL,

y feedback loop

multaneously w

two cases, the

(a)

(b)

ults of the ADPL

gnals, (b) θe, fout

a frequency ov

0.22 per unit (p

e that the 5% se

ms.

g. 17 shows th

cy step from 50

y smoothly co

ms. The transie

nd amplitude ar

e ADPLL is ab

om 42Hz to 6

andards [3].

his paper, the D

DOEC-PLL, C

sidering that th

other studies an

onding experim

The transient p

storted grid con

condition, all of

nd CCF-PLL sh

SOGI-PLL a

p to realize fre

worsens the dyn

ey also show a

LL for a frequenc

and Am signals.

vershoot of 7H

p.u) and a phas

ettling time und

e experimental

Hz to 55Hz. No

onverges to it

ent overshoots

re 15.1° and 0

ble to achieve a

62Hz, which s

Delay-PLL, Der

CCF-PLL and

hese established

nd are not the fo

mental data is d

performances o

nditions are pre

f the PLLs exc

ow a relative re

and CCF-PLL

equency self-ad

namics. Theref

a slow dynami

1531

cy step:

Hz, an

se error

der this

results

ote that

ts new

for the

0.15p.u,

a wider

atisfies

ri-PLL,

TPFA-

d PLLs

ocus of

directly

of these

esented

cept the

esponse

use a

daption,

fore, in

ic. The

15

AD

De

De

Pa

SO

DO

CC

TP

D

a

be

of

Pa

sa

th

ar

re

fe

of

Pa

ex

co

an

sp

vo

W

sh

fa

U

gr

ph

B

of

gr

ph

oc

ze

co

fil

th

ha

N

7t

th

a

532

DYNAMIC

Settli

Vo

DPLL

elay-PLL

eri-PLL

ark-PLL

OGI-PLL

OEC-PLL

CF-PLL

PFA-PLL

18ms

22ms

0.0ms

60ms

55ms

16ms

30ms

15ms

DOEC-PLL also

dc compensat

eneficial to the

f the DOEC-P

ark-PLL. Mean

ame. The Delay

he frequency fe

re based on a

espectively. Bot

eedback loop an

f the cases are

ark’s and inver

xtra MAFs ar

omponents. Thu

nd other interf

peed for freque

oltage sag it rem

When compared

hows the best d

ast response, les

Under the frequ

reatly shortened

hase overshoot.

. Robust Expe

1) Dc Offset:

f the ADPLL. A

rid voltage at 30

hase error (12.9

ccur, the ADPL

ero steady-state

omplete elimina

2) Harmonics

ltering capabili

hird-order, 0.05

armonic compo

Note that the FFT

th harmonics in

hat only a few h

small oscillatio

TABL

C PERFORMANCE

ing time(5%) /Freq

ltage Sag P

/0.1Hz/8.6°

/2.9Hz/3.3°

s/0.0Hz/0.0°

/2.5Hz/6.7°

/2.9Hz/6.0°

/0.7Hz/2.0°

s/10Hz/5.5°

/1.5Hz/3.5°

39m

40m

40m

81m

70m

82m

104m

105m

employs a Park

tion loop to r

amplitude track

PLL for a vol

while, in the oth

y-PLL, Deri-PL

edback loop. T

fixed T/4 dela

th of the algorit

nd no filter. The

relatively fast.

rse Park’s trans

re needed to

us, it obtains a

ferences. Howe

ency step and p

mains fast due to

d to these PLLs

dynamic perfor

ss frequency ov

uency step con

d with zero freq

eriments

Fig. 18 evaluat

A sudden dc off

0ms. Although t

96°), frequency

LL attains a ne

e errors. That

ation capability

Distortion: Fi

ty of the ADPL

5p.u fifth-order

onents in the

T analysis dem

n the output si

harmonics are le

on in the detecte

Journal of

LE II

E COMPARISON OF

quency overshoot/P

Phase Jump

ms/7.0Hz/20.1°

ms/17.0Hz/16.2°

ms/17.0Hz/16.0°

ms/18.9Hz/37.0°

ms/22.0Hz/25.0°

ms/18.9Hz/40.5°

ms/16.6Hz/17.8°

ms/17.1Hz/28.8°

2

7

7

7

5

7

7

9

k-based OSG. H

remove dc off

king. Thus, the r

ltage sag is b

her two cases, t

LL and TPFA-

The Delay-PLL

ay algorithm an

thms are simple

erefore, their re

The TPFA-PL

sformations. In

filter unwant

filtering ability

ever, do to this

phase jump is s

o its insensitivit

s, the ADPLL

rmance. It show

vershoot and sm

ndition, the res

quency oversho

tes the dc rejec

fset of 40% is in

transient errors

(1Hz) and amp

ew steady state

is to say, the

in terms of dc o

g. 19 evaluates

LL in the prese

r and 0.04p.u

grid voltage (

monstrates that th

ignal are greatl

eft. However, it

ed phase error

f Power Electro

F PLLS

Peak phase error

Frequency Step

7ms/0.0Hz/15.1°

0ms/2.2Hz/16.0°

0ms/2.0Hz/12.5°

2ms/2.5Hz/17.0°

3ms/2.1Hz/15.5°

2ms/2.5Hz/17.0°

5ms/8.1Hz/21.0°

0ms/2.6Hz/25.0°

However, it has

ffset, which is

response speed

better than the

they are almost

-PLL all avoid

and Deri-PLL

nd a derivator,

e with no extra

esponses for all

LL is based on

n addition, two

ted frequency

y for harmonics

s, its response

slow while for

ty to amplitude

almost always

ws a relatively

mooth dynamics

sponse time is

oot and a small

ction capability

njected into the

in the detected

plitude (0.3p.u)

e in 28ms with

ADPLL has a

offset.

s the harmonic

ence of 0.05p.u

seventh-order

(THD=8.12%).

he 3th, 5th and

ly reduced and

t still results in

and amplitude.

onics, Vol. 18, N

d

a

.

.

a

r

Fig. 18. Ex

V50, Vout an

Fig. 19.

distortion:

and Am sig

No. 5, Septemb

xperimental resu

nd XPI signals, (b

Experimental re

(a) Vin, V50, Vo

gnals.

ber 2018

(a)

(b)

ults of the ADPL

b) θe, fout and Am

(a)

(b)

esults of the A

out, XPI and VoutF

LL for dc offset:

signals.

ADPLL for har

FFT signals, (b)

(a) Vin,

rmonics

) θe, fout

Fi

di

an

Th

0.

1%

an

of

(A

N

co

ph

Th

w

0.

vo

w

am

st

di

ex

er

A

co

B

ig. 20. Experim

isturbances: (a) V

nd Am signals.

he maximum p

.35° and 0.014p

% standard [21

nd dc offset.

3) Combined D

f the ADPLL to

Asinθin) along w

Note that in th

oincident to the

hase, frequency

his means that

well. At 30ms, a

.05p.u fifth-ord

oltage. After 40

with a peak-pea

mplitude error o

andard [21].

4) Comparison

ifferent abnorm

When a dc of

xcept the ADPL

rrors for lake of

ADPLL and DO

ompensation alg

oth of them sho

(a)

(b)

mental results o

Vin, V50, Vout, XPI

phase error an

p.u, respectivel

]. Thus, the AD

Disturbances: Fi

o sine signal. I

with harmonics

he steady state

e input sine sig

y and amplitude

the ADPLL ca

a 0.4p.u dc offse

der harmonics

0ms, the ADPLL

ak phase error

of 0.002p.u, wh

n: The robust pe

alities are prese

ffset occurs in

LL and DOEC-

f dc rejection a

EC-PLL use a

gorithm to remo

ow a good dc rej

Fast Single-P

)

)

of the ADPLL

I and VoutFFT sig

d amplitude er

y. This still sat

DPLL is robus

ig. 20 verifies th

In this test case

and a dc offset

e, the output

gnal. In addition

e errors all con

an lock the sin

et and 0.05p.u t

are injected

L reaches its ne

r of 0.32° and

hich also satisfie

erformances of t

ented in Table I

grid voltage, a

-PLL suffer fro

ability. On the o

CFA SOGI stru

ove the dc offse

ejection perform

Phase All Digita

for combined

gnals, (b) θe, fout

rror are below

tisfies the TVE

st to harmonics

he applicability

e, a sine signal

t is considered.

signal is well

n, the detected

nverge to zero.

ne-signal phase

third-order and

into the grid

ew steady state

d a peak-peak

es the TVE 1%

the PLLs under

II.

all of the PLLs

om steady-state

other hand, the

ucture and a dc

et, respectively.

mance with zero

al Phase-Locke

t

w

d

d

r

R

ADPLL

Delay-PLL

Deri-PLL

Park-PLL

SOGI-PLL

DOEC-PL

CCF-PLL

TPFA-PLL

steady-sta

performan

response

Under th

except for

TVE 1%

based on

CCF-PLL

However,

not enoug

enhanced

harmonic

and ADP

the TPFA

shows th

harmonic

amplitude

accurate

compariso

properties

In this

been pres

obtain hig

and frequ

contains n

tradeoff, i

A parame

delays is a

and to gu

experimen

are also c

ADPLL,

harmonic

than 39ms

under a fr

performan

overshoot

more than

ed Loop for �

ROBUST PERFORM

Peak-peak

DC offset

L

L

L

L

LL

L

L

0Hz/0°/0p.u

1.6Hz/1.7°/-

1.5Hz/1.5°/-

1.5Hz/1.8°/-

1.7Hz/1.9°/-

0.0Hz/0.0°/-

3.2Hz/3.8°/-

1.2Hz/1.2°/-

ate errors. They

nce. However,

since it does no

e harmonics d

r the Delay-PLL

standard [21].

a simple OSG

L uses a comp

, its filtering ca

gh. Therefore,

. Among these

rejection capa

LL, then the P

A-PLL is sensit

he best robust

s and dc offset

e information o

phase tracking

on, the ADPL

s.

VI.

paper, a single-

ented to ensure

gh steady-state

uency-varying c

no extra feedba

improves the dy

eter optimizatio

also employed t

uarantee system

ntal investigatio

arried out. The

in addition to i

s and dc offset

s) and a good ro

frequency step o

nce without freq

t. In addition, t

n twice that of o

TABLE III

MANCE COMPAR

k frequency error/ P

Harmonics Disto

0Hz/0.35°/0.00

3.8Hz/0.8°/-

8.7Hz/2.2°/-

1.1Hz/0.4°/-

1.2Hz/0.4°/-

0.9Hz/0.3°/-

1.5Hz/0.6°/-

0.0Hz/0.0°/-

also show a sim

the ADPLL h

ot have an add

distortion scena

L, Deri-PLL an

The Delay-PL

G with no filt

plex-coefficient

apability for 8.1

their filtering

PLLs, the TPFA

ability, followed

Park-PLL and S

tive to dc offse

t performance

t. Moreover, th

of the utility vo

g of sine and

LL shows the

CONCLUSION

-phase ADPLL

e a fast dynamic

accuracy under

conditions, a ne

ack loop, which

ynamic speed a

on design with

to obtain a good

m stability. The

ns on the perfor

obtained result

its sufficient rej

t, has a fast dy

obustness (below

of +5th, it show

quency deviatio

the settling tim

other established

RISON OF PLLS

Peak-peak phase e

ortion Combin

Disturba

5p.u

-

-

-

-

-

-

-

0Hz/0.32°/0

-

-

-

-

-

-

-

milar harmonic f

has a better dy

itional feedback

ario, all of the

nd CCF-PLL m

LL and Deri-PL

tering capabilit

t filter as an

12% harmonics

capabilities m

A-PLL shows th

d by the DOE

SOGI-PLL. Ho

et. Thus, the A

in the presen

e ADPLL can

oltage and achi

d cosine signa

best compreh

N

based on a FPG

c response. In o

r dc offset, harm

ew OSG is app

h avoids the und

and enhances st

consideration o

d transient perfor

eoretical analys

rmance of the A

ts demonstrate t

ejection capabil

ynamic respons

w 0.35°). In par

ws a smooth dy

on and less phas

me (27ms) has s

d PLLs.

1533

error

ned

ances

0.002p.u

filtering

ynamic

k loop.

e PLLs

meet the

LL are

y. The

OSG.

is still

must be

he best

EC-PLL

owever,

ADPLL

nce of

extract

ieve an

als. By

hensive

GA has

order to

monics

plied. It

desired

tability.

of loop

rmance

sis and

ADPLL

that the

ities of

se (less

rticular,

ynamic

se error

shorten


On the other hand, this design belongs to all digital PLLs. It can be easily embedded in other systems to realize rich functionality and implementation as low-cost chips. Looking at the trends of the grid synchronization techniques, the digitalizing and integrating of the PLL technique is conducive to the promotion of grid-tied technology and the development of the power electronics industry. Therefore, the proposed ADPLL is a competitive solution in engineering applications.

ACKNOWLEDGMENT

The project is supported by the National Science Foundation of China (61474098 and 61674129).

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Peiyong Zhang was born in Anqing, China,

in 1977. He received his Ph.D. degree from

Zhejiang University, Hangzhou, China, in

2004. In the same year, he joined the

Institute of VLSI Design, Zhejiang

University. Since 2004, he has been working

on VLSI designs for manufacturability.

Haixia Fang was born in Zhejiang, China, in

1990. She received her B.S. degree in

Electronic and Information Engineering from

Zhejiang University, Hangzhou, China, in

2013. She is presently working towards her

M.S. degree in the Institute of VLSI Design,

Zhejiang University. Her current research

interests include phase lock loops and high

speed SerDes.

Fast Single-Phase All Digital Phase-Locked Loop for � 1535

Yike Li was born in Sichuan, China, in 1996.

He received his B.S. degree in Electrical

Engineering from Zhejiang University,

Hangzhou, China, in 2018. He is presently

working towards his M.S. degree in the

Institute of VLSI Design, Zhejiang

University. His current research interests

include low-power high-speed transceiver

modules in integrated circuits.

Chenhui Feng was born in Pingtan, China,

in 1990. He received his B.S. and Ph.D.

degrees from Zhejiang University, Hangzhou,

China, in 2011 and 2016, respectively. He

joined the College of Physics and

Information Engineering, Fuzhou University,

Fuzhou, China, in 2016. His current research

interest include on-chip parameter extraction.

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