FAST DIGITIZATION AND DIGITIAL RECEIVER TECHNOLOGY

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FAST DIGITIZATION ANDDIGITIAL RECEIVER

TECHNOLOGY

INTRODUCTION

A/D CONVERTER ARCHITECTURES

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LEVELDECODE

1 (FULL SCALE)

2n

2 (FULL SCALE)

2n

2n - 2 (FULL SCALE)

2n

2n - 1 (FULL SCALE)

2n

AIN...

DOUT

FLASH A/D ARCHITECTURE

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SAMPLEAND HOLD

m-bit ADC

DAC

DOUT

DOUTAIN

DIN

AINAOUT

+

-

++

Σ

Σ(m-bits) 2*(m-bits)

PIPELINED A/D ARCHITECTURE

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SAMPLEAND HOLD

AIN +-

Σ ADC

DAC

SAR DOUT

SUCCESSIVE APPROXIMATION A/D ARCHITECTURE

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AIN

1-BITDAC

DIGITALFILTER

ANDDECIMATOR

DOUT

+

-

ΣDOUT

BITSTREAM

COMPARATORINTEGRATOR

SIGMA-DELTA A/D ARCHITECTURE

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A/D SPECIFICATIONS

Signal-To-Noise Ratio (SNR or S/N)rms Signal to rms Noise

Quantization Error = V*LSB/√12rms Signal = 0.5 V/√2

SNR = 2n√3/√2 = 1.225*2n

SNRdb = 20 Log (2n√3/√2)SNRdb = 20 Log (2)*n + 20 Log (√3/√2)SNRdb = 6.021*n + 1.763 (dB)

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Dynamic Range (DR)

Signal-to-Noise And Distortion (SINAD)

Effective Number of Bits (ENOB)

ENOB (bits) = (SINAD -1.763)/6.021

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Aperture Uncertainty (Jitter)

Seconds rms

SNR = -20 Log (2πFin*Tau)

For Tau = 0.25 ps rms

Fin = 10 MHz, SNR = 96 dB



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Spurious-Free Dynamic Range (SFDR)

Amplifier SFDR = 2/3(P1-P0-10Log(BW)-NF)P1 = IP3 - GAINPO = Input Noise Power (-114 dBm, 50 Ohms)BW = Bandwidth in MHzNF = Noise Figure

Example:SFDR = 2/3(+38-16-0-114+4) = -88 dB

A/D SFDR = rms signal to peak spurious component

A/D SFDR can be > ideal SNR

Dither Noise for Better SFDR

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Processing GainFrequency Domain

Gain = 10 Log (number of points) ComplexGain = 10 Log (number of points/2) Real

Time DomainA/D Integrated Noise Is ConstantIncreasing Sample Rate Lowers Noise Per SampleGain = 10 Log (Decimation)

Filter Design Can Give Slight IncreaseThere Is A Limit To The Passband Noise FloorCorrelated Digital Sample Noise Floor

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DigitalLow-PassFilter(Optional)

DigitalLow-PassFilter(Optional)

AMPRF

Input

LO 1

LocalOscillator

Power Splitter2-Way90 Deg.

I

0DegPower Splitter

2-Way0 Deg.

Q

I & Q Demodulator

L.O.

RF

90DegLocal

Oscillator

LO 2

Sq. LawDetector

A/DConverter

Sq. LawDetector

A/DConverter

I

Q

Baseband

1st IF

ANALOG RECEIVER

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AMPRF

Input

LO 1

LocalOscillator

A/DConverter

NCO

(LO 2)

Sine

Phase Offset

Tuning Frequency

I

Q

Cosine

1st IF DigitalLow-PassFilter

DigitalLow-PassFilter

Baseband

DIGITAL RECEIVER

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D(n-1) to D0

IFInput A/D

Converter(n Bits)R

XFMR(>/=1:1)

Matching

IF INPUT A/D

Digitization Requirements

Band-Limited

Headroom

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Digital Mixing

Fs/4 Up/Downconversion

I(t) = A(t) consine (2π F(t))Q(t) = A(t) sine (2π F(t))0° - 90° - 180° -270°

Consine Sequence1 0 -1 0

Sine Sequence0 -1 0 1

Fs/2 Spectral Inversion (1, -1)

Numerically Controlled Oscillator (NCO)

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Phase Increment(Frequency Tune

Word)

Sine

In-PhaseData Output

QuadratureData Output

Cosine

RealData Intput

CORDIC Engine(SINE/COSINE)

PhaseAccumulator

Phase Offset

Phase Value

A(t)

Q(t)

I(t)

I(t) = A(t)cosine(PV(t))

Q(t) = A(t)sine(PV(t))

NCO BLOCK DIAGRAM

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CORDIC Precision

Clock Rate (LO Frequency)

Multipliers (18 x 18)

Interleaved NCO’s

I(t) and Q(t) Filtering

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Digital Filtering

CIC (High Decimations)

FIR (Sharp Response)

Commercial Digital Receiver Chips

Analog Devices

Graychip (TI)

Harris (Intersil)

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DECIMATEBYR

(N Stages) (N Stages)(M=1)

Integrator Comb

Fs FsR

Decimating CIC Filter

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CIC Response (Decimating)

Magnitude Squared P(f) = (1/(M*R)N)2 sine (πMfR/fs)/sine(πf/fs))2N

fs = input sample rateR = decimationf = input frequency

Often Plotted Normalized to fout = fs/RP(f) = (sine(πMf)/sine(πf/R))2N

P(f)dB = 10 Log (P(f))

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CIC RESPONSE

Decimate by 4, Varying Order Varying Decimation, Order = 4

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CIC ALIAS REJECTION

Order = 4, Decimation = 4 Order = 4, Decimation = 64

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FIR Filters

Transversal Filter EquivalentSharp ResponseNumber of TapsNumerical PrecisionPolyphaseFully ParallelSymmetrical Coefficient FIR is Phase LinearWindow Functions (Blackman, Hamming, etc.)Remez (Parks-McClellan)

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5 Tap Symmetric FIR Filter

X(n)

Y(n)

h0(h4)

h1(h3) h2

X(n-1) X(n-2) X(n-3)

X(n-4)X(n-5)

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FIR BLACKMAN

Decimate by 4

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FIR BLACKMAN

Decimate by 16

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CIC ALIAS REJECTION

Order = 4, Decimation = 64

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DC CICFIN2

CIC (Order 4, Decimate by 64) with 127-Tap FIR, Decimate by 2(18-Bit Coefficients, Decimate by 4 Design)

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CIC (Order 4, Decimate by 64) with 127-Tap FIR, Decimate by 2(18-Bit Coefficients, Decimate by 4 Design)

DC FIRFIN2

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0 3.24 6.48 9.72 12.96 16.2 19.44 22.68 25.92 29.16 32.4140

130

120

110

100

90

80

70

60

50

40

30

20

10

0

10Frequency Domain Channel 1

Frequency MHz

Pow

er d

Bm

ECDR-GC314-PMC Raw A/D Data

Source: 21.03 MHz. 5.5 dBm @ HP8664A with 20 MHz HPF and 32.4MHz LPF at Channel 1 Input. Clock: 64.8 MHz. Crystal Oscillatorwith 60 MHz HPF and 65 MHz LPF. 2048 Point FFT

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127 111.125 95.25 79.375 63.5 47.625 31.75 15.875 0 15.875 31.75 47.625 63.5 79.375 95.25 111.125 127140

130

120

110

100

90

80

70

60

50

40

30

20

10

0

10Frequency Domain

Frequency KHz

Pow

er d

Bm

ECDR-GC314-PMC Receiver Data

Source: 21.03 MHz. 5.5 dBm @ HP8644A with 20 MHz HPF and 32.4MHz LPF at Channel 1 Input. Center Frequency at 21.02355 MHz.Clock: 64.8 MHz. Crystal Oscillator with 60 MHz HPF.Receiver Processing Gain = 10Log(256) = 24 dB, 4096 Point CFFT.A/D S/N (Jitter) = -20Log (2π21.03x106(0.1x10-12)) = 97.6 dB

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Digital Receiver Advantages

Improved PerformanceReduced Components and CostNo Component Tolerance, Frequency or Temperature, etc. DependenceReduced ObsolescenceImproved SFDRNear Perfect I&Q BalanceNear Perfect Filtering

Application CommonalityEasily ReconfiguredReduced System I/ODistributed Processing

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Product Design Considerations

Today’s Technology RequirementsSchematic Capture

Component LibrariesParts FootprintsBOMNetlistNotes and Documentation

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Board Layout

CADAuto-routersMulti-layerViasControlled ImpedanceMechanical ConsiderationsSpecial Requirements (Mixed-Signal)

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Product Manufacture

PC Board ManufactureCapabilities RequiredMin. Quantities Hole Size, Line Width, ControlledImpedance, Testing, etc.

PC Board StuffingMin. Quantities, Component Size, Inspection,Testing, etc.

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Example Beam Instrumentation Product Design

Bunch-by-Bunch Current MonitorInclude Co-adding

Support Beam Steering

Example ParametersFRF = 360 MHz = FCLKNumber of Bunches = 300FREV = 1.2 MHzTrigger = Bunch 1Four BPMsBand-limited Analog Inputs

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Design Elements

A/D: AD9430 (12-bits, >210 MSPS, 700 MHz BW)Time-Interleaved Pairs

PECL Clock Logic

Programmable LogicAltera Stratix FPGA (One Per Channel)In-Circuit Reprogrammable Configuration

Standard Bus Interface (VME, PCI, etc.)

Additional Altera Stratix FPGABeam Steering Algorithms

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A/D Converter#1

Primary Bus

Ain1(360MHz) Bunch-By-Bunch

StratixFPGA

Beam-SteeringStratixFPGA

Local Data Bus

Primary Bus Interface

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A/D Converter#2

PECLClockLogic

ClockInput

TriggerInput(Pulse)

TriggerControlLogic

System Clock

System Trigger

Other 3Channels

FlashFPGA

ProgramMemory

FPGA Prog

A/D SampleClocks(180MHz)

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LVDS-TO-LVTTL

Dual PortRAM

Local Data Bus

Timing&

ControlLogic

Clock

Trigger

FIFOMemory

LVDS-TO-LVTTL

Logic

A/D #1 DataLVDS 180MSPS

A/D #2 DataLVDS 180MSPS

Logic Logic Logic

Dual PortRAM

Dual PortRAM

Dual PortRAM

FIFOMemory

FIFOMemory

FIFOMemory

Output Logic

Beam-SteeringFPGA

90MSPSControl

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Other Bunch Data Processing Options

Individual Bunch FilteringIndividual Bunch Digital Receiver (1.2 MHz)Multi-Bunch Digital Receiver (360 MHz)

Beam Steering Algorithms

Difference-Over-SumAM/PM ConversionLog-RatioStable Beam Suppression

IP Cores

Log, Rectangular-to-Polar, FIR, DFFT, etc.

In-Circuit Programming

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The Stratix Device FamilyThe Stratix Device Family

94

194

224

295

384

574

767

1,118

10,570

18,460

25,660

32,470

41,250

57,120

79,040

114,140

60

82

138

171

183

292

364

520

1

2

2

4

4

6

9

12

920,448

1,669,248

1,944,576

3,317,184

3,423,744

5,215,104

7,427,520

10,118,016

6

10

10

12

14

18

22

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LogicElements

Device 32x18M512

Blocks

128x36M4K

Blocks

4,096x144MegaRAM

Blocks

Total RAMBits

DSPBlocks

EP1S10

EP1S20

EP1S25

EP1S30

EP1S40

EP1S60

EP1S80

EP1S120

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Package Offerings & User I/OPackage Offerings & User I/O

EP1S10

EP1S20

EP1S25

EP1S30

EP1S40

EP1S60

EP1S80

EP1S120

341

422

469

35 x 35

679

679

679

679

40 x 40mm 341

422

469

27 x 27422

582

593

593

29 x 29

702

726

769

769

33 x 33mm

818

1,018

1,199

40 x 40mm

1,234

1,310

45 x 45mm

Device 672-PinBGA

Wire-Bond1.27 mm

956-PinBGA

Flip-Chip1.27 mm

672-PinFBGA

Wire-Bond1.0 mm

780-PinFBGA

Flip-Chip1.0 mm

1020-Pin

FBGAFlip-Chip

1508-Pin

FBGAFlip-Chip

1923-Pin

FBGAFlip-Chip

Vertical Migration Supported

FAST DIGITIZATION AND DIGITIAL RECEIVER TECHNOLOGY

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