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Fall 2005 Yield Management Solutions

Where in the World is the Process Yield Window?Conjoint DFM and APC Strategies for Reducing Hidden Systematic Errors at 65 nm and Below

Kevin Monahan and Brian Trafas, KLA-Tencor Corporation

Immersion lithography at 193 nm has emerged as the leading contender for critical patterning through the 32 nm technology node. Super-high numerical aperture (NA), along with attendant polarization effects, will require re-optimization of virtually every resolution enhancement technology and the implementation of advanced process control (APC) at intra-wafer and intra-field levels. Furthermore, interactions of critical dimensions (CDs), profiles, roughness, and overlay between layers will impact design margins and become severe yield limiters. In this work, we show how design margins are reduced as a result of hidden process error and how this error can be parsed into unobservable, unsampled, unmodeled, and uncorrectable components. We apply four new process control technologies that use spectroscopic ellipsometry, grating-based overlay metrology, e-beam array imaging, and simu-lation to reduce hidden systematic error. Feedback of super-accurate process metrics will be critical to the application of conjoint design for manufacturability (DFM) and APC strategies at the 65 nm node and beyond. Manufacturing economics will force a trade-off between measurement cost and yield loss that favors greater investment in process control.

Addressing pattern limited yieldIn this work, we assess the impact of hidden error on pattern limited yield and generate unique CD and overlay-limited yield models for the 65, 45, and 32 nm nodes. We expect 193 nm immersion lithography to remain the domi-nant patterning technology at the 32 nm node (Figure 1). Even at the 130 nm node, the interaction of more complex designs with shrinking process windows was already evident. In memory manufacturing, for example, ramp delays of several months were common, leading to revenue losses in the tens of millions of dollars per product and reduction of ROI for 300 mm factories. Ramp delays occur primarily for two reasons: lengthy process optimization for smaller yield windows and increased time allocated for more complex intra-field cor-rections (e.g., re-design and re-layout). We and the semiconductor industry are

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attacking this problem using DFM and APC strategies. Although the exact definitions of DFM and APC vary significantly with manu-facturing context, the goals are clear. The primary goal of DFM is to enlarge the process yield window, and the primary goal of APC is to keep the process in that yield window.

A simplified scheme for conjoint DFM and APC strategies is shown in Figure 2. Implementing the DFM strategy requires feeding for-ward design intent, simulator out-put, layout clips, and design-rule-check (DRC) hot spots. Current DRC and aerial image modeling at best focus and exposure conditions is increasingly unreliable. Process-win-dow-aware approaches will require powerful full-chip simulators that can accurately predict and mea-sure developed patterns in resist, along with a super-computing environment that can produce results in an acceptable timeframe. On the process control side, implementing an APC strategy requires feeding forward process context data and prior-step measurement data. In the future, both context and measurement data must increase. In particular, mea-surement sample plans will increase dramatically to support multi-variate control at the lot, wafer, field, die, and intra-die levels.

Note that process metrology is at the center of a conjoint DFM and APC strategy. For example, yield window improvements depend on accurate feedback of CD and overlay variation to set design margins. Full-chip simulators require resist model calibration, and yield prediction depends on correlation with metrology, inspection, and electrical test data. Likewise, control improvements also depend on accurate feedback of measurement

data to update control models, to correctly analyze CD and over-lay variation, to adjust process tool settings, and to establish correlations to device performance and yield with high levels of confidence.

Systematic design-to-process yield loss is mostly pattern limited and is a grand challenge for semicon-ductor manufacturing at the 65 nm node and beyond. The root-cause is the yield gap originating from

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Figure 1. Lithography at the 32 nm node may be dominated by 193 nm, super-high NA immersion technology using numerical apertures ranging from 1.3 to 1.5. A daunting array of CD, overlay, and systematic defect challenges will require conjoint DFM and APC strategies to enable yield.

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Figure 2. Process metrology is at the center of a conjoint DFM and APC strategy. Both DFM and APC depend on feedback of accurate measurement data and on removing hidden process error.

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Fall 2005 www.kla-tencor.com/magazine

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the interaction of more complex designs with shrinking lithographic process windows1. Using past trends and pinning to recent yield data, we can generate models for pattern-limited yield2, as shown in Figures 1-6. Projections of pat-tern limited yield to the 32 nm technology node indicate a strong need for innovation to

improve yield in early production. The projections for mature defect- limited yield are still relatively high. An 85 percent yield entitlement for mature 140 nm DRAM production would lie directly on the curve, but the yield-dollar impact of a 3-6 month delay in early production can be tens of millions of dollars per product.

Memory speed deficits and time- to-market delays impact initial average selling price and die cost, drastically reducing ROI for 300 mm factories. Specific cost and perfor-mance issues can vary significant-ly by product type, as shown in Figures 5 and 6 for memory and logic, respectively.

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Figure 3. Rapidly shrinking process windows have created a pattern-limited yield

crisis in early production since the 130 nm technology node. Ramp delays can

last several months and cost tens of millions of dollars.

Figure 4. Going forward, systematic error will be the primary cause of yield

loss in early production. Innovative conjoint DFM and APC strategies must be

employed to close the design-to-process yield gap at 65 nm and beyond.

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Figure 5. Overlay limited yield is a key contributor to yield loss for memory in

early production. Windows are shrinking and hidden, unobservable, unsampled,

and unmodeled process errors are limiting yield entitlement at “zero error”.

Figure 6. CD limited yield is a key contributor to yield loss for logic in early

production. Windows are shrinking and hidden, unobservable, unsampled,

and unmodeled process errors are limiting yield entitlement at “zero error”.

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Accurate feedback for DFM and APCThe prospect of massive systematic yield losses at the 65 nm node and beyond will drive conjoint DFM and APC strategies. The success of these strategies is critically dependent on feedback of accurate metrology data and on removing the types of hidden process errors shown in Figure 7. As super-high NA immersion lithography drives CDs smaller, process windows are expected to shrink commensurately. A necessary con-dition for smaller design rules is the control of edge placement error (EPE). In the factory, we mea-sure EPE as two separate com-ponents: pattern placement error (PPE) and critical dimension error (CDE). Both are affected by hidden process errors, such as lithographic dose and defocus that may or may not be measured directly4. As demonstrated in Figure 7, CD and overlay ultimately share a common error budget and constrain the designer’s intent to shrink design rules, improve performance, or increase yield entitlements.

Four types of “hidden error” are expected to limit yield in the era of immersion lithography:

• Unobservable error. Some systematic variations are profile-related and may not be measurable with the current generation of metrology tools. For example, traditional top-down SEM and electrical CDs miss yield-relevant footing and notching at the bottom of gate structures; these excursions are measurable using spectroscopic ellipsometry-based CD systems (SCD). CD SEMs also suffer from poor material contrast on shallow trench isolation (STI) stacks where the critical silicon top CD is obscured by a nitride structure; again, these excursions are measurable using SCD. On the other hand, SCD measure-ments are limited to grating targets and can miss yield-relevant shape excursions inside the device (e.g., an SRAM cell). In the case of overlay, large box-in-box targets may be subject to process- induced distortion or, because of their size, may not be sensitive to coma-induced, design rule PPE across the lithographic field.

• Unsampled error. Assuming the CDE is measurable, sparse sample plans may still fail to capture actual statistical distributions. If the mean of the sample distribution is shifted, aliased inputs will defeat APC systems and result in costly yield loss, leaving insufficient historical data for robust root-cause analysis. As an example, traditional atomic force micro-scopes (AFMs) often miss STI profile excursions because sample plans are throughput limited; this is typically not the case for SCD. Insufficient sampling increases alpha and beta risk during ADI and ACI dispositioning, resulting in unnecessary rework, scrap, or yield loss. In the case of overlay, die-level PPE sampling using small targets may be required to support higher- order intra-field models. For nascent super-high NA immersion technologies that use directional liquid injection, it may be appro-priate to revisit boustrophedonic sampling plans that separate the effects of stage and scan direction.

• Unmodeled error. Simple run-to-run control models are no longer adequate for the 65 nm node and beyond. Model-based APC must take into account CD variation at the lot, wafer, field, and die levels. As much as 80 percent of mea-sured CDE in lithography results from changes in effective focus or exposure, and most of this is now intra-wafer variation. Underlying root causes are a combination of reticle, lens, scan, stage, track, and etch variation. For immersion lithography, formerly small interaction effects will become more important. Focus and exposure, profile and overlay, wafer and field, and litho and etch interaction effects should be modeled simultaneously. For nascent super-high NA immersion tech-

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Figure 7. In-chip 65 nm failure analysis showing gate-to-contact shorting. Deprocessing revealed a total of seven

different error types contributing to yield loss, including overlay error interacting with CD dilation, profile excursion,

and roughness error on the gate layer and CD dilation, profile excursion, and roughness error on the contact

layer. Most types were classified as hidden error.

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nologies, control of edge-die focus and exposure may be critical, and models should anticipate and enable shot-level correction.

• Uncorrectable error. Even if CDE is accurately modeled with low systematic residuals, it may not be correctable in the factory and must be treated as a DFM issue. For example, CDE on the reticle could require a new mask or costly redesign. In other cases, process ad-justments that could compensate for CDE are simply not accessi-ble. Most stepper suppliers allow shot-to-shot dose and focus cor-rection across the wafer, but few support field-dependent piston-and-tilt corrections that could minimize total intra-wafer varia-tion. In the case of overlay, higher- order scanner errors may be observed, sampled, and modeled; but, again, no means of correction may exist inside the factory. In such cases, the burden of correction shifts to DFM.

In the following sections, we discuss four technologies that were created to minimize hidden systematic error and to provide more accurate and comprehensive feedback for conjoint DFM and APC strategies.

Accurate grating-based overlay metrologyAccuracy of overlay measurement may be compromised by process-induced distortion of traditional box-in-box overlay targets. Errors fed back into APC systems drive incorrect scanner adjustments that can take a process out of its yield window. Likewise, erroneous data fed back into DFM strategies drives incorrect margin setting that can result in smaller yield windows. Replacing box-in-box tar-gets with grating-based (AIM) targets greatly increases robustness to pro-cess variation5, as shown in Figure 8.

The most critical layer pairs are usu-ally active-to-gate, gate-to-contact, and contact-to-metal. Active-to-gate misregistration, specifically with respect to the line-end, can result in gate leakage or reduced static noise margin. Gate-to-contact misregistra-tion, particularly in conjunction with CD, profile, or roughness error, can result in shorts and functional failure. Contact-to-metal misregistration quite often results in resistive or open interconnects. As the number of metal layers increases, the probability of a metal-to-via overlay failure also in-creases, particularly for layers pat-terned with aggressive pitch.

In addition to process-induced error such as that created by CMP or asymmetric metal deposition, there may be higher-order intra-field error from the reticle and scanner than can account for as much as 50 percent of the overlay model residuals. The effectiveness of APC is reduced in such cases, and DFM strategies must be used to increase the yield window. At least two strategies for target design

are being tested. First, with a small sacrifice in performance, Archer AIM targets may be shrunk to about 10 µm on a side to enable in-chip overlay metrology. Second, if lithographic lens aberrations such as coma are significant, design-rule structures may be incorporated in the bars of the grating target so that feature-size effects are faithfully replicated. Back-end designers should note that, to support conjoint APC and DFM strategies, these targets must be sub-ject to the same resolution enhance-ment technique (RET) treatments used to enhance printability in the chip. The PROLITH™ simulator can be a useful tool in such applications.

Accurate ellipsometry-based profile metrologyPattern noise in CD-SEM measure-ments can compromise performance of front-end-of-line (FEOL) APC loops, resulting in lower yield and performance entitlements. Replacing SEMs with spectroscopic ellipsom-etry-based CD systems, as shown

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Figure 8. Overlay measurement accuracy may be compromised by process-induced distortion of traditional box-

in-box overlay targets. Replacing box-in-box targets with grating-based (AIM) targets, shown above, can increase

target robustness, APC performance, and device yield.

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in Figure 9, provides more spa-tial averaging and more yield- relevant correction of gate CD and L-cap errors6. Gate stack profile metrology is a common application of SCD because of the association of footing and notching with yield loss due to drive current deficien-cies and gate leakage, respec-tively. In the case of traditional top-down SEM metrology, such yield- affecting fine structure is typically unobservable, hidden systematic error. These profile variations are also known to affect subsequent sidewall spacer and implant steps. Remark-ably, given the small size of the fine structure and the lower information content, static and dynamic precision are still typically less than 0.4 nm 3-sigma, providing the sensitivity to detect and correct nanometer-scale etch offsets that can tie all the way back to lithography.

For DFM strategies, SCD 3D contact metrology is now especially important because small, sloped, or footed open-ings are associated with excessive con-tact resistance and yield loss. The low static noise floor (~0.1 nm) of the SCD system enables precise measurement of faceting and footing in addition to CD. In addition, yield-relevant aspect-ratio metrology becomes feas- ible since we avoid the spatial, temporal, and technology de-cor-relation often associated with com-pound measurements using multiple tools. Furthermore, the low dynamic noise floor (~0.2 nm) enables accurate crossfield and cross-wafer comparison. Both elliptical and rectangular contacts can be measured in any orientation, and most contact attri-butes can be measured and used for process control. In addition, an ever expanding variety of rectangular, triangular, and paired layouts are supported to enable sophisticated

DFM strategies. Because of its high precision and accuracy, SCD can also be used as a calibration tool for the PROLITH simulator.

Accurate SEM-based roughness/array metrologyCD-SEMs can uniquely character-ize and monitor line-width rough-ness (LWR) and line edge roughness (LER) for DFM applications that address the insertion of immersion lithography into volume production7. For immersion lithography, LWR varies significantly with resist and top coat characteristics. In fact, if current levels of LWR are not reduced, device yield will trend to zero at the 32 nm technology node. The use of top coats in immersion lithogra-phy adds another opportunity for systematic process error. In particular, we have found that LWR is a strong function of cross-wafer, top coat uni-formity. The CD-SEM (eCD-1) used for the study is capable of generating online LWR analysis, as shown in Figure 10. A controlled overdose experiment revealed no significant change in the LWR measurement after 100 images had been acquired. The LER, however, was visibly reduced.

Due to the challenges of creating robust SCD models for back-end- of-line (BEOL) metrology, CD-SEMs are likely to be the main APC enablers for some time. Two key problems compromising accurate and robust APC performance have been solved uniquely on eCD-2 Class SEMs. First, line/space identification error in older-generation CD-SEM measure-ments has been decreasing yield and increasing rework in the BEOL ap-plications. Recently, we have verified that electrostatic beam tilt can provide robust identification8 in less than 900 ms without the hysteresis effects

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Figure 9. Pattern noise in CD-SEM measurements can compromise performance of FEOL APC loops, resulting in

lower yield and performance entitlements. Replacing SEMs with SCD systems provides more spatial

averaging and more yield-relevant correction of gate CD and L-cap errors.

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and long delays associated with elec-tromagnetic deflection (Figure 11). Second, the development of array- mode metrology for BEOL applica-tions can greatly reduce the contri-bution of pattern noise to error in APC adjustments. The CD-SEM measures several lines within its image field and reports mean and standard deviation statistics. These same statistics are now a reliable means for setting design margins in DFM strategies. Combined with beam tilt, array-mode measurements can be virtually flier-free, even when the SEM image field is located deep inside an array of lines and spaces.

Accurate simulation-based DFM optimizationAccurate printability simulation is essential for DFM. The PROLITH simulator can have up to a ten-fold accuracy advantage relative to other simulators and can be calibrated for DFM using either array-mode CD-SEM or SCD metrology. Two unbiased metrics for ac-curacy are the Kintner Image Intensity Test and the Steele Image Placement Test, some results of which are shown in Figure 12. High levels of accuracy are critical to the generation of multiple simulated measurements used to create overlapping focus-exposure windows. Such process windows enable back-end designers to modify layouts for maximum process robustness, device performance, and functional yield. For DFM applications, the natural extension of this technol-ogy is the application of reticle and wafer simulation to the inspection of integrated circuit databases in a supercomputing environment9.

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Figure 10. CD-SEMs can characterize and monitor LWR and LER for DFM applications. Line-width roughness

varies by resist type and top coat uniformity, but not by electron dose. If current levels of LWR are not reduced,

device yield will trend to zero at the 32 nm technology node.

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Figure 11. Incorrect line/space identification in CD-SEM measurements can affect APC performance, yield, and

rework in the BEOL. Electrostatic beam tilt provides robust identification, enabling array metrology and the strong

spatial averaging required for BEOL APC applications.

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Conclusions and recommendationsIn this work, we have shown how design margins and process control performance can be reduced as a result of hidden process error and how this error can be parsed into unobservable, unsampled, unmod-eled, and uncorrectable components. We have applied four new process control technologies to reduce hid-den systematic process error. These technologies can provide accurate feedback of process metrics to enable conjoint DFM and APC strategies at

the 65 nm node and beyond. We con-tend that manufacturing economic considerations will force a trade-off between measurement cost and yield loss that favors greater expenditure on process control, particularly on those technologies that enable APC and DFM.

In summary, we have introduced the following concepts:

• A concept of 193 nm immersion lithography extending through the 32 nm technology node,

• A concept of conjoint DFM and APC strategies that would rely on accurate feedback of process metrics to enable larger process yield win-dows and better centering of the process within those yield windows,

• A concept of predictive yield mod-els for CD and overlay control that can be pinned to actual factory data and can include the yield limiting effects of hidden systematic error,

• A concept for parsing hidden sys-tematic error into unobservable,

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Figure 12. Accurate printability simulation is essential for DFM. As shown above, the PROLITH simulator has up to a ten-fold accuracy advantage and can be calibrated

using CD-SEM or SCD metrology. Multiple simulated measurements are used to create overlapping process windows that enable designers to modify layouts for maximum

process robustness, device performance, and functional yield.

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unsampled, unmodeled, and un-correctable components,

• And, finally, a concept for de-velopment of technologies such as grating-based overlay, ellip-sometry-based profile metrology, array-based CD SEM metrology, and calibrated simulators to provide accurate process metrics for 65 nm technology and beyond.

Acknowledgements The authors would like to thank Chris Mack, David Tien, Amir Azordegan, Chris Sallee, and Matt Hankinson, all of KLA-Tencor Corporation, for valuable discussion.

References 1. K. Monahan, “Microeconomics of

Process Control in Semiconductor Manufacturing”, Proc. of SPIE, Vol. 5043, pp. 57-71, February 2003.

2. K. Monahan, “Microeconomics of Yield Learning in Semiconductor Manufacturing”, Proc. of SPIE, Vol. 5043, pp. 41-56, February 2003.

3. K. Monahan, “Chairman’s Introduction to the ISSM 2003 Cost and Performance Workshop”, ISSM 2003, September 29, San Jose, California.

4. K. Monahan, “Microeconomics of Process Control in Semiconductor Manufacturing,” Proc. of SPIE, Vol. 5043, pp. 57-71, February 2003.

5. L. Lecarpentier, V. Vachellerie, A. Feneyrou, P. Thony, S. Guillot, E. Kassel, Y. Avrahamov, C. Huang, F. Felten, M. Polli, “Overlay Measure-ment Accuracy Verification using CD-SEM and Application to the Quanti-fication of WIS Cause by BARC”, Proc. of SPIE, Vol. 5257-172, March, 2005.

6. W. Lin, S. Liao, R. Tsai, M. Yeh, C. Hsieh, C. Yu, B. S. Lin, T. Dziura,

“Feasibility of Improving CDSEM-based APC System for Exposure Tools by Spectroscopic Ellipsometry-based APC System”, Proc. of SPIE, Vol. 5755-17, March 2005.

7. P. Leunissen, G. Lorusso, T. Dibiase, “Full Spectral Analysis of Line-edge Roughness“, Proc. of SPIE, Vol. 5752-49, March, 2005.

8. E. Solecky, C. Chin, G. Qu, H. Yang, A. Azordegan, “Automated CD SEM Tilt: Ready for Prime Time, a Fast In-line Methodology for Differentiating Lines and Spaces Using Tilted Images for Process Control”, Proc. of SPIE, Vol. 5752-73, March, 2005.

9. J. Tirapu-Azpiroz, J. Culp, S. Man-sfield, W. Howard, Y. Xiong, C. Mack, R. Shi, G. Verma, W. Volk, H. Lehon, Y. Deng, “Inspection of Integrated Circuit Databases through Reticle and Wafer Simulation: an Integrated Approach to Design for Manufacturability”, Proc. of SPIE, Vol. 5756-07, March, 2005.

This article is based on a paper that was previously published in the SPIE Proceedings 5756-7.

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