Face-up semiconductor chip assembly (US patent 5852326)

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    United StateS Patent [19]Khandros et al.

    IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIUS005852326A[11] Patent Number: 5,852,326[45] Date of Patent: Dec. 22, 1998

    [54] FACE-UP SEMICONDUCTOR CHIPASSEMBLY[75] Inventors: Igor Y. Khandros, Orinda; Thomas H.Distefano, Monte Sereno, both of Calif.[73] Assignee: Tessera, Inc., San Jose, Calif.[21] Appl. No.: 110,527[22] Filed: Jnl. 6, 1998

    5,148,2655,173,7635,233,2215,347,1595,489,7495,491,3025,619,0175,679,9775,685,885

    9/1992 Khandors et al..12/1992 Cipolla et al..8/1993 Bregmann et al..9/1994 Khandros et al..2/1996 Distefano et al..2/1996 Distafano et al..4/1997 Distefano et al..10/1997 Khandros et al..11/1997 Khandros et al..

    Related U.S.Application Data

    [56] References CitedU.S. PATENT DOCUMENTS

    4,878,098 10/1989 Saito et al..

    [63] Continuation of Ser. No. 861,280,May 21, 1997,which is acontinuation of Ser. No. 319,966, Oct. 7, 1994, Pat. No.5,685,885, which is a continuation of Ser. No. 30,194,Apr.28, 1993,Pat. No. 5,679,977,which is a continuation-in-partof Ser. No. 586,758, Sep. 24, 1990, Pat. No. 5,148,266, anda continuation of Ser. No. 765,928, Sep. 24, 1991,Pat. No.5,347,159,which is a continuation-in-part of Ser. No. 673,020, Mar. 21, 1991, Pat. No. 5,148,265, and Ser. No.586,758.

    [51] Int. Cl.'............................01L 23/48; H01L 23/52[52] U.S.Cl............................57/692; 257/701; 257/690[58] Field of Search .....................................57/692, 701,257/702, 703, 698, 693, 690, 786, 784

    [57] ABSTRACTA semiconductor assembly having contacts on a peripheralregion of the top surface of a chip and a backing elementoverlying the bottom surface of the chip. The backingelement has terminals such that at least some of the terminalsoverlie the bottom surface of the chip. Leads includingbonding wires extending alongside the edges of the chipconnect the contacts and the terminals. The terminals of theassembly are movable with respect to the chip.

    29 Claims, 19 Drawing Sheets

    Pvimavy Examinev~ahshid SaadatAttorney, Agent, or Firm~rner, David, Littenberg,Krumholz & Mentlik

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    U.S. Patent Dec. 22, 1998 Sheet 1 of 19 5,S52,326

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    U.S. Patent Dec. 22, 1998 Sheet 2 of 19 5,S52,326

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    U.S. Patent Dec. 22, 1998 Sheet 9 of 19 5,S52,326

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    5,852,326FACE-UP SEMICONDUCTOR CHIPASSEMBLYCROSS-REFERENCE TO RELATEDAPPLICATIONS

    This is a continuation of U.S. patent application Ser. No.08/861,280, filed on May 21, 1997 which is in turn acontinuation of U.S. patent application Ser. No. 08/319,966,filed on Oct. 7, 1994, now U.S. Pat. No. 5,685,885. U.S.patent application Ser. No. 08/319,966 is a continuation ofU.S. patent application Ser. No. 08/030,194, filed Apr. 28,1993 as the national phase of International ApplicationPCT/US91/06920 filed Sep. 24, 1991.Said Ser. No. 08/030,194 application, now U.S. Pat. No. 5,679,977,was in turn acontinuation of U.S. patent application Ser. No. 07/765,928,filed Sep. 24, 1991,now U.S. Pat. No. 5,347,159.Said U.S.patent application Ser. No. 07/765,928 was a continuation inpart of U.S. patent application Ser. No. 07/673,020, filedMar. 21, 1991, now U.S. Pat. No. 5,148,265 and said U.S.patent application Ser. No. 07/765,928 was a continuation inpart of U.S. patent application Ser. No. 07/586,758, filedSep. 24, 1990,now U.S.Pat. No. 5,148,266. Said U.S.patentapplication Ser. No. 08/030,194 is also a continuation in partof said U.S. patent application Ser. Nos. 07/586,758 and07/673,020.

    BACKGROUND OF THE INVENTIONThe present invention relates to the art of electronic

    packaging, and more specifically to assemblies incorporat-ing semiconductor chips and to methods and componentsuseful in making such assemblies.

    TECHNICAL FIELDModern electronic devices utilize semiconductor chips,commonly referred to as "integrated circuits" which incor-porate numerous electronic elements. These chips are

    mounted on substrates which physically support the chipsand electrically interconnect each chip with other elementsof the circuit. The substrate may be a part of a discrete chippackage used to hold a single chip and equipped withterminals for interconnection to external circuit elements.Such substrates may be secured to an external circuit boardor chassis. Alternatively, in a so-called "hybrid circuit" oneor more chips are mounted directly to a substrate forming acircuit panel arranged to interconnect the chips and the othercircuit elements mounted to the substrate. In either case, thechip must be securely held on the substrate and must beprovided with reliable electrical interconnection to the sub-strate. The interconnection between the chip itself and itssupporting substrate is commonly referred to as "first level"assembly or chip interconnection, as distinguished from theinterconnection between the substrate and the larger ele-ments of the circuit, commonly referred to as a "secondlevel" interconnection.The structures utilized to provide the first level connectionbetween the chip and the substrate must accommodate all of

    the required electrical interconnections to the chip. Thenumber of connections to external circuit elements, com-monly referred to as "input-output" or "I/O" connections, isdetermined by the structure and function of the chip.Advanced chips capable of performing numerous functionsmay require substantial numbers of I/O connections.

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    with smaller distances between chips provide smaller signaltransmission delays and hence permit faster operation of thedevise.First level interconnection structures connecting a chip toa substrate ordinarily are subject to substantial strain causedby thermal cycling as temperatures within the device changeduring operation. The electrical power dissipated within thechip tends to heat the chip and substrate, so that thetemperatures of the chip and substrate rise each time thedevice is turned on and fall each time the device is turnedolf. As the chip and the substrate ordinarily are formed fromdilferent materials having dilferent coefficients of thermalexpansion, the chip and substrate ordinarily expand andcontract by dilferent amounts. This causes the electricalcontacts on the chip to move relative to the electrical contactpads on the substrate as the temperature of the chip andsubstrate changes. This relative movement deforms theelectrical interconnections between the chip and substrateand places them under mechanical stress. These stresses areapplied repeatedly with repeated operation of the device, andcan cause breakage of the electrical interconnections. Ther-mal cycling stresses may occur even where the chip andsubstrate are formed from like materials having similarcoefficients of thermal expansion, because the temperatureof the chip may increase more rapidly than the temperatureof the substrate when power is first applied to the chip.The cost of the chip and substrate assembly is also a majorconcern. All these concerns, taken together, present a for-

    midable engineering challenge. Various attempts have beenmade heretofore to provide primary interconnection struc-tures and methods to meet these concerns, but none of theseis truly satisfactory in every respect. At present, the mostwidely utilized primary interconnection methods are wirebanding, tape automated bonding or "TAB" and flip-chipbonding.In wire bonding, the substrate has a top surface with a

    plurality of electrically conductive contact pads or landsdisposed in a ring-like pattern, The chip is secured to the topsurface of the substrate at the center of the ring-like pattern,so that the chip is surrounded by the contact pads on thesubstrate. The chip is mounted in a face-up disposition, withthe back surface of the chip confronting the top surface ofthe substrate and with the front surface of the chip facingupwardly, away from the substrate, so that electrical contactson the front surface are exposed. Fine wires are connectedbetween the contacts on the front face of the chip and thecontact pads on the top surface of the substrate. These wiresextend outwardly from the chip to the surrounding contactpads on the substrate. In the wire bonded assemblies, thearea of the substrate occupied by the chip, the wires and thecontact pads of the substrate is substantially greater than thesurface area of the chip itself.In tape automated bonding, a polymer tape is providedwith thin layers of metallic material forming conductors on

    a first surface of the tape. These conductors are arrangedgenerally in a ring-like pattern and extend generally radially,towards and away from the center of the ring-like pattern.The chip is placed on the tape in a face down arrangement,with contacts on the front surface of the chip confronting theconductors on the first surface of the tape. The contacts onthe chip are bonded to the conductors on the tape. Ordinarily,numerous patterns of conductors are arranged along thelength of the tape and one chip is bonded to each of these

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    5,852,326diately adjacent portions of the pattern are encapsulated andthe outermost portions of the metallic conductors aresecured to additional leads and to the ultimate substrate.Tape automated bonding can provide the assembly withgood resistance to thermal stresses, because the thin metallicleads on the tape surface are quite flexible, and will bendreadily upon expansion of the chip without imposing sig-nificant stresses at the juncture between the lead and thecontact on the chip. However, because the leads utilized intape automated bonding extend outwardly in a radial, "fanout" pattern from the chip, the assembly is much larger thanthe chip itself.In flip-chip bonding, contacts on the front surface of the

    chip are provided with bumps of solder. The substrate hascontact pads arranged in an array corresponding to the arrayof contacts on the chip. The chip, with the solder bumps, isinverted so that its front surface faces toward the top surfaceof the substrate, with each contact and solder bump on thechip being positioned on the appropriate contact pad of thesubstrate. The assembly is then heated so as to liquify thesolder and bond each contact on the chip to the confrontingcontact pad of the substrate. Because the flip-chip arrange-ment does not require leads arranged in a fan-out pattern, itprovides a compact assembly. The area of the substrateoccupied by the contact pads is approximately the same sizeas the chip itself. Moreover, the flip-chip bonding approachis not limited to contacts on the periphery of the chip. Rather,the contacts on the chip may be arranged in a so-called "areaarray" covering substantially the entire front face of the chip.Flip-chip bonding therefore is well suited to use with chipshaving large numbers of I/O contacts. However, assembliesmade by flip-chip bonding are quite susceptible to thermalstresses. The solder interconnections are relativelyinflexible, and may be subjected to very high stress upondilferential expansion of the chip and substrate. Thesedilficulties are particularly pronounced with relatively largechips. Moreover, it is dilficult to test and operate or "burn-in" chips having an area array of contacts before attachingthe chip to the substrate. Additionally, flip-chip bondingordinarily requires that the contacts on the chip be arrangedin an area array to provide adequate spacing for the solderbumps. Flip-chip bonding normally cannot be applied tochips originally designed for wire bonding or tape auto-mated bonding, and having rows of closely spaced contactson the periphery of the chip.

    SUMMARY OF THE INVENTIONOne aspect of the present invention provides a semicon-ductor chip assembly. An assembly according to this aspectof the invention typically includes a semiconductor chip

    having a plurality of surfaces and having contacts on at leastone of said surfaces. The assembly further includes asheetlike, preferably flexible, element having terminalsthereon, the terminals being electrically connected to thecontacts on the chip. Assemblies according to this aspect ofthe invention are characterized in that the sheetlike elementand at least some of said terminals overly one surface of saidchip, said terminals are movable with respect to said chipand in that resilient means for permitting displacement of theterminals toward the chip, but resisting such displacementare provided. Most preferably, a compliant layer is disposedbetween said terminals and said chip so that said compliantlayer will be compressed upon movement of said terminals

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    sheetlike element and terminals may overlie said frontsurface of the chip. Alternatively, the sheetlike element andsaid terminals may overlie the rear, or bottom surface of saidchip. The terminals on the sheetlike element can be con-nected to contact pads on a substrate, as by solder bonding.Because the terminals, and hence the contact pads on thesubstrate overlie the chip front or back surface, the assemblyis compact. The ability of the terminals to move with respectto the chip in directions parallel to the chip surfaces providescompensation for dilferential thermal expansion of the chipand substrate.The ability to accumulate movement of the terminalstowards the face of the chip greatly facilitates temporary

    engagement of the terminals by test equipment and hencefacilitates testing and "burn-in" of the assembly before thesame is mounted to a substrate. According to a further aspectof the present invention the compliant layer includes massesof compliant material interspersed with holes. Desirably,each such mass is aligned with one of the terminals.A further aspect of the invention provides method ofmaking a semiconductor chip assembly including the step ofassembling a flexible, sheetlike element having terminalsthereon to a seminconductor chip and connecting terminalson said sheetlike element to contacts on said chip. Methodsaccording to this aspect of the invention desirably arecharacterized in that the assembling step is conducted so thatsaid terminals on said sheetlike element overlie a surface of

    the chip and in that a compliant layer is disposed betweensaid chip and said terminals. Most preferably, these methodsare further characterized by the step of testing the chip byestablishing temporary electrical contact between a pluralityof test probes and said terminals and utilizing said temporaryelectrical contact to actuate said chip. The compliant layerpermits displacement of at least some of said central termi-nals toward said chip during the step of establishing tem-porary electrical contact. The step of establishing temporaryelectrical contact preferably includes the step of simulta-neously establishing temporary contact between a pluralityof terminals and a plurality of test probes rigidly connectedto a test fixture.Further aspects of the invention provide components for

    assembly to a semiconductor chip including a flexible shee-tlike element having terminals thereon, characterized by acompliant layer underlying said terminals. The compliantlayer preferably includes masses of a low modulus materialand holes interspersed with said masses of low modulusmaterial, said masses of said low modulus material beingaligned with said terminals, said holes in said compliantlayer being out of alignment with said terminals.A chip assembly according to a further aspect of theinvention includes a semiconductor chip having a frontsurface with a plurality of contacts disposed in a pattern onthe front surface. The pattern of contacts on the front surfaceencompasses an area, referred to herein as the "contactpattern area" on the front surface. The chip assembly accord-ing to this aspect of the invention also includes a sheetlikedielectric element, referred to herein as "interposer", over-lying the front surface of the chip. The interposer has a firstsurface facing toward the chip and a second surface facingaway from the chip. An area of the interposer overlies thecontact pattern area of the chip. The interposer has aperturesextending through it, from the first surface to the secondsurface. The interposer also has a plurality of electrically

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    5,852,326pattern area on the chip. Each such terminal is associatedwith one contact on the chip.The assembly also includes flexible, electrically conduc-tive leads. The leads preferably extend through the apertures

    in the interposer. Each such lead has a contact end connectedto the associated contact of the chip and a terminal endconnected to the associated terminal on the second surfaceof the interposer. The leads and the interposer are con-structed and arranged so that the contact ends of the leads aremoveable relative to the terminals at least to the extentrequired to compensate for dilferential thermal expansion ofcomponents. The leads desirably are flexible to permit suchmovement. Most preferably, the interposer itself is flexibleso as to facilitate such movement. The assembly accordingto this aspect of the invention optionally may include acompliant layer as discussed above.The assembly incorporating the chip, interposer, terminals

    and leads may be incorporated in a larger assembly includ-ing a substrate having a top surface facing toward the secondsurface of the interposer.Preferred chip assemblies according to this aspect of thepresent invention are compact and may be utilized withchips having large numbers of input-output connections. The

    terminals on the interposer, and the corresponding contactpads on the substrate, desirably are disposed in areas sub-stantially the same size as the contact pattern area on thechip itself.The flexible leads may be formed integrally with theterminals on the interposer, or else may be separately formed

    fine wires. The leads desirably are curved to provideincreased flexibility. The interposer desirably is a thin,flexible sheet of a polymeric material such as polymide, afluoropolymer, a thermoplastic polymer or an elastomer. Inthis arrangement, flexing of the interposer facilitates move-ment of the contact ends of the leads relative to the terminalsand thus contributes to the ability of the assembly towithstand thermal cycling. The assembly may also include acompliant dielectric encapsulant having a low elasticmodulus, such as an elastomeric encapsulant, covering theflexible leads in whole or in part. The encapsulant may beprovided in the form of a layer, with holes in the encapsulantlayer aligned with the terminals on the second surface of theinterposer. The bonds between the terminals and the contactpads of the substrate extend through these holes. The encap-sulant protects the relatively delicate leads during handlingand during service, but does not prevent flexing of the leadsor the absorption by the leads of relative motion of the chipand substrate during thermal expansion.A chip assembly according to yet another aspect of thepresent invention incorporates a chip having a front surfaceincluding a central region and a peripheral region surround-

    ing the central region, the chip having a plurality of periph-eral contacts disposed in the peripheral region of the frontsurface. The assembly preferably further includes a sheet-like dielectric interposer overlying the central region of thechip front surface. The interposer has a first surface facingdownwardly toward the chip and a second surface facingupwardly, away from the chip. The interposer also has edgesdisposed inwardly of the peripheral contacts. For example,the interposer may overly only the central portion of the chipfront surface. A plurality of central terminals are disposed onthe interposer and overly the central region of the chip front

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    contact lead thus has a central terminal end overlying theinterposer and connected to one of the central terminals anda contact end projecting outwardly beyond one of the edgesof the interposer and connected to one of the peripheralcontacts. Each peripheral contact lead extends inwardlyfrom one of the peripheral contacts to one of the centralterminals on the interposer. The peripheral contact leads andpreferably the interposer as well are at least partially flexibleso that the central terminals are movable with respect toperipheral contacts to accommodate movement caused bydilferential thermal expansion. Here again, the assemblymay optionally include a compliant layer as discussedabove. Desirably, the peripheral contact leads include bentportions.The peripheral contact leads and central terminals provide

    a "fan-in" arrangement in which the terminals on the inter-poser are disposed inside the region bounded by the periph-eral contacts on the chip. Typically, the peripheral contactson the chip are disposed in one or two rows along each edgeof the chip, in a generally rectangular pattern, so that thecontacts on the chip are close to one another. By contrast, theterminals on the interposer may be substantially evenlydisposed over the second surface of the interposer. Thecentral terminals may be disposed in a so-called "areaarray". Accordingly, the distance between adjacent terminalsmay be substantially greater than the distance betweenadjacent contacts on the chip. The distances between adja-cent terminals on the interposer may be large enough toaccommodate solder bonding and similar processes whichrequire substantial distances between adjacent bonds.Some or all of the peripheral contact leads may haveoutward extensions projecting outwardly beyond the periph-eral contacts of the chip. The assembly may include secure-

    ment means for holding these outward extensions. Forexample, one or more securement elements may be disposedoutwardly of the peripheral contacts, and each such secure-ment element may be physically connected to a plurality ofthe outward extensions on the peripheral contact leads. Eachsuch securement element may be a generally planar strip ofdielectric material having an inboard edge extending gen-erally parallel to one of the edges of the interposer so thateach pair of parallel edges define an elongated slot betweeneach such securement element and the interposer, and eachperipheral contact lead may extend across one of these slots.In this arrangement, the peripheral contacts of the chip maybe disposed in alignment with the slots between the secure-ment elements and the interposer. The securement elementmay be physically connected to the interposer, as by bridgeelements extending between the securement elements andthe interposer at spaced-apart locations around the peripheryof the chip front surface. The securement elements, bridgeelements and interposer may be formed integrally with oneanother as a single, sheet-like unit. The securement elementsprovide physical reenforcement to the peripheral contactleads during the manufacturing operations and in service.Additional terminals, referred to herein as "outside"terminals, may be disposed on the securement elements, andmay be connected to some of the peripheral contacts on thechip by outside terminal leads extending across the slots, theinboard ends of the outside terminal leads being secured tothe interposer so that the slot and interposer cooperativelyprovide reinforcement to the outside terminal leads as well.These assemblies may be made by methods which include

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    5,852,326chip. When the dielectric interposer is disposed on the chip,a first surface of the interposer faces downwardly toward thechip and a second surface of the interposer faces upwardlyaway from the chip, and a plurality of central terminals onthe interposer overly the central region of the chip frontsurface. The method further includes the step of connectinga plurality of peripheral contact leads between at least someof the peripheral contacts of the chip and at least some of thecentral terminals on the interposer, so that each such periph-eral contact lead extends inwardly from one of the peripheralcontacts an the chip to one of the central terminals on theinterposer. The method may further include the step ofassembling a substrate having a plurality of contact pads tobe assembled interposer and chip and connecting each of thecentral terminals on the interposer to one of the contact padson the substrate.The interposer may have prefabricated leads mountedthereon and connected to the central terminals before the

    interposer is assembled to the chip. In this case, the prefab-ricated contact leads are positioned on the chip when theinterposer is assembled to the chip. Such prefabricatedcontact leads may be electrically connected to the contactsof the chip by thermocompression bonding or similar pro-cesses. Alternatively, the peripheral contact leads may beformed after the interposer is applied to the chip, as in awire-bonding step in which a fine wire is dispensed andformed into a lead connecting the contact and terminal.Preferably, securement elements are provided as discussedabove with reference to the chip assembly, and the secure-ment elements are connected to the interposer before theinterposer is placed on the chip. In this case, the securementelements may support the prefabricated leads during the stepof placing the interposer on the chip.A semiconductor chip assembly in accordance with yetanother aspect of the invention includes a semiconductor

    chip having oppositely facing front and rear surfaces withedges extending between these surfaces, the chip havingcontacts on the front surface. The assembly further includesa generally sheet-like element referred to herein as "backingelement" underlying the chip, the backing element having atop surface facing toward the chip and a bottom surfacefacing away from the chip. A central region of the backingelement is aligned with the chip. The backing element isprovided with terminals. At least some, and preferably all ofthe terminals on the backing element are disposed in thecentral region, so that the terminals underlie the bottomsurface of the chip. The assembly in accordance with thisaspect of the present invention further includes electricallyconductive leads interconnecting the contacts on the chipfront surface with the terminals on the backing element,these leads extending alongside the edges of the chip.Preferably, the backing element and the leads are flexible sothat the terminals on the backing element are moveable withrespect to the chip. Thus, the terminals desirably are move-able with respect to the contacts on the front surface of thechip in directions parallel to the plane of the chip top andbottom surfaces. The backing element and leads provide forconnection to the chip at the back surface, so that the chipcan be mounted in face-up disposition on a substrate.However, because the terminals on the backing element aredisposed in the central region and aligned with the chipitself, the connections to the substrate can be made in thearea beneath the chip. Therefore, the assembly need not be

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    between the chip and substrate. Desirably, the terminals onthe backing elements are also moveable relative to the chipin directions towards the bottom surface of the chip asdiscussed above, and the assembly may include resilientmeans for permitting movement of the terminals towards thebottom surface but resisting such movement. For example,the assembly may incorporate a layer of a compliant mate-rial disposed between the chip rear surface and the terminals.Most desirably, the assembly includes at least one gen-

    erally sheet-like flap connected to the backing element. Eachsuch flap extends upwardly, towards the front surface of thechip and away from the backing element alongside one edgeof the chip. Each of the aforementioned leads desirablyincludes a flap portion extending along one of these flaps.The flaps may be formed integrally with the backing ele-ment. Desirably, both of the flaps and the backing elementinclude electrically conductive layers and a dielectric layerdisposed between the electrically conductive layers and theleads so as to provide a controlled impedance in the leads.Assemblies of this type are especially well suited to use withchips having contacts arranged in rows adjacent the periph-ery of the chip front surface peripherate. Desirably, each flapextends to the vicinity of at least one row of contacts. Theflap portions of the leads on each such flap are connected tothe adjacent row of contacts. Such connection may be madefor instance by wire bonding or by direct connectionsbetween the flap portions of the leads and the contacts on thechip. Even where wire bonding is employed, however, thewires extending between the chip contacts and the flapportions of the leads are short. Such short wire bonds can bereadily applied and have relatively low inductance.Most preferably, the chip assembly includes one or more

    support elements disposed between the flaps and the edgesof the chip. The support elements may cooperatively con-stitute a ring or box surrounding the chip. The box may alsoincorporate a floor element disposed beneath the rear surfaceof the chip, between the rear surface and the backingelement. Where the assembly includes a floor elementunderlying the chip rear surface, the compliant layer may bedisposed between the floor element and the terminals, as, forexample, between the floor element and the backing ele-ment. These arrangements provide for mechanical supportof the flaps and protection of the interconnections. Furtherprotection may be alforded by encapsulating the assembly.Further aspects of the invention provide components

    incorporating subassemblies of the backing element, leadsand support element. Preferably, these components includesupport elements defining a box, and include flaps integralwith the backing element extending upwardly along thesides of the box. The conductors extending along the flapsare prepositioned adjacent the top edges of the box walls. Inmanufacture of the assembly, the chip may be placed withinthe box and the conductors may be joined to the chipterminals.Assemblies as discussed above may be incorporated in alarger assembly with a substrate having contact pads, thecontact pads of the substrate being aligned with the termi-nals on the backing element and connected thereto. Suchconnection may be made for example by masses of electri-cally conductive bonding material disposed between the

    terminals and the contact pads of the substrate.A further aspect of the present invention provides a circuit

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    other, such that each chip assembly other than the bottom-most chip assembly overlies another, immediately subjacentchip assembly. The bottom surface of the backing element ineach such overlying chip assembly faces the second surfaceof the interposer of the immediate subjacent chip assembly.Most preferably, at least some of the inside terminals on thebacking element of each such overlying chip assembly areconnected to the central terminals on the interposer of theimmediately subjacent chip assembly, so that the chips of thevarious chip assemblies are electrically connected to oneanother.Further aspects, features and advantages of the present

    invention will be more readily apparent from the detaileddescription of the preferred embodiments set forth below,taken in conjunction with the accompanying drawings.BRIEF DESCRIPTION OF DRAWINGS

    FIG. 1 is a diagrammatic perspective view of a chipassembly in accordance with one embodiment of the inven-tion.FIG. 2 is a fragmentary sectional view taken along line2in FIG. 1.FIG. 3 is a fragmentary view, on an enlarged scale, of the

    area indicated in FIG. 2.FIG. 4 is a layout diagram depicting the spatial relation-

    ship of certain components in the assembly of FIG. 1.FIGS. 5A and 5B are fragmentary diagrammatic perspec-tive views depicting certain operations, in manufacture of acomponent utilized in the assembly of FIG. 1.Each of FIGS. 6, 7 and 8 is a fragmentary diagrammaticperspective view depicting certain operations in the processof manufacture of the assembly of FIG. 1.FIG. 9 is a fragmentary diagrammatic perspective viewsimilar to FIG. 7 but depicting components and process steps

    in accordance with a further embodiment of the invention.Each of FIGS. 10A through 10E is a fragmentary dia-grammatic perspective view depicting a stage in a furthercomponent fabrication process according to the invention.FIG. 11 is a diagrammatic plan view of a semiconductor

    chip incorporated in one embodiment of the present inven-tion.FIG. 12 is a view similar to FIG. 11 but shoving the chipin conjunction with additional components.FIG. 13 is a fragmentary, partially sectional perspectiveview on an enlarged scale depicting portions of the compo-nents illustrated in FIG. 12.FIG. 14 is a fragmentary, diagrammatic sectional viewdepicting the components shown in FIG. 13 together withadditional components and process equipment.FIG. 15 is a fragmentary, diagrammatic sectional viewdepicting an assembly operation according to a furtherembodiment of the invention.FIG. 16 is a fragmentary, partially sectional diagrammaticperspective view depicting an assembly according to afurther embodiment of the invention.FIG. 17 is a diagrammatic plane view depicting theassembly of FIG. 16.FIG. 18 is a diagrammatic plan view depicting an assem-bly according to yet another embodiment of the invention.FIG. 19 is a fragmentary plan view depicting certaincomponents used in the assembly according to FIGS. 16 and

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    10FIG. 21 is a diagrammatic plan view of a component.FIG. 22 is a fragmentary sectional view on an enlargedscale taken along lines 223 in FIG. 21.FIG. 23 is a diagrammatic perspective view of a furthercomponent used with the components of FIGS. 212.FIG. 24 is a fragmentary sectional view taken along lines244 in FIG. 23.FIG. 25 is a diagrammatic perspective view showing thecomponents of FIGS. 214 at an intermediate stage of an

    assembly process.FIG. 26 is a fragmentary, partially sectional perspectiveview depicting a final assembly incorporating the compo-nents of FIGS. 215.FIG. 27 and 28 are fragmentary, partially sectional per-spective views depicting components in accordance withadditional embodiments of the invention.FIGS. 29 and 30 are diagrammatic sectional views depict-ing still further embodiments.

    DETAILED DESCRIPTION OF THEPREFERRED EMBODIMENTSEach chip assembly in accordance with one embodimentof the present invention includes a rigid substrate 20 having

    a top surface 22 and having contact pads 24 disposed on thetop surface. Substrate 20 is also provided with conductors 26interconnecting certain ones of the contact pads 24. Thecontact pads 24 are arranged in a pattern on the top surfaceof the substrate generally corresponding to the pattern ofconnections to devices, such as semiconductor chips 28 and30 and discrete components 32 mounted on the substrate.Substrate 20 also has external connections such as pins 34.The conductors 26 are arranged to interconnect the variouscontact pads 24 in the desired patterns so as to interconnectchips 28 and 30 when the same are mounted to the substrateand also to connect these chips to the discrete components32 and to the external connectors 34 in the appropriatemanner for functioning of the particular circuit. Althoughonly a few contact pads 24, conductors 26 and externalconnections 34 are illustrated in FIG. 1, the substrate 20 mayhave an unlimited number of contact pads 24, conductors 26and external connections 34.Hundreds or thousands of theseelements typically are provided in each substrate.Chip 28 has a generally planar rear face 36 and a generallyplanar front face 38 with electrical contacts 40 (FIG. 2)disposed thereon. The electrical contacts 40 are electricallyconnected to the internal electronic components (not shown)

    of chip 28. Chip 28 is mounted on substrate 20 in afront-face-down orientation, with the front face 38 of thechip facing toward the top of face 22 of the substrate. Aflexible, sheetlike dielectric interposer 42 is disposedbetween the chip and the substrate. Interposer 42 has a firstgenerally planar face 44 facing toward chip 28 and a secondgenerally planar face 46 facing in the opposite direction,away from chip 28. Interposer 42 may incorporate one ormore layers. Preferably, the interposer includes a compliant,compressible layer as further discussed below. Interposer 42has a plurality of terminals 48 on its second face 46. Eachsuch terminal is associated with one of the contacts 40 onchip 28 and connected to such contact by a flexible lead 50.Each terminal 48 is also associated with one contact pad 24on substrate 20, and each terminal is bonded to the associ-ated contact pad by a mass 52 of electrically conductive

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    5,852,326 12Interposer 42 has apertures 54 extending through it, fromits first surface 44 to its second face of 46. Each aperture isaligned with one contact 40 on chip 2II. Each terminal 4II isdisposed adjacent one of the apertures 54. The lead 50associated with each terminal has a contact end 56 disposed

    within the associated aperture 54 and connected to theassociated contact 40 on the chip. Each lead 50 also has aterminal end 5II connected to the associated terminal 4II. Inthe structure of FIG. 2, the leads 50 are formed integrallywith the terminals 4II so that the terminal end 5II of each leadmerges with the associated terminal 4II.As best seen in FIG.2, each lead 50 is curved between its contact end 56 and itsterminal end 5II. The curvature is in the direction perpen-dicular to the faces 46 and 4II of the interposer. Anelastomeric, dielectric encapsulant 60 is disposed in aper-tures 54 so that the encapsulant covers the contact ends 56of leads 50 and hence covers the junctures of the leads withthe contacts 40.The contact end 56 of each lead 50 is moveable relative

    to the associated terminal 4II. As best seen in FIG. 3, thecontact end 56a of lead 50a can be displaced from itsnormal, undeformed position (shown in solid lines) in thedirections parallel to the faces 44 and 46 of interposer 42 andparallel to the front face 3II of chip 2II. For example, thecontact end 56a may be displaced to the position indicatedin broken lines at 56a'. This displacement is permitted by theflexibility of the lead 50 and by buckling and wrinkling ofinterposer 42. Encapsulant 60 is compliant, and does notsubstantially resist flexing of leads 50 and buckling andwrinkling of interposer 42. The displacement illustrated inFIG. 3, from the normal undisplaced position 56a to thedisplaced position 56a'laces the lead 50 in compression.That is, the terminal end 56a moves generally toward theassociated terminal 4II in moving from position 56a toposition 56a'. Movement in this direction is particularly wellaccommodated by buckling of the lead 50. The contact endof each lead can also move in other directions, such as in theopposite direction from position 56a away from the associ-ated terminal 4II, and in directions perpendicular to thesedirections, into and out of the plane of the drawing as seenin FIG. 3. Prefabricated leads formed on the interposer maycurved in directions parallel to the face of the interposer andparallel to the plane of the front face of the chip. Thisprovides increased flexibility in the leads. Desirably, thecurved portion of each lead overlies an aperture in theinterposer. Thus, the curved portion of the lead is not bondedto the interposer. This portion of the lead therefore can flexto accommodate relative movement of the contact andterminal without deformation of the interposer.As best seen in FIG. 4, the contacts 40 on chip 2II (eachsymbolized by a dot in FIG. 4) are disposed in a pattern onthe front surface of chip 2II. Contacts 40 cooperativelyencompass a contact pattern area 62 on the front face of chip2II. The boundary of the contact pattern area is illustrated bya broken line B in FIG. 4. The boundary of the contact

    pattern area may be taken as the shortest combination ofimaginary line segments along the front face of the chipwhich cooperatively enclose all of the contacts 40. In theparticular example illustrated in FIG. 4, this boundary isgenerally in the form of a rectangle. Contacts 40 are dis-posed throughout contact pattern area 62, in locations deter-mined by the interior structure of chip 2II. Contact patternarea 62 includes a peripheral region, adjacent the boundary

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    substantially equal spacings throughout the entirety of con-tact pattern area 62. The terminals 4II, each symbolized byan X in FIG. 4, are disposed in a similar pattern on thesecond surface 46 of interposer 42. At least some of termi-nals 40 are disposed in the area of interposer surface 46overlying contact pattern area 62. Terminals 64 encompassa terminal pattern area 66 on the second face 46 of theinterposer. The boundary of terminal pattern area 66 isillustrated in FIG. 4 by the broken line T. The boundary ofthe terminal pattern area may be taken as the shortestcombination of imaginary line segments which would coop-eratively enclose all of the terminals on the second surfaceof the interposer. The geometric center of terminal array area66 desirably is coincident, or approximately coincident, withthe geometric center 64 of the contact array area. Desirably,terminal pattern area 66 is not substantially larger thancontact pattern area 62. That is, the perimeter of the terminalarea preferably is less than about 1.2 times, and mostpreferably about 1.0 times the perimeter of contact patternarea 62. Stated another way, the outermost terminals 4IIdesirably lie within or close to the boundary B of contactarray area 62. The total area encompassed within terminalpattern area 66 desirably is less than about 1.4 times, andmost desirably about 1.0 times the total area encompassedwithin contact pattern area 62. Thus the leads 50 connectingcontacts 4II to terminals 40 do not "fan out", away from thegeometric center 64 the contact pattern area. Typically, themean distance of the terminals 4II from geometric center 64of the contact pattern area, measured in the direction parallelto the surfaces of the chip and interposer, is less than about1.1,and typically about 1.0, times the mean distance of thechip contacts 40 from center 64.The interposer and leads utilized in the structure of FIGS.

    1 may be fabricated by a process as schematically illus-trated in FIGS. 5AB. In this procedure, the terminals 4IIand leads 50 may be deposited on the second surface 46 ofthe sheetlike interposer by conventional printed circuitmanufacturing techniques before formation of apertures 54.Thus, the leads and terminals may be formed either by anadditive process, wherein the metal is deposited in thedesired pattern by plating, or else in a subtractive processwhich begins with a laminate including both the sheetlikeinterposer 42 and a full layer of metal and removes the metalexcept in the areas where the terminals and leads are desired,so as to yield a sheet having the terminals and leads inposition (FIG. 5A). After formation of the terminals andleads, apertures 54 are formed in registration with thecontact ends 56 of the leads 50 (FIG. 5B)by etching throughthe interposer from the first surface 44, or by applyingradiant energy such as laser beam focused at the appropriatespots on the first surface 44.A further method of making a component incorporatingthe interposer, terminals and leads is shown in FIGS.10A10E. In this method, the apertures 54 are formed ininterposer 42, and the aperture interposer is provided with alayer 302 of adhesive on the second surface 46 of theinterposer. A conductive sheet, such as a sheet of copper 304is applied on the first surface of the interposer, so that sheet304 overlies adhesive 302 and so that sheet 304 overlies theapertures 54. A first surface 306 of sheet 304 faces towardsinterposer 42 and confronts the second surface 46 of theinterposer, with the adhesive layer 302 disposed therebetween. A second surface 30II of the conductive sheet faces

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    13 5,852,326 14surface 306 of conductive layer 304 within apertures 54.Desirably, resist 312 is applied by applying a layer of thesecond resist composition to the first surface 44 of interposer42 as illustrated in FIG. 10B.Both resist compositions 310and 312 may be provided as so-called "dry resist" i.e., as afilm of resist composition which can be laminated to theother structures. Resist composition 312 is laminated to thefirst surface 44 of the interposer 42 under pressure so that theresist composition flows into apertures 54 and substantiallyfills these apertures.In the next stage of the process, depicted in FIG. 10C, the

    first resist layer 310 is selectively cured and uncured por-tions are removed so as to leave the cured resist in a patterncorresponding to the desired pattern of conductive materialsin the finished product. Such selective curing and removal ofa resist layer may be accomplished by known photographictechniques. The remaining resist pattern on the secondsurface 30II of the conductive layer 304 includes elongatedlead areas 314 and terminal areas 316 contiguous with thelead areas. At least a part of each lead area 314 overlies oneof the apertures 54 in the interposer, whereas the terminalareas 316 do not overly the apertures. The portion of eachlead area 314 overlying an aperture is smaller than theaperture, so that each lead area overlies only a portion of theassociated aperture 54. Desirably, each lead area 54 pro-trudes lengthwise across the aperture 54, as illustrated inFIG. 10C.The second resist material 312within apertures 54desirably also is cured. As the second resist material may becured in its entirety, and need not be cured selectively in apredetermined pattern, the second resist material may be ofa type which can be cured by exposure to heat or othernonselective curing method. Alternatively, the second resistmaterial 312 may be photographically cured.In the next stage of the process, illustrated in FIG. 10D,the assembly is immersed in an etchant capable of dissolving

    the conductive material in layer 304 so that the etchantcontacts this layer. During the etching procedure, the firstresist in lead area 314 and terminal areas 316 protects thesecond surface 30II of conductive layer 304. The interposer42 protects the first surface 306 of layer 304 in the terminalareas 316 and in those portions of lead areas 314 which donot overly apertures 54. The second resist 312 protects thefirst surface 306 in those portions of lead areas 314 whichoverlie apertures 54. The etchant therefore does not attackthose portions of conductive layer 304 covered by leadportions 314 and terminal portions 316 of the first resistlayer 310.The first resist layer 310 and the second resist 312are then removed by conventional resist decompositionprocesses such as exposure to solvents which attack theresist. This leaves the unattacked portions of conductivelayer 304 as leads 50 and terminals 4II on the second surface46 of interposer 42, with a contact end 56 of each lead 50protruding over the associated aperture 54 and with aterminal end 5II of each lead connected to the associatedterminal 4II.This process can be modified. For example, the adhesive

    layer 302 may be omitted where the conductive layer formsa satisfactory bond to the material of the interposer. Also, thepattern first resist 310 need not be provided by a subtractiveprocess as discussed above but instead may be provided byan additive process, wherein the resist is applied only in theareas to form the pattern, as by silkscreening. Formation ofthe leads 50 and terminal 4II by this type of etching process

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    The assembly of the interposer and terminals and contactsis fabricated in a substantially continuous sheet or strip. Asillustrated in FIG. 6, the interposers may be provided in theform of a continuous tape 70, with plural interposers 42spaced lengthwise along the tape, each such interposerhaving terminals 4II and leads 50 thereon. Tape 70 may bein the form of a single sheet of the material employed for theinterposers 42, or else may include separate pieces of suchmaterial, each constituting one or more interposers, securedto a backing or the like. Tape 70 may have sprocket holes(not shown) or other features such as those commonlyutilized on the tapes for tape automated bonding of semi-conductor chips.In an assembly method according to the invention, tape 70is advanced in a downstream direction (to the right as seenin FIG. 6) and chips 2II are connected to the tape uponassembly of each chip with one interposer 42 and with theassociated terminals and leads. The chips are subsequentlycarried downstream with the tape, through further operations

    as discussed below.As best seen in FIG. 7, each interposer, with the terminals4II and leads 50 thereon, is brought into juxtaposition witha chip 2II, and the chip is aligned with the interposer so thateach aperture 54 is aligned with one contact 40 of the chip.The interposer 42 and chip 2II are brought together, so thatthe first face 44 of the interposer bears on the front face 3IIof the chip, and the contacts are received in the apertures 54of the interposer. The contact end 56 of each lead 50 initiallylies substantially in the plane of the second surface 46 of theinterposer. A tool 74 is advanced into engagement with thecontact end 56 of each lead so as to deform the contact end56 downwardly, into the underlying aperture 54 and towardsthe associated contact 40. Tool 74 may be a substantiallyconventional thermal bonding tool, thermosonic bondingtool, ultrasonic bonding tool, compression bonding tool, orthe like of the types commonly used in tape automatedbonding or wire bonding. By advancing the tool 74 into eachaperture 54, the contact ends of leads are manipulated withinthe apertures and bonded to the contacts 40 on the chip.Although only a single tool 74 is depicted in FIG. 7, thebonding operation may be performed in a multipleoperation, with many or all of the leads 50 being bonded tothe associated contacts at once.After the contacts and leads have been bonded to one

    another, the interposer and the chip are advanced to a furtherstation, where the encapsulant 60 is applied within eachaperture 54. The encapsulant 60 may be applied dropwise,by conventional drop application equipment. As best seen inFIG. II, each drop of encapsulant 60 covers the contact end56 of the associated lead, but leaves the associated contact4II uncovered. The encapsulant protects the relatively deli-cate contact ends 56 of the leads and the relatively delicatejunctures with the terminals 40. Once the encapsulant hasbeen applied, the assembly of the interposer, leads, terminalsand chips is advanced to a testing station. As illustrated inFIG. II, the assembly, including the chip 2II, may be tested.The test may involve connection of the chip, through theterminals 4II, to an external electronic test device (notshown). The test device may be arranged to operate the chipunder power for an appreciable period so as to "burn-in" thechip and detect any latent defects. Typically, numerousconnections should be established to the chip simulta-neously. As illustrated in FIG. II, this may be accomplished

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    15in FIG. II). The probes 76 are mounted to a common fixture(not shown) so that the vertical position of the probesrelative to one another are fixed. This type of "noncompli-ant" probe array is particularly convenient where therequired spacings between probes (the spacings of theterminals 4II) are relatively small. However, non-uniformities in the dimensions of the probes 76 and/or in thedimensions of the terminals 4II or chip 2II may cause one ormore of the probes 76 to engage the associated terminal 4IIbefore the other probes have engaged their terminals.Desirably, interposer 42 is compliant, so that each terminal4II can be displaced slightly by the associated probe 76 in thedirection toward chip 2II. The region of interposer 42beneath each terminal 4II compresses slightly to accommo-date such displacement. This allows all of the probes 76 toengage their associated contacts 4II without imposing exces-sive loading on any one probe. The terminals 4II may belarger than the contacts on the chip, so as to provide arelatively large area for engagement by each contact 76 andthus accommodate a reasonable amount of misalignment ofthe contacts in the directions parallel to the faces of theinterposer. Because each chip can be tested in this fashion,prior to assembly with the substrate, defects in the chips, inthe terminals and leads associated with the interposer and inthe bonds between the leads and the chip contacts can bedetected before the chip is united with the substrate.After the testing operation, the chip and interposer areunited with the substrate. The chip and interposer assemblyis oriented so that the second face of the interposer, and theterminals 4II, face the top surface of the substrate, and eachterminal 4II confronts one contact pad 24 on substrate.Masses of solder are applied between the confronting ter-minals 4II and contact pads 24 and melted in a "solder

    reflow" operation so that the solder forms a solid jointbetween the contact pad and terminal, and so that the soldermasses support the chip and interposer assembly above thesubstrate 20, in the orientation illustrated in FIG. 2. Thesolder application and reflow operation may be performed insubstantially the same way as the solder application andreflow operation of conventional flip-chip bonding. Thus,the masses of solder may initially be applied to the contactpads 24 of the substrate, before the chip and interposerassembly is united with the substrate. Alternatively, thesolder may be applied to the terminals 4II and bonded to thecontact pads 24 in the reflow operation. A flux typically isemployed in the solder reflow operation. Because the soldermasses support the chip and interposer surface assemblyabove the substrate, there is a gap IIO between the interposerand the substrate. Flux residues may be rinsed out of theassembly by passing a rinsing fluid through this gap.In an assembly method according to a further embodimentof the invention, the interposer 42 is not provided with leadsbefore the interposer is united with the chip 2II. Instead,leads 50're applied by bonding separately formed pieces offine wire to the terminals 4II and to the contacts 40 after theinterposer is assembled with the chip. Leads 50're flexible

    and curved, and arranged to deform as discussed above sothat each contact 40, and the associated contact end of thelead 50'an move relative to the associated terminal 4II soas to accommodate thermal expansion. In the embodimentillustrated in FIG. 9, a layer of an adhesive II1 is disposedbetween the first surface of the interposer and the frontsurface of the chip.

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    16the leads 50'. The layer is provided with holes in alignmentwith the terminals 4II. These holes may be formed by etchingthe encapsulant layer by applying this layer in a selectivecoating process such as silk screening or the like or byapplying the encapsulant layer in a selective curing process.Thus, the encapsulant which may be curable by ultravioletor other radiant energy. The encapsulant may be depositedover the entire interposer, and over terminals 4II. Afterapplication of the encapsulant, radiant energy may beapplied selectively, so that the areas of the layer overlyingterminals 4II remain uncured. These layers are then removedby washing or by a relatively mild etching operation, leavingholes in alignment with terminals 4II. Alternatively, theencapsulant layer may be cured non-selectively and thenportions may be removed by applying radiant energy such aslaser light in alignment with terminals 4II. Masses of elec-trically conductive bonding material are deposited withinthese holes in the encapsulant layer. These masses are thenengaged with the contact pads (not shown) of the substrateand heated so that bonding material forms a bond betweeneach terminal 4II and the associated contact pad on thesubstrate, in a manner similar to the solder bonds of theassembly depicted in FIG. 2.A chip may have contacts disposed in a peripheralarrangement, i.e., where all of the contacts are disposedadjacent the periphery of the chip and hence adjacent theperiphery of the contact pattern area. The central zone of thecontact pattern area, adjacent the geometric center of thecontact array, may be devoid of contacts. With such a chip,the terminals on the interposer may be arranged in a "fan in"pattern, i.e., where the mean distance from the geometriccenter of the contact array to the terminals on the interposeris less than the mean distance from this geometric center tothe contacts on the chip. Some of the terminals are disposedon the area of the interposer overlying the central, contact-free zone of the contact pattern area. This arrangement canprovide a substantially uniform distribution of terminalsover an area equal to the contact pattern area. This providesa spacing between adjacent terminals larger than the spacingbetween adjacent contacts. Such an arrangement allowsconnection of chips with peripheral contact arrays to areaarrays of contact pads on the substrate. Thus chips originallyintended for conventional bonding processes such as tapeautomated bonding can be adapted readily and economicallyto substrates having compact contact pad arrays similar tothose used in flip-chip bonding.Chips may be provided in the form of a wafer incorpo-

    rating a plurality of chips, all of the same design or ofdilfering designs. Individual, separate, interposers may bepositioned on the individual chips constituting wafer andthe-interposers may be assembled to the chips as discussedabove. In this operation, the contacts on each chip aresecured to the leads and terminals of each interposer. Afterthe interposers are secured to the chips, and desirably afterthe junctures between the leads of each interposer and thecontacts of each chip are encapsulated, the individual chipsare separated from the wafer and from one another, as bycutting the wafer using conventional wafer severing or"dicing" equipment commonly utilized to sever individualchips without interposers. This procedure yields a pluralityof chip and interposer subassemblies, each of which may besecured to an individual substrate.Alternatively, a wafer incorporating a plurality of chips

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    17after this operation, and desirably after encapsulating theleads, so as to provide individual subassemblies each includ-ing a chip and an interposer.Interposers also may be provided in the form of a sheetincorporating plural interposers such as interposer and atpredetermined relative positions corresponding to the posi-tions of chips on a completed assembly including a sub-strate. Chips may be secured to the individual interposersand the entire assembly of plural chips and the sheet ofplural interposers may be secured to a substrate. Eachinterposer in such an assembly desirably incorporates apattern of terminals and leads as discussed above. Thisvariant of the assembly procedures provides for consolida-tion of plural chips into a larger subassembly before bondingto the substrate.A semiconductor chip II20 used in a further embodimentof the invention has a generally planar front face II22 (theface visible in FIG. 11)having a central region II24 adjacentthe geometric center of the face and a peripheral region II26adjacent the edges II2II bounding face II22. The front orcontact-bearing face II22 of the chip is regarded as definingthe top of the chip. Thus, in specifying directions, thedirection pointing out of front face II22, and away from thechip, i.e., the direction pointing out of the plane of thedrawing towards the viewer in FIG. 11, is the upwardlydirection. The downward direction is the opposite direction.As used in the present disclosure with respect to a semicon-ductor chip assembly, such terms should be understood asbased on this convention, and should not be understood asimplying any particular directions with respect to the ordi-nary gravitational frame of reference. The chip II20 also hasa plurality of peripheral contacts II30 arranged in rows II32,there being one such row adjacent each edge II2II of the chip.The rows II32 do not intersect one another but insteadterminate at appreciable distances from the corners of thechip so that the corners II34 are devoid of peripheral contactsII30. The central region II24 of the chip front surface II22 isalso devoid of contacts. The contacts II30 in each row II32are spaced at very close intervals, typically about 100 toabout 250 micrometers center to center. This center to centerspacing is adequate for wire bonding or tape automatedbonding. This chip configuration is typical of high I/O countchips originally intended for use with wire bonding or tapeautomated bonding systems.In an assembly method according to one embodiment of

    the invention, a sheet-like dielectric interposer II36 isassembled to chip II20. Interposer II36 includes a flexible toplayer II3II (FIG. 13) formed by a thin sheet ofmaterial havinga relatively high elastic modulus and a compliant bottomlayer II40 formed from a material having a relatively lowelastic modulus. The high-modulus material of top layer II3IImay be a polymer such as a polyimide or other thermosetpolymer, a fluoropolymer or a thermoplastic polymer. Thecompliant, low-modulus material of bottom layer II40 maybe an elastomer. Desirably, the low-modulus material haselastic properties (including modulus of elasticity) compa-rable to those of soft rubber, about 20 to 70 Shore Adurometer hardness. Interposer II36 has a first or bottomsurface II42 defined by bottom layer II40 and a second or topsurface II44 defined by top layer II3II. Bottom, compliantlayer II40 includes holes or voids II41 interspersed withmasses II43 of the low-modulus material.Interposer II36 has edges II46 bounding surfaces II42 and

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    18constitute a "area array". The dimensions of interposer II36in the plane of top surface II44 are smaller than the corre-sponding dimensions of chip II20 in the plane of frontsurface II22. The number of central terminals II4II may beapproximately equal to the number of peripheral contactsII30 on the semiconductor chip Nonetheless, the center-to-center linear distance between adjacent ones of centralterminals II4II is substantially greater than the center-to-center distance between adjacent peripheral contacts II30 onthe chip, because the central contacts II4II are substantiallyevenly distributed rather than concentrated in only a fewrows. Each central terminal II4II is aligned with one of themasses II43 of low-modulus material in compliant layer II40,whereas the holes II41 in the complaint layer are out ofalignment with the central terminals II4II. In a variation ofthis embodiment, the holes may be aligned with terminalsII4II. In a further variation, the holes may be continuous withone another whereas the masses of low-modulus materialmay be separate posts or pillars entirely surrounded by suchcontinuous holes.As best seen in FIG. 13, each central terminal II4II isconnected with a partial lead 50 and a bonding terminal II52which are formed integrally with the central terminal. Cen-tral terminals II4II, partial leads 50 and bonding terminalsII52 may be formed from substantially any electricallyconductive material, but preferably are formed from metallicmaterial such as copper and copper alloys, noble metals andnoble metal alloys. These components typically are fabri-cated on the top or second surface II44 of interposer II36 byconventional photolithographic end etching or depositiontechniques. Bonding terminals II52 are arranged in rows 54adjacent the edges II46 of the interposer. As best seen in FIG.12, there are four such rows 54 of bonding terminals, oneadjacent each edge of the interposer.In the assembly method according to this embodiment ofthe invention, the interposer II36 with the preformed termi-nals II4II, partial leads 50 and bonding terminals II52 thereonis positioned on chip II20 so that the first surface II42 of theinterposer faces the front surface II22 of the chip, and so thatthe edges II46 of the interposer are disposed inwardly of therows II32 of peripheral contacts II30 on the chip. Bondingterminals II52 are electrically connected to contacts II30 onthe chip by a conventional wire bonding operation. Thearrangement of the bonding terminals II52 in rows parallel toand adjacent to the rows of peripheral contacts II30 on thechip substantially facilitates the wire bonding process. Thefine, flexible bonding wires II56 applied in the wire bondingoperation merge with the bonding terminals II52 and partialleads 50 on the interposer to form composite leads extendingfrom the peripheral contacts of the chip to the centralterminals on the interposer. As best appreciated with refer-ence to FIG. 13, each such composite lead extends inwardlyfrom one peripheral contact II30 to an associated centralterminal II4II in the central way. Each such composite leadextends across the edge II46 of the interposer.In the next stage of the process, a low elastic modulusdielectric encapsulant or solder masking material such as asilicone rubber or other castable elastomer II5II (FIG. 14) is

    applied over the interposer and chip and over bonding wiresII56. The encapsulant is applied so as to leave holes II60 inalignment with each of the central terminals II4II on theinterposer. This may be accomplished as discussed abovewith reference to the assembly of FIG. 9.At this stage, the

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    19 5,852,326 20can be tested by making temporary electrical connections tothe central terminals II4II. Because the central terminals II4IIare at substantial center-to-center distances, they may bereadily contacted with probes such as the plural probe setII62 schematically illustrated in FIG. 14.Moreover, becausethe bottom layer II40 of the interposer is compliant, eachcentral terminal II4II is displaceable towards and away fromthe front surface II22 of the chip II20. Thus, the bottom layercan be compressed by the tips II64 of the probe set II62. Thisgreatly facilitates making good electrical contact between aplurality of probes and a plurality of central terminals atonce, and hence greatly facilitates electrical testing of thechip and the other components of the assembly. The con-figuration of compliant layer II40 contributes to this action.Each mass II43 of low-modulus material provides backingand support for the aligned terminal II4II. As the tips II64 ofthe test probe set II62 engage the terminals, each mass II43is compressed in the vertical direction and therefore tends tobulge in horizontal directions, parallel to the plane of thechip. Holes II41 provide space for such bulging. Eachterminal II4II can move downwardly toward the chip sub-stantially independently of the other terminals. Compliantlayer II40 need only provide for sulficient downward move-ment of terminals II4II to accommodate tolerances in thecomponents and test equipment by accomodating dilfer-ences in vertical position between adjacent terminals and/ortest probes. Typically, about 0.125mm or less compliance issufflcient. For example, complaint layer II40 may be about0.2 mm thick.Although test probe set II62 is schematically illustrated as

    including only a few tips II64, the test probe set in fact mayinclude a full complement of tips II64, equal in number to thenumber of terminals II4II, so that all of terminals II4II can beengaged simultaneously. The tips of probe set II62 may berigidly mounted to a common support II65. Therefore, thetest probe set may be rugged, reliable and durable. Theparticular shape of tips II64 is not critical. However, tips II64may desirably be formed as small metallic spheres solder-bonded to support II65. Support II65 in turn may be a ceramicbody with appropriate internal leads, similar to a conven-tional semiconductor substrate. Because the test probe setmay make simultaneous connections with all terminals inthe subassembly, and because the test probe set may havedimensions and configuration similar to a real substrate, thetemporary electrical connection made using the test probecan provide a realistic test of the chip and interposersubassembly. In particular, the test probe set need notinvolve long leads which may introduce unwanted induc-tance and/or capitance. Accordingly, the test probe set can beemployed to test and operate the chip at full speed. Becausethe test probe set may be a simple, economical device, manysuch probe sets can be provided in a manufacturing plant, sothat each chip can be tested for a prolonged period.In the next stage of the assembly operation after testing,

    the chip and interposer subassembly is juxtaposed with asubstrate having electrical contact pads thereon. The assem-bly is placed on the substrate so that the central terminalsII4II face toward the electrical contact pads on the substrate,and so that each central terminal II4II is aligned with onecontact pad. Masses of an electrically conductive bondingmaterial such as a solder or an electrically conducted adhe-sive may be disposed between the central terminals and thecontact pads of the substrate. These masses may then be

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    tially the same techniques as are employed in surface mounttechnology for assembly of components on printed circuitboards. Because the central terminals II4II are disposed atsubstantial center-to-center distances, the standard surfacemount techniques can be used without dilficulty. Forexample, a high I/O count can be achieved with 105 mil(25025 micrometer) center-to-center distances. In analternate embodiment, each contact pad on the substrate maybe a microminiature separable connector such as a socket,and a mating separable connector may be provided on eachterminal. For example, each terminal II4II may incorporate aminiature pin adapted to engage such a socket. In this case,the pins would serve as the means for connecting terminalsII4II to the contact pads of the substrate. The encapsulent orsolder mask layer can be provided with metal rings sur-rounding each hole II60 and hence surrounding each termi-nal II4II. Each such ring defines a preselected area which canbe wetted by solder and thus confines the solder of each jointto a preselected area. Also, small studs, balls, or pins may bepositioned in the holes of the solder mask layer in electricalcontact with the terminals II4II, and these studs may besoldered to a substrate.Inasmuch as each peripheral contact II30 on the chip isconnected to one of the central terminals II4II on the

    interposer, and each such central terminal is connected toone of the contact pads on the substrate, each peripheralcontact II30 is connected to one of the contact pads of thesubstrate. The substrate contact pad of course may beconnected to other elements of an electrical circuit throughconventional connections (not shown) incorporated in thesubstrate. For example, substrate may be a circuit board,circuit panel or hybrid circuit substrate incorporating variouselectronic elements in addition to chip II20.The interconnections between the chip and the substrate(between peripheral contacts II30 and contact pads) areaccommodated within the area of the chip itself, i.e.,within

    the area on the substrate occupied by chip II20. Thus, nospace on the surface of the substrate is wasted by a conven-tional "fan-out" pattern of interconnections. Moreover, theassembly is substantially resistant to thermal cycling. Eachof the composite leads connecting one of the chip peripheralcontacts and one of the central terminals II4II on the inter-poser is flexible. Thus, the partial leads 50 (FIG. 13) on theinterposer surface itself preferably are flexible, and the finebonding wires II56 are also flexible. The interposer itself,and particularly the top layer II3II and bottom compliantlayer II40 may be flexible. Accordingly, there can be sub-stantial movement of terminals II4II on the interposer relativeto contacts II30 on the chip in directions parallel to the chipfront surface. Such movement can be accommodated with-out applying substantial forces to the junctions between theleads and the chip contacts. During use of the assembly,dilferential thermal expansion of chip II20 and substrate maycause appreciable displacement of the contact pads on thesubstrate relative to peripheral contacts II30 on the chip.Inasmuch as the central terminals II4II of the interposer arebonded to the contact pads of the substrate by relatively stilfnoncompliant conductive masses, the central terminals willtend to move with the contact pads. However, such move-ment is readily accommodated and does not result in sub-stantial stresses at the bonds between the central terminalsand contact pads.The assembly shown in FIG. 15 has an interposer

    I ' im

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    21 5,852,326 22As prefabricated leads II50're disposed on top layer II3II'fthe interposer, the prefabricated leads cross the edge II46'fthe interposer at an appreciable height above the first orbottom surface II42'f the interposer. The projecting outerportions II54're curved downwardly, toward the first sur-face II42'f the interposer. This curvature desirably isprovided during fabrication of the interposer and leads,before the interposer is assembled to the chip. In theassembly operation, the interposer II36', with the leads

    I 0 ' n dterminals II4II'lready mounted thereon is placed ontochip II20'o that the outer portions II54're in alignment withcontacts II30'f the chip. The curvature of the leads placesthe outer or contact portions II54'n close proximity to chipcontacts II30' tool II55 is then applied to the outer portionsII54'o as to force the outer portions thus forcing leads

    I 4 ' n tengagement with the chip contacts II30'o as to bond theouter portions II54 of leads II50'irectly to the chip contacts.Typically, pressure is applied through tool II55 along withheat and/or ultrasonic energy. This stage of the process mayemploy conventional thermolcompression or ultrasonicbonding techniques commonly used to bond inner leads in atape automated bonding or "TAB" operation. This bondingestablishes a connection between each chip contact II50'ndone of the terminals II4II'n the interposer, without the needfor any intermediate wire bonding operation. Once thecontacts and terminals are connected in this manner, theresulting subassembly can be encapsulated and bonded to asubstrate in substantially the same fashion as discussedabove. As leads II50're flexible, terminals II4II're movablewith respect to contacts II30'o compensate for thermalexpansion.The terminals II4II'nd leads II50'sed in this structurecan be fabricated by photolithigraphic techniques. For

    example, the interposer may initially be fabricated with asolid sheet of copper or other metal covering the secondsurface II44'nd extending beyond edges II46'. These por-tions of the metal sheet extending beyond the edges of theinterposer may be embossed to impact a downward curva-ture. The surface of the metallic layer facing upwardly awayfrom the interposer (facing toward the top of the drawing inFIG. 15) may be covered with a conventional photoresistpattern such that the photoresist covers the areas correspond-ing to the terminals II4II'nd leads II50'. The opposite surfaceof the sheet may be covered with a further photo resist in theareas extending beyond the edges II46'f the interposer. Thesheet may then be exposed to an etching solution so as toremove those areas not covered by the photo resist on the topsurface, i.e., to remove all areas of the metal sheet other thanthe terminals II4II'nd leads II50'. The photo resist may beremoved, leaving interposer with the terminals and leadsthereon. The curvature imparted to the metal sheet byembossing provides the desired downward curvature in theouter portions II54'f the leads. Alternatively, the leads maybe bent after etching, using a forming die. In yet anotherlead-forming method, the dielectric interposer, or one of thegenerally planar dielectric layers constituting the interposermay be provided with features projecting out of the plane ofthe layers, such as bumps or elongated ridges. The leads maybe formed by depositing metal or other conductive materialso that it forms leads extending over the projecting featuresand then removing those portions of the dielectric layer orinterposer constituting the projecting features, as by selec-tively etching the dielectric layer, leaving behind leads

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    selectively etching or otherwise removing conductive mate-rial before etching the dielectric layer.An alternate, generally similar arrangement, includes aninterposer incorporates a flexible top layer similar to the toplayer II3II of the interposer discussed above with reference to

    FIGS. 1114.Terminals and leads are positioned on the firstor bottom surface of this layer, so that the terminals facetowards the chip when the layer is in position on the chip.The interposer may also include a separate compliant under-layer disposed between the top layer and the chip frontsurface, and also disposed beneath terminals i.e., betweenthe terminals and the chip. The compliant layer may bepositioned on the chip surface, before the top layer, andterminals are positioned on the compliant layer. In this case,the compliant layer may incorporate adhesives at its top andbottom surfaces so as to bind the top layer to the chip.Because the compliant layer is soft, the top layer will remainflexible even when bound to the chip through the compliantlayer, and the terminals will still be movable with respect tothe contacts in directional parallel to the face of the chip.Alternatively, the compliant layer may be formed from apartially cured elastomer such as a so-called "B-stage"silicone elastomer. After assembly of the top layer, thispartially cured material may be more fully cured, as byheating it, which causes the elastomer to bond with the toplayer and with the chip surface. In this arrangement, theterminals are disposed beneath the top layer. To provideaccess to the terminals from the second or top surface of theinterposer, the interposer top layer is punctured as applyingradiant energy from a radiant energy source such as a laserin registration with the terminals to thereby form holes inalignment with the terminals. Once the holes have beenformed, the resulting subassembly can be bonded to asubstrate in the same manner as discussed above. Theseholes may be formed before the interposer is connected tothe chip, and indeed may be formed before the terminals arepositioned on the interposer. In a further alternativearrangement, the terminals and leads can be provided on thecompliant layer itself.The assembly illustrated in FIG. 16 is similar to the

    assembly of FIG. 15.However, the outboard portions II354of leads II350 have outward extensions projecting outwardlybeyond chip peripheral contacts II330.These outward exten-sions are secured to a securement element II361.Althoughonly one securement element II361 is visible in FIG. 16, itshould be clearly appreciated that a similar securementelement II361 is provided at each edge of interposer II336 asseen in FIG. 17. Each securement element serves to rein-force and support the outboard portions of the leads, and toprevent undesired bending of the leads in directions parallelto the surfaces of the interposer and chip during assembly.The central terminals II34II and peripheral contact leadsII350 associated with interposer II336 are disposed on thefirst or chip-facing surface II342 of the interposer top layerII33II.As best seen in FIG. 17, the securement elements II361are connected to interposer II336 by bridge elements II363.The bridge elements are disposed at spaced-apart locationsaround the periphery of the interposer. Preferably, theinterposer, securement elements and bridge elements areformed as an integral unit. All of these components may beportions of a unitary sheet of dielectric material. Thus, theinterposer II336, bridge elements II363 and securement ele-ments II361 may all be formed as part of an elongated tape

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    23 5,852,326 24the interposers and chips may be advanced through theprocess by advancing the tape.Bridge elements 8363 are disposed at the corners of theinterposer. The chip 8320 used in this assembly includesfour rows 8332 of peripheral contacts 8330, the rows form-

    ing a generally rectangular pattern. However, the rows ofperipheral contacts stop short of the corners of this rectan-gular pattern, so that the corner regions of the pattern aresubstantially devoid of contacts 8330.Bridge elements 8363overlie these corner regions, and hence do not cover any ofthe contacts 8330.Each securem