Fabricaton Mos My Ppt

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MOS fabrication technology

NMOS PMOS CMOS

N WELL

P WELL

TWIN TUB

SOI

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A relatively thick silicon dioxide layer (5000A), also calledfield oxide, is created on the surface of Substrate

The field oxide is selectively etched to expose the siliconsurface on which the MOS transistor will be created

The surface is covered with a thin, high-quality oxidelayer (25A), which will eventually form the gate oxide ofthe MOS transistor

On top of the thin oxide, a layer of polysilicon(polycrystalline silicon is deposited

After deposition, the polysilicon layer is patternedand etched to form the MOS transistor gates

Si Substrate (P type)

1. N MOS Fabrication

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The thin gate oxide not covered by polysilicon is alsoetched away, which exposes the bare silicon surfaceon which the source and drain junctions are to be

formed

The entire silicon surface is then doped with N typeimpuritie, either through diffusion or ion implantationultimately creating two n-type regions (source anddrain junctions) in the p-type substrate

Once the source and drain regions are completed,the entire surface is again covered with aninsulating layer of silicon dioxide

The insulating oxide layer is then patterned inorder to provide contact windows for the drain andsource junctions

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The surface is covered with evaporatealuminum (5000A) which will form theinterconnects

Finally, the metal layer is patterned and

etched, completing the interconnectionof the MOS transistors on the surface

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3D View of NMOS Transistor3D View of NMOS Transistor

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2. PMOS Fabrication2. PMOS Fabrication

Similar to N mos processOnly difference is that the

Substrate N typeDrain $ Source P type

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Drawbacks of MetalDrawbacks of Metal--gate MOSgate MOS

TransistorsTransistors MetalMetal--gate PMOS transistors cannot maintain thegate PMOS transistors cannot maintain theminimal(+0.5V) threshold variation.minimal(+0.5V) threshold variation.

Excess surface state charges and mobile ionExcess surface state charges and mobile ioncontamination are two main sources of thresholdcontamination are two main sources of thresholdvariation.variation.

Parasitic capacitancesParasitic capacitances CCgsgs andand CCgdgd slow theslow thetransistor because they must be charged andtransistor because they must be charged anddischarged during switching.discharged during switching.

Aluminum is used as gate material which canAluminum is used as gate material which canerode completely causing contact spiking.erode completely causing contact spiking.

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Features of PolysiliconFeatures of Polysilicon--gategate

CMOS ProcessCMOS Process Optimized to form complementary PMOS andOptimized to form complementary PMOS andNMOS transistors on a common substrateNMOS transistors on a common substrate

Can also fabricate some analog circuits withCan also fabricate some analog circuits withslight modificationsslight modifications

Poly silicon gate can withstand the highPoly silicon gate can withstand the hightemperatures used in the diffusion process, sotemperatures used in the diffusion process, sothat the gate can serve as a diffusion mask.that the gate can serve as a diffusion mask.

PolysiliconPolysilicon--gate is doped with phosphorus togate is doped with phosphorus to

minimize mobile ion contamination, resulting inminimize mobile ion contamination, resulting infaster switching speeds and better control offaster switching speeds and better control ofthreshold voltagethreshold voltage

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CMOS Technology depends on using both N-Type and P-Type devices on the same chip.

The two main technologies to do this task are:

P-Well (Will discuss the process steps involved with this

technology) The substrate is N-Type. The N-Channel device is built

into a P-Type well within the parent N-Type substrate.The P-channel device is built directly on the substrate.

N-Well The substrate is P-Type. The N-channel device is built

directly on the substrate, while the P-channel device isbuilt into a N-type well within the parent P-Typesubstrate.

3. Complementary MOS fabrication

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Two more advanced technologies to do this task are: Twin Tub

Both an N-Well and a P-Well are manufacturedon a lightly doped N-type substrate.

Silicon-on-Insulator (SOI) CMOS Process SOI allows the creation of independent,

completely isolated nMOS and pMOStransistors virtually side-by-side on an insulating

substrate.

Complementary MOS fabrication (cont.)

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3.13.1 NN--well Processwell Process

Steps : P -type substrate Oxidation, and mask (MASK 1) to create N-well (4-5Qm deep) N-well doping

N-well acts as substrate for pMOS devices.The two areas are electrically isolated using thick field oxide (and oftenisolation implants [not shown here])

N-well

SiO2

P-type substrate

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3.2 Twin-Tub (Twin-Well) CMOS Process

This technology provides the basis for separate optimization of the nMOS and pMOStransistors, thus making it possible for threshold voltage, body effect and the channel

transconductance of both types of transistors to be tuned independently.Generally, thestarting material is a n+ or p+ substrate, with a lightly doped epitaxial layer on top. This

epitaxial layer provides the actual substrate on which the n-well and the p-well areformed. Since two independent doping steps are performed for the creation of the wellregions, the dopant concentrations can be carefully optimized to produce the desireddevice characteristics. The Twin-Tub process is shown below.

In the conventional p & n-well CMOS process, the doping density of the well region istypically about one order of magnitude higher than the substrate, which, among other

effects, results in unbalanced drain parasitics.The twin-tub process avoids this problem

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TWINTWIN--WELL CMOS ProcessWELL CMOS Process

Lightly doped epi layerComposite layerPhosphorus implant

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Nitride is stripped boron pwell

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Phosphorous glass layer

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Al metallizationdry etchingPlasma-deposited Silicon-nitride layer (sealing/ mech. Protection)

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3.3 Silicon-on-Insulator (SOI) CMOS Process

Rather than using silicon as the substrate material, technologists have sought to use

an insulating substrate to improve process characteristics such as speed and latch-up susceptibility. The SOI CMOS technology allows the creation of independent,completely isolated nMOS and pMOS transistors virtually side-by-side on aninsulating substrate. The main advantages of this technology are the higherintegration density (because of the absence of well regions), complete avoidance ofthe latch-up problem, and lower parasitic capacitances compared to the conventional

p & n-well or twin-tub CMOS processes.A cross-section of nMOS and pMOS devicesusing SOI process is shown below.

The SOI CMOS process is considerably more costly than the standard p & n-well CMOSprocess. Yet the improvements of device performance and the absence of latch-upproblems can justify its use, especially for deep-sub-micron devices.

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Thank you..Thank you..

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Fabricaton Mos My Ppt

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