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Introduction►Purpose

• This course highlights the compatibility between the S08, 8 bit QE, ColdFire V1 32 bit QE devices and reviews the strengths and applications of the 8bit and 32bit processors.

►Objectives • Explain the power management features of the

QE128.Low Power ModesClock GatingInternal Clock Source32KHz OscillatorVoltage RegulatorReal Time Counter

• Learn about clock management• Freescale’s market positioning with ultra-low power

devices• Learn the specifications of the QE128 • Explain how the QE128 can be applied to sample

applications

►Content• 28 pages • 4 questions

►Learning Time• 40 minutes

Welcome to the “QE128 Low Power” course, one of an exciting series of courses offered by Freescale. The Q128 family is an industry leader in ultra-low power technology driven by advances in process technology, design techniques, peripheral features and next generation tools. These advances enable not only energy savings but novel flexibility. It is now possible to switch between an 8 and a 32-bit device with only four mouse clicks, using Freescale code warrior for MCU's version 6.0 or greater.

The majority of the material in this course is applicable to the MC9S08QE128 and the MCF51QE128. Content specific to one or the other device is identified.

This course covers ultra-low power with the QE128. It discusses power management features including low power modes, clock gating, the internal clock source, the 32 kilohertz oscillator, the voltage regulator, and real time counter. It also covers clock management, Freescale positioning with ultra-low power, QE128 general specifications, and some target applications.

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Ultra-low Power with QE128

►QE128 family—an industry leader in ultra-low power• Optimized peripherals enables better power efficiency to extend battery

life• Market contender in comparable 8-bit and 32-bit devices in run current

in low power run mode• Flexibility to choose a combination of low power and high performance

options

The QE128 family is an industry leader in ultra-low power technology. Both devices offer lower power than the best ARM devices on the market to date. It boasts many energy efficient features. New optimized peripherals enable better power efficiency to help extend battery life. The QE128 beats market comparable devices by offering lower run currents in a low power run mode. A combination of low power and high performance offers unique flexibility to turn peripheral clocks on and off to use only the current you need.

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►Low Power Features

• Multiple power saving modesStop2 and Stop3 modesLow-power run and wait modes

• Clock gating • Internal Clock Source (ICS)• Ultra-low-power (ULP) 32KHz oscillator• New voltage regulator

Faster wake up times• Real Time Counter (RTC)

Power Management Features

The QE128 has multiple power saving modes, such as stop modes, also known as Stop2 and Stop3, a wait mode, low power run, and low power wait modes. Other features that enable low power are the clock gating techniques, an internal clock source, the new ultra-low power 32KHz oscillator with a standby current around one microamp, a new voltage regulator with a fast wake up time, and a real time counter.

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Low Power Modes

Lowest Power

Highest Performance

►Stop2

►Stop3

►Low power wait (LPWait)

►Wait

►Low power run (LPRun)

►Run

Click a button to explore another mode.

Here are the six operating modes of the QE128 devices. Stop2 is the lowest power mode with the lowest functionality and the slowest wake up at around 29 micro seconds. Stop3 mode is also very low power but it does have more wake up sources and a faster wake up time of around 6 micro seconds.

Low power wait mode is also low power, but it benefits from immediate wake up from an interrupt. Wait mode offers higher power than low power run mode, but it has less functionality because the CPU is not clocked.

Low power run mode is lower power than wait mode, but it has more functionality because the CPU is clocked and is executing code, though at a reduced bus speed. Run mode is the normal and default operating mode. It has the highest power and the highest functionality.

Examine each of these six modes by clicking each of the six buttons. After you explore each mode you will return to this menu. When you have explored all of the modes, click the forward arrow to go to the next page.

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Low Power Modes—Stop2►Partial power down mode with typical IDD as low as

370 nA at 3V►Wakes up in 29us►Exit with IRQ, reset or RTC

• Always resets device on stop recovery

STOP2

POWERLIMIT

370nA

• Most Register values are reset, but values can be saved to and restored from RAM

• Cannot use BDM• Limited Wake Up Sources

• Still very low power consumption

• RAM contents are maintained with I/O states latched

• The RTC can be used to wake the MCU up without an external event

LimitationsAdvantages

Stop2 is the lowest power mode on the QE128. It halts the systems clocks and powers down the voltage regulator. It wakes up from a valid interrupt - IRQ, a reset, or a flag from the real time counter - in 29 microseconds. Stop2 mode is always exited as if a POR (power on reset) occurred.

The advantages of using Stop2 mode is that it still has a very low power consumption. The RAM contents are maintained and the I/O states are latched. The RTC can be used to wake up the MCU without an external event at periodic intervals.

The limitations of Stop2 mode are that upon reentry into the main program from Stop2, most register values are reset but values can be saved and restored from RAM before entering the mode. You cannot use BDM in Stop2 and, as mentioned earlier, the number of wake up sources are very limited.

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Low Power Modes—Stop3►The equivalent to HC08’s stop mode with typical IDD as

low as 450 nA at 3V►Wakes up in 6us►Exit with any of the following active interrupt: ADC,

ACMP, IRQ, KBI, LVD, RTC, SCI or reset

POWERLIMIT

450nA

STOP3

• Not quite as low current as stop2

• Limited Wake Up Sources

• Still has very low current consumption

• RAM and register retain their values

Does not require re-initialization of peripherals

• Can use external clock as a highly accurate input into the RTI

LimitationsAdvantages

Three versions of Stop3: 1. BDM (background debug mode) enabled2. Voltage Regulator active3. No frills - BDM off; V reg in standby

Stop3 mode halts the systems clocks and places the voltage regulator into standby. For those familiar with Freescale's previous families, Stop3 mode is equivalent to the HC08's stop mode, with typical IDDs as low as 450 nano Amps at 3V. Stop3 on the QE128 consumes the most power of the two stop modes but requires a wake up time of just six microseconds.

The six microsecond wake up time for both devices -- the HCS08 and the ColdFire V1 – contains a few time components. One is an RC time; the others are based on clock speed. The voltage regulator on the new VLP (very low power) regulator takes approximately five microseconds to start up, regardless of the CPU frequency. The remaining one to two microseconds are based on the clocks: 16 cycles are needed from the ICS output and another 11 bus clocks for interrupt stacking.

Obviously, this can go well beyond two microseconds if a very slow clock source is used. Applications needing a quick response time typically have high bus frequency.

Exit from Stop3 mode is not as limited as from Stop2 mode but is limited to the analog digital converter, the analog comparator, an interrupt request, a keyboard interrupt, low voltage detect, the real time counter, the serial communication interface, or a reset if enabled.

The advantages of Stop3 mode are that it still has a very low current consumption, the RAM and registers retain their values, so you are not required to reinitialize your peripherals, and you can use an external clock as a highly accurate input to the real time counter.

The limitations of Stop3 mode are that it is not quite as low current as Stop2 and it has limited wake up sources.

There are versions of Stop3. The first is with BDM (background debug mode) enabled. This is very useful when debugging, but it should not be used at any other time because the BDM module draws a significant amount of current. The second version of Stop3 is with the Voltage Regulator active. This means that the LVD circuitry is enabled -- LVD being low voltage detect -- and any attempts to enter Stop2 with the LVD on will actually result in a Stop3 entry. The third version of Stop3 is no frills: the BDM is off and the V reg is in standby. This version uses the least power.

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Low Power Modes—LPRun►The voltage regulator is in standby►Typical IDD as low as 22µA at 16 kHz and 3V ►The bus clock source is limited to FBELP

V1 POWER

LIMIT

50μA

S08 POWER

LIMIT

22μA• Maximum frequency is

limited (see reference manual)

• Flash cannot be programmed or erased

• ACMP cannot use BandgapReference

• LVD System Disabled• Cannot Use BDM• ADC must use asynchronous clock source

• All peripherals can be used• Reduces power

consumption versus run mode when high performance is not required

• Interrupts can be serviced without changing modes

LimitationsAdvantages

There are two new power saving modes on the QE128: low power run and low power wait. Low power run mode saves power compared to normal run mode by placing the voltage regulator in standby. Typical IDDs are as low as 22uA. This mode has restrictions on the ICS mode as you can only enter this mode if you are in FBELP mode, which will be explained later. There are also restrictions on low volt detect circuitry, the internal Bandgapuse, and background mode enablement. This restriction does not apply to peripherals. This is because the mode allows you to run all of them at a reduced bus speed with the benefit of reduced current consumption due to the voltage regulator stand by state.

Another advantage of low power run mode is that interrupts can be serviced without having to change modes. Please see the reference manual for details on the bus speed restrictions.

You cannot program or erase the flash in this mode. The ACMP can not use the internal Bandgap as a reference due to the LVD circuitry being disabled. It can not use BDM, and the ADC, if needed, must use the asynchronous clock source.

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Low Power Modes—LPWait►The bus clock source is limited to FBELP►Clocks are disabled to CPU but peripherals can be clocked►Typical IDD as low as 195 µA at 16 kHz and 3V►The voltage regulator is in standby

LPWAIT

POWERLIMIT

19μA

• Consumes more current than stop modes

• Maximum frequency is limited (see reference manual)

• Reduces power consumption versus LPRun mode

• No stop recovery time; the interrupt is serviced immediately

• Wake up to Run or LPR by any interrupt

LimitationsAdvantages

Low power wait mode can only be entered from low power run. The low power run ICS mode is limited to FBELP. The clocks are disabled to the CPU but the peripherals can be clocked. Typical IDD in low power wait mode is as low as 19 microamps at 16 kilohertz and 3 volts. Like low power run, the voltage regulator is in standby.

The advantages of this mode are that the power is reduced versus low power run mode, there is no recovery time because the interrupt is serviced immediately. Another advantage is that you can wake to either low power run or normal run by any interrupt from low power wait mode.

The limitations of this mode are that it consumes more current than stop modes and the maximum frequency is limited. The MCU can typically save around 50% of its current consumption in low power wait versus low power run mode.

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Low Power Modes—Wait►The bus clock source remains active►Clocks are disabled to CPU but peripherals can be

clocked

POWERLIMIT

680μA

WAIT

• The voltage regulator remains active, consuming more current than stop or LP modes

• Reduces power consumption versus run mode

• No stop recovery time; the interrupt is serviced immediately

LimitationsAdvantages

In wait modes, the CPU shuts down as the system clock is disabled to conserve power. The MCU system clocks and voltage regulation are maintained, saving more power than when the system is in run mode.

Wait mode saves approximately 30-60% of the run mode current, depending on the bus frequency. The higher the frequency, the greater the savings. Wait mode benefits from the key feature that any interrupt will allow the mode to be exited.

The limitations of this mode are the voltage regulator does remain active, consuming more current than stop or low power wait and run modes.

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Low Power Modes—Run►Standard user mode – default out of any reset►Clocks are enabled to CPU and all peripherals►Typical IDD as low as 12mA at 50MHz CPU speed and 3V►The voltage regulator is in active mode

V1 POWER

LIMIT

25mA

S08 POWER

LIMIT

12mA

50 MHz CPU• Consumes more current than other modes

• All peripherals can be used without limitations

• Interrupts can be serviced without changing modes

• Flash can be reprogrammed across all VDDs and temperature

LimitationsAdvantages

Run mode is the standard user mode and is the default mode out of any reset. The clocks are enabled to the CPU and to all the peripherals by default allowing code to be executed. Typical IDDs can be as low as 12 microampsat 50 megahertz CPU, 25 megahertz bus at 3 volts. The voltage regulator is in active mode.

The advantages of this mode are that all peripherals can be used without any limitations, the interrupts can be serviced, the flash can be reprogrammed across all VDDs and temperatures.

The limitations of this mode is that is uses more current than any of the other modes on these devices.

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Match each item to the most appropriate description by dragging the letters on the left to the correct locations on the right. Click Done when you are finished.

Low Power Run

Stop2B D

Done Reset ShowSolution

A Saves approximately 30-60% of the run mode current, depending on bus frequency. C

C Wait

Second lowest power mode. Features a wakeup time of 6 uS.

A Cannot program or erase the flash.

D Stop3 F Can wake to either low power run or normal run by any interrupt.

Question

E Run

F Low Power Wait

E

B

Standard user mode; the default mode out of any reset.

The lowest power mode on the QE128

Test what you have learned so far by matching the feature on the left with the appropriate description.

Correct.

C.) Wait mode saves approximately 30-60% of the run mode current, depending on the bus frequency. D.) Stop3 consumes the most power of the two stop modes but requires a wake up time of just six microseconds. A.) You cannot program or erase the flash in low power run mode. F.) The device can wake to either low power run or normal run by any interrupt from low power wait mode. E.) Run mode is the standard user mode and is the default mode out of any reset. B.) Stop2 is the lowest power mode on the QE128.

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Mode Interaction

Stop3

Stop2RUN Low PowerRun (LPR)

Low PowerWait (LPW)WAIT

This diagram shows what clock mode transitions are legal. From the default mode RUN the user code can transition to Stop3, Stop2, and WAIT modes. User code can also transition to Low Power Run mode. You can not go from RUN mode directly into Low Power Wait. The only path to this mode is through Low Power Run.

From Low Power Wait mode you can wake up into either RUN mode or Low Power Run mode by setting the correct bits.

From Low Power Run mode you can go to Stop3, RUN, or Low Power Wait. The limitation of Low Power Run mode is that you can not go from Low Power Run into Stop2 which is the lowest power mode on the devices.

Stop3 can be entered from RUN or Low Power Run modes and can wake up to either of those modes.

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Timing Optimizations

► Implement new cell library and improved clock tree and gating techniques

• Achieved through new design tools

►Re-architecture for module enabling/disabling during run mode (explicit clock gating)

►Every peripheral has clock enable bit

►Reset to clock enabled for compatibility with existing MCUs

►Disabling clocks to unused modules reduces run and wait currents

The QE128 design has been focused to achieve flexibility, performance, and power reduction due to timing optimization. The devices implement a new cell library and an improved clock tree and gating techniques. The devices have been restructured for module enabling/disabling during the run modes through explicit clock gating. Every peripheral has a clock enable bit.

The reset condition of these bits are enabled for compatibility with existing MCUs. Disabling clocks to unused modules reduces run and wait currents because unused gates on the silicon are not clocked. This saves significant amounts of power.

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Clock Gating

► Clock gating is the mechanism used to disable the clock tree to any unused peripheral

► On previous families and the default setting on QE128 the bus or peripheral clock runs to all modules regardless if they are enabled or not

► Clock Gating saves power by not clocking unused gates

Clock gating is the mechanism used to disable the clock tree to any unused peripheral. This is either total or sectional. Thus, at the beginning of your code unused peripherals can be gated off so they do not draw power. During your code execution you can turn on modes only when they are needed, and turn them off when you are finished with them. This saves the system's total power consumption.

In previous families the bus and peripheral clocks are supplied to all modules regardless of whether they are specifically enabled or not. This is the default setting on the QE128.

Clock gating saves power by not clocking unused gates.

This pie chart shows the level of savings that can be produced by gating off the peripherals. Notice that this is approximatelyone third of total power use.

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Internal Clock Source modes

► Module that controls all the clocks on the device

► Frequency Locked Loop (FLL)• The FLL varies frequency using the internal 32KHz oscillator or an

external clock as reference

► Mode name descriptions• F - FLL• E - Engaged• B - Bypassed• I - Internal• E - External• LP - Low Power

The ICS - internal clock source module - controls all the clocks on the device. The heart of the ICS module is the FLL, the frequency locked loop. The FLL varies frequency using the internal 32 kilohertz oscillator or an external crystal or resonator as a reference.

There are six modes of the ICS. The acronyms used for these modes, once understood, are very simple to understand. Every mode begins with F, which stands for FLL. The next letter in the mode is E for engaged or B for bypassed. The third letter is either I for internal clock source or E for external clock source. LP at the end of the mode description stands for low power. This extension to the ICS not only bypasses the FLL but also disables it to save power.

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Clock Modes► FEI (FLL Engaged Internal) default► FEE (FLL Engaged External)► FBI (FLL Bypassed Internal)► FBE (FLL Bypassed External)► FBILP (FBI Low Power)► FBELP (FBE Low Power)

FLL EngagedInternal (FEI)

FLL BypassedInternal (FBI)

FLL BypassedInternal Low

Power (FBILP)

FLL BypassedExternal Low

Power (FBELP)FLL BypassedExternal (FBE)

FLL EngagedExternal (FEE)

FEI, FLL Engaged Internal, is the default ICS mode out of reset. You can freely move between the four modes: FEI, FEE, FBI, and FBE. FBILP can only be entered from FBI mode and FBELP can only be entered from FBE mode. In practice, what this means is to go to FBELP mode from reset, the code must go through and stabilize an FBE mode before moving on. The same applies to FBILP mode.

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Internal Clock Source Features

►Software-selectable bus frequency divider (ICS:BDIV)• Divide bus clock• Available in all clock modes• Allows quick frequency change

►Two types of external clocks:• Oscillator (crystal) – needs feedback• Canned oscillator, function generator – no feedback

►The external reference can be left enabled in stop mode

The ICS is one of the most flexible and feature-rich clock modules on an MCU. It has a software-selectable bus frequency divider, also known as BDIV. This, as the name states, divides the bus clock from the internal clock source. It is available in all clock modes, even bypassed and low power. This divider allows quick frequency changes without affecting the FLL frequency because all it does is divide the FLL out signal.

The ICS has two possible types of external clock sources: a crystal oscillator which requires feedback and a canned oscillator, or function generator, that does not require feedback.

The external reference can be enabled in stop mode if required.

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Oscillator Options

►Low power limits voltage swing on oscillator pins to minimize power consumption

►High gain drives oscillator pins to rail for robust operation in noisy environments

►Low range, low power 32 - 38.4KHz

►Low range, high gain

►High range, low power 1 – 8MHz

►High range, high gain 1 – 16MHz

The external oscillator can be manipulated through settings internal to the microcontroller to set it to either high power or low gain. Low power settings limit the voltage swing on the oscillator pins to minimize power consumption. High gain drives the oscillator pins from rail to rail for robust operation in noisy environments.

Low range/low power and low range/high gain can be used with crystals or resonators from 32 - 38.4 kilohertz.

High range/low power can be used with crystals or resonators from 1-8 megahertz, and high range/high gain can be used with crystals or resonators from 1-16 megahertz. Using the correct crystal and the correct settings can help save power in your system.

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Real Time Counter

►Basic timer used to generate a periodic interrupt

► RTC is the only timer function available in the stop modes• Generates periodic wake up from stop2 or stop3

►There are 3 clock sources for the RTC• 1kHz Low power oscillator (LPO) • OSCOUT - output of the external crystal oscillator • ICSIRCLK - internal reference clock of the ICS

The real time counter is a basic timer used to generate a periodic interrupt. It is the only timer function available in the stop modes. It can generate a periodic wake up from stop2 or from stop3. There are three clock sources from the real time counter: a 1 kilohertz low power oscillator, known as the LPO; the output of the external crystal oscillator; or the internal reference clock of the ICS, known as ICSIR clock.

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32KHz Oscillator

►RTC’s internal clock (Low power oscillator) is not accurate over processing, voltage and temperature variations

• +/-30% frequency variation• Customers often require more accuracy

►Used in stop modes to drive the RTC providing an accurate time base for the wakeup

►Advantages• Reduces typical stop3 current from 5uA to 1uA• Allows for time-keeping accuracy at very low power

The real time counter's internal clock (the low power oscillator) is not accurate over processing, voltage, and temperature variations. It has a plus or minus 30% frequency variation, however customers often require more accuracy. The external 32 kilohertz oscillator can be used in stop mode to drive the real time counter, providing an accurate time base for wakeup. This offers two advantages. It reduces the stop3 current from around five microamps from the previous S08 devices to one microamp. This allows for timekeeping accuracy at very low power.

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Voltage Regulator (VREG)► VREG is always on when MCU is in run or wait modes

• Also on when in stop3 with LVI enabled

• Runs internal logic at lower voltage, therefore lower power

► Modify standby VREG to allow execution in low power modes• New LPRun and LPWait modes allow

peripherals to run while VREG is in standby

► Create new VREG with faster start up• Allows more applications to

use stop modes

2.42V

IDD

VDD

The voltage regulator, also known as V reg, is always on when the MCU is in run or wait modes. It is also on when in stop3 with LVI or BDM enabled. The V reg runs the internal logic at a lower voltage, therefore the MCU consumes less power.

The V reg on the QE128 has been modified from the standard V reg to allow module execution in low power modes. The new low power run and low power wait modes allow the peripherals to run while the voltage regulator is in standby.

The new voltage regulator also has a faster startup, which allows more applications to use the stop modes. Wake up from stop2 is now 29 microseconds and wake from stop3 is around six microseconds.

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Summary of ULP Features► Ultra-low-power run and wait modes

• CPU and peripherals run with voltage regulator in standby• Allows full peripheral functionality at reduced frequency for lower power operation

► Clock gating• Turn clocks off to unused peripherals• Reduces overall run and wait mode current

► Ultra-low-power internal regulator & oscillator• Fast start up from stop modes, typically 6-7 us• New low power external oscillator consumes around 1 uA

► Ultra-low-power internal clock source & oscillator• Eliminates need for external clock source• Supports low frequency operations which lowers power in system

► Ultra-low-power real time counter• Use in run, wait and stop modes• Use with low power oscillator, internal or external clock sources

Here is a summary of the ultra-low-power features. Ultra-low-power run and wait modes allow the CPU and peripherals to run with the voltage regulator in standby. They also allow full peripheral functionality at a reduced frequency for lower poweroperation.

Clock gating turns the clock off to unused peripherals whenever required, reducing the overall run and wait mode currents, because fewer gates are clocked.

The ultra-low-power internal regulator and oscillator have fast start up times, typically six to seven microseconds. There is also a new low power external oscillator consuming around one microamp.

The ultra-low-power internal clock source eliminates the need for an external clock source and supports low frequency operations, which lowers power in the system.

The ultra-low-power real time counter can be used in run, wait, and stop modes with the one kilohertz low power oscillator, the internal 32.768 kilohertz oscillator, or the external clock source known as OSCOUT.

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Which of these statements about clock management is true? Select all that apply and then click Done.

A. The FBI is the default ICS mode out of reset.

B. The FLL varies frequency using the internal 32 kilohertz oscillator or an external crystal or resonator as a reference.

C. Clock gating saves power by not clocking unused gates.

D. A crystal oscillator is the only type of external clock source available on the ICS.

Done

Question

Take a moment now to answer this question about clock management.

Correct.

A.) FEI, FLL Engaged Internal, is the default ICS mode out of reset. B.) The FLL varies frequency using the internal 32 kilohertz oscillator or an external crystal or resonator as a reference.C.) Clock gating saves power by not clocking unused gates. D.) The ICS has two possible types of external clock sources: a crystal oscillator which requires feedback and a canned oscillator, or function generator, that does not require feedback.

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Flash Reprogramming Voltage

The QE128 flash array is reprogrammable down to 1.8 volts. In an application such as remote control running off two 1.5 volt, also known as AA batteries, this means that useful battery life is prolonged. This diagram highlights the potential of this feature. Should an application require that you write to flash to store data, for example to use the flash as emulated E PROM, the QE128 will allow the battery life to be extended.

Note that the LVD, low voltage detect system – which is enabled after reset - has a low trip point of 1.84 volts. The POR reset condition of the LVD bit in the System Power Management Status and Control Register 3 (SPMSC3) is zero, which means the LVD circuit will hold the device in reset while the supply is still below 1.84 V. The exception is a wake up from Stop2, which leaves the LVD system setting unchanged. This means that if an application is intended to run down to 1.80 V, resets should be avoided because the only way to recover would be to change the batteries.

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Extending Battery Life

►Clock management• Run fast when CPU performance

is the critical path

• Run slow when waiting on peripheralsUse bus divider to reduce frequency

Instead of continuously reading a flag (polling), use wait mode and interrupts

• Use external clock option (FBELP) for lowest power

Turns the FLL off

• Use lowest power DCO multiplier and divider combination when FLL is used

Clock management enables you to run fast when the CPU performance is the critical path. It also allows you to run slow when you're waiting on peripherals. The bus divider can be used to quickly reduce the frequency and instead of continuously reading a flag (often referred to as polling). Clever clock management means you can use wait modes and interrupts instead.

Using the external clock option (FBELP mode) uses the lowest power because the FLL is turned off. You can also extend your battery life by using the lowest DCO (digital controlled oscillator) multiplier and divider combination when the FLL is used.

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Power Saving: I/O Manipulation

►Slew Rate Control• Output pins have slew rate control• Reduce system power by slowing transients.

►Drive Strength Control• GPIO pins are at high or low drive strength

High - pin sources or sinks higher currents Low - pin minimizes power consumption of MCU and application

►Unused Pins• Inputs - pulled up by the internal pull up resistor • Outputs - drive low to keep power consumption down

There are three simple power-saving input/output manipulation features on the QE128 device. The first is slew rate control. All of the devices' output pins have slew rate control which means, when driving external components, you can reduce power by slowing the transients.

The second power-saving feature is drive strength control. Each general purpose I/O pin can operate as either high or low drive strength. If high strength is selected, the pin sources or sinks higher currents. This means that the MCU consumes more power. Low drive strength with a small loading on the pins keeps the power consumption of the MCU and the application at a minimum.

The third power-saving feature is that all unused pins in the application, including on smaller packages in which the GPIO are not bonded out to pins, should be pulled up by the internal pull up resistor if they are set as inputs. If they are set as outputs, they should drive low to keep power consumption down and to improve the application's robustness.

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Positioning with Ultra-low Power

S08 with ULP

HC08

Performance

Power

S08 w/o ULP

This diagram illustrates the competitive landscape in which Freescale will thrive after the introduction of the QE128. Each of the stars represents a competitor’s comparable product. As you can see, earlier Freescales 8 bit MCUs, such as the HC08, were not designed to be low voltage, low power. Through low voltage peripheral techniques and state-of-the-art optimizations, Freescale will compete and boost power and performance.

Be assured the QE128, MC9S08, and MCF51 versions will beat the best ARM products on the market today. The ultra-low power technology provides additional power savings and energy efficiency while retaining the same performance characteristics. With the introduction of these new ultra-low power features, Freescale has cemented its place in this market.

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General Specifications

6 us6 usStop3 - Wake Up Time

450 nA520nAStop3 - Int. circuits loosely regulated; clocks at low frequency

370 nA370 nAStop2 – Lowest power mode; partial power down of circuits

22 uA50 uALower Power Run Mode @ 32 kHz CPU/16 kHz bus

11 mA27 mARun Mode @ 50 MHz CPU / 25 MHz bus

1 mA2 mARun Mode @ 2 MHz CPU / 1 MHz bus

MC9S08QE128MCF51QE128

This table shows power consumption figures for the key CPU modes of the MCF51QE128 and MC9S08QE128. Notice that in run mode and low power run mode, the ColdFire V1 product is approximately twice as power hungry as the S08 product. Stop2 and Stop3 modes are approximately the same in terms of power and they have the same wake up times.

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Smoke Detector Case Study

3.3V to 1.8V

GND

LED

Alarm

SmokeChamber

OpAmp

MC9S08QE128or

MCF51QE128

Here is a block diagram of a simple smoke detector. The MCU has one main input from the smoke chamber and a power supply from a battery, and two outputs: an alarm and an LED. The real time counter module can wake up the device periodically from Stop2.

If no event has occurred, the MCU has to take a reading from the op amp, process the data, and make a decision to go back into Stop2 mode. If there is a battery warning the MCU must turn on the LED permanently. It must sound the alarm If smoke is detected.

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Smoke Detector Case Study

Stop Stop Stop Stop

Run

Run

Run

Run

Run Run Run Run

Stop Stop Stop Stop

PowerQE128 S08QE128 CFv1

Time

The MC9S08QE128 has a slightly lower run mode current than the ColdFire equivalent, but the CPU has fewer data processing capabilities. Due to this, the MC9S08QE128 may take longer than the MCF51QE128 to perform the required tasks. This is dependent upon how the code is written and how the routines are executed. This is especially true in data manipulative applications because the 32 bit core can crunch numbers faster than the 8 bit S08 core.

This graph shows the power versus times performance. Please note the axes are not to scale. The Flexis devices give the designer a choice of speed or power, depending on the application’s profile. In applications where execution speed is important, the ColdFire V1 device may be the best solution. The controller continuum of these two products means that migrating from one strategy to the other is quick and easy because you can use the same board software. And, with the available memory and I/O with the two products, you can add networking and even Zigbee to the solution.

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Applications

► Medical applications• Blood Pressure monitor

Uses in stop, run and low power run modesLow current consumptionFast wake up time

► Industrial applications• Industrial security

Serial smoke detector systemRuns in low-power run modeExtended battery life

In many applications, lower power is an extremely important consideration. These two examples point out some of the new low power features introduced in the QE128 devices.

A blood pressure monitor is an example of a medical application. Most of the time, this device is running in stop mode. Therefore, it has low current consumption. It wakes up in 6 microseconds periodically to read an e field sensor to turn on a display. When it gets this reading, it enters low power run mode, to help keep the application power down, while the user is surfing the menus because this does not require high speed operation. When commanded to take a measurement, it goes into run mode. Because run mode is high speed, it can also be used for voice generation.

In industrial applications, industrial security systems can use our device in low power run mode, allowing it to run at lower frequency and consume less power. For example, in a serial smoke detector, stop modes cannot always be used in these applications because the system has a current budget, meaning it cannot afford a current spike when it wakes up from the stop mode. The low power run mode not only enables the application to run within the power quota, it also lowers the power, enabling extended battery life.

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QuestionMatch each value to the correct mode and device by dragging the items on the left to the correct cells in the table on the right. Click Done when you are finished.

6 us

Done Reset ShowSolution

450 nA

1 mA

22 uA

27 mA

370 nA 6 us6 usStop3 - Wake Up Time

450 nA520nAStop3 - Int. circuits loosely regulated; clocks at low frequency

370 nA370 nAStop2 – Lowest power mode; partial power down of circuits

22 uA50 uALower Power Run Mode @ 32 kHz CPU/16 kHz bus

11 mA27 mARun Mode @ 50 MHz CPU / 25 MHz bus

1 mA2 mARun Mode @ 2 MHz CPU / 1 MHz bus

MC9S08QE128MCF51QE128

Test what you have learned so far by matching the value on the left with the correct mode and device on the right.

Correct.

The correct answers are shown.

Click the forward arrow to continue on to the next page.]

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True or false? The MC9S08QE128 has a slightly lower run mode current than the ColdFire equivalent. Click the correct answer and then click Done.

A)True

B)False

Done

Question

Please answer this question about migrating from the 8bit QE to the 32bit QE family.

Correct!

The MC9S08QE128 has a slightly lower run mode current than the ColdFire equivalent, but the CPU has fewer data processing capabilities.

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• Power Management Features– Low Power Modes– Clock Gating– Internal Clock Source– 32KHz Oscillator– Voltage Regulator– Real Time Counter

• Clock Management• Freescale Positioning with Ultra-low Power• QE128 General Specifications • Applications

Course Summary

For more information, please visit our Web site:www.freescale.com/flexis

• AN3460 titled Lower Power Design Enabled by MC9S08QE128 application note• MCF51QE128 Flexis Microcontrollers application note

This concludes the “QE128 Low Power” course. Thank you for taking the time to complete this training. In thiscourse you learned about the power management features of the QE128 including low power modes, clock gating, the internal clock source, the 32 kilohertz oscillator, the voltage regulator, and real time counter. You also learned about clock management, Freescale’s positioning with ultra-low power, QE128 general specifications, and some target applications.

Visit Freescale.com/Flexis for details on the QE128 ultra-low-power features and more information on great applications and how to move within the Freescale controller continuum. The website also includes additional information on the Flexis concept, including information on our key design objectives and training modules on how to use these controllers.

sFor more detail about CPUs, ICS, and registers, read the AN3460 titled Lower Power Design Enabled by MC9S08QE128 application note and MCF51QE128 Flexis Microcontrollers application note.