F 19 SERVICE MANUAL - Reptips · F 19 SERVICE MANUAL THIS DOCUMENT IS A PROPERTY OF INDUSTRIE...

F 19 SERVICE MANUAL

THIS DOCUMENT IS A PROPERTY OF INDUSTRIE FORMENTI ITALIANO AUTHORIZED MODIFICATIONS

ARE PERMITTED.

CREATED BY E.G.

There are two different types of F19 chassis that are equipped with two

different microcontroller.

These microcontroller are known as ETT having a code SAA5297A and

PAINTER with a code number SAA5553.

From the point of view of the application on the F19 chassis the two type of

microcontroller are substantially having the same performances, the same pin-

out , the same firmware but they are not interchangeable as the power supply

are different.

In case of SAA5297A the power supply is 5 V for the SAA5553 is 3.3 V.

Even if the two devices are non interchangeable the two chassis

can be interchanged as the in/out interface are exactly the same.

As the specifications of the two devices are the same and the first version of

the chassis was equipped with the SAA5297A , in this document the

characteristics of it are very much detailed meanwhile there is a very short

description (as an addendum at the end) for the SAA5553.

E.G.Data creazione 31/10/99 15.38 1 / 7 f19intro

F19 CHASSIS DESCRIPTION

Summary

The F19 is a chassis suitable to drive CRT having both 4 by 3 and 16 to 9 aspect

ratio and dimension from 25" up to 34".

As we can see from the block diagram the chassis is equipped with the most recent

Integrated Circuit like the one chip TV processor TDA884x that does include all the low

level signal processing including Video, Audio, synchronisation process, and chroma

decoder . (see more detail at the "TDA884x FAMILY SPECIFICATION" paragraph), and

the Sound Processor TDA9875A that perform all sound function including digital decoding

of NICAM signals. (see more detail at the " TDA9870A & tda9875A MAIN

CHARACTERISTICS" paragraph).

The above mentioned devices are driven by an Integrated Circuit that does include

the microcontroller function with 64 K ROM and the TELETEXT acquisition and 8 pages

RAM. (SAA5297A)

In the F19 chassis there are, besides the stereo one, two possible module that are

performing "FEATURES" like PIP (picture in picture) and / or CTI (colour transients

improvement) and 4 by 3 to 16 by 9 signal processing. One further module is dedicated to

the so called "Zero Power Stand By"

A 26 Key Remote Control is performing the full control for the end- used but can

also be used in " SERVICE MODE" to control and adjust, without open the back cover of

the TV set all the necessary functions.

With the 5 "LOCAL KEY BOARD" button all the end user function can also be

performed

When the TV set is equipped with a PLL tuner the microcontroller recognise it and

the tuning method became a frequency synthesis system if not it work as a voltage tuning

system (provided all necessary components are mounted)

The TV make use of a multilevel MENU (activated both by the Remote Control and

Local Keyboard) using five selectable languages ( Italian, German, English, France, end

Spanish) with which it is possible to control sequentially all video and sound value, to

adjust several parameter like picture format, sound response, sleep timer etc., and to set

others important parameter like standard, select country for automatic tuning and sort etc.

Here below a list of the characteristics of the TV se


TV SET CHARACTERISTICS (MONO & STEREO )

PICTURE TUBE SIZE :• 4 : 3 ASPECT RATIO 21” / 25” / 28” / 29” / 34”• 16 : 9 ASPECT RATIO 28 “ / 32”• STANDARD• R.F. (ANTENNA) (FOR FREQ. SYNTH.) CCIR ( B / G/ L / L’ / D / K / I )• VIDEO (SCART & CINCH) B / G/ L / L’ / D / K / I / M / N• COLOUR (MAX. THREE STANDARDS) PAL / SECAM / NTSC• SOUND STANDARD: B / G/ L / L’ / D / K / I∗ MONO AM & FM∗ STEREO A2 OR NICAM

TUNING SYSTEM SELECTABLE : FACTORY OPTION

FREQUENCY SYTHETIZER• TOTAL AVAILABLE CHANNEL NUMBER 200• CHANNEL IN ONE RF STANDARD UP TO 100• NUMBER OF PROGRAM 100• DIRECT PROGRAM & CHANNEL CALL WITH 1, OR 2 OR 3 DIGIT• PROGRAM & CHANNEL STEP UP AND DOWN YES• VOLTAGE SYNTHESISER• CABLE & HYPERBAND CHANNEL YES• SWITCHABLE AFC YES• AUTOMATIC SEARCH TUNING YES• A S T WITH AUTO SORT YES

AUDIO SECTIONPOWER• MONO 6 W RMS.• STEREO 2 x 6 W RMS.EXTERNAL CONNECTION• HEADPHONE STEREO SET ONLY• LOUDSPEAKERS INTERNAL L.S. SWITCHEDA / V INPUT / OUTPUT• FRONT PANEL CINCH A / V INPUT• I FULL SCART (CVBS, STEREO, RBA) MULTIMEDIA INPUT OUTPUT• SCART (CVBS & STEREO IN / OUT) VCR, HI.FI, SATELLITE, ETC• SCART A TO SCART B LOOP THROUGH FOR PROGRAMS DUBBINGTXT PANEUROPEAN CHARACTER SET• LEVEL 1 8 PAGES• LEVEL 1,5 (FASTEXT) 7 PAGESFEATURES• CTI (COLOUR TRANSIENT IMPROVEMENT) OPTION• 16:9 TO 4:3 VIDEO COMPRESSION ONLY FOR 16:9 TV SET• VERTICAL ZOOM OUT 3 LEVEL• MENU DRIVEN SYSTEM• EASY TO USE REMOTE CONTROL• REMOTE CONTROL WITH “SERVICE” USE NOT ACCESSIBLE TO END USER

• PIP OPTION

IIC bus

RGB

VIDEO &AUDIO

AUDIOAUDIO

VERTICALTDA3654

RGB(OSD)

H. DRIVER L.O.T.BU 508 D

E.W. GEN.

V.

H.

EAT

110°

VIDEO PROCESSOR

TDA 8362A

PIPSIEMENS

A U D I O

THIS MODULE IS PRESENT ONLY FOR STEREO SET

FULL SCARTSCART INTER.2ND SCART

RGB

BC 639

TDA4950E H T TRAFO

F16UPF19.DRWE.G. 2/02/99

F16 UPDATED F19 BLOCK DIAGRAM

TDA1521

MICRO

PCA84C841/210

PIP (RGB)

PLL

TUNER

RGB

CUT-OFF

TXT & OSD R B G

A/V INA /V OUTA/V IN/OUT

TDA9875

140 V26 V

15 V12 V

8 V

TDA 4605 & STH7N80F

POWER SUPPLY

VIDEO AMPL.

TDA5112

S E C A M D.L. CROMA

TXT

SAA5281/....

SAA52

97A

PHILIPST.O.P.

TDA4661TDA8395TDA844X

SAWFILTER

EEPROM

PCF8582

AUDIO

IIC bus

RGB

VIDEO & AUDIOAUDIO

AUDIO

H. DRIVER

V.

H.

EAT

110°

AUDIO STEREO (NICAM) PROCESSOR


VIDEOSCARTSWITCH LA7955

RGB

BC 338

H. DEFL.& E H T TRAFO

F19BLDIA.DRWE.G. 17 / 7 / 99

TDA1521

PIP (RGB)

RGB

CUT-OFF

TXT & OSD R B G

A/V INA /V OUT

A/V IN/OUT

150 V26 V

12 V8 VTDA 4605 & STH7N90F1

POWER SUPPLY

E T T

MICROCONTROLLER& TELETEX 8 PAGES

I.R. INPUT

LOCAL KEY BOARD

EEPROMPCF8584 /ST2404CB

TDA 8843(4)*IF VIDEO & PLL DEM*AGC & AFC, MUTE*AUDIO PLL DEM *PAL/NTSC (SECAM) DEC.*B.B CHROMA DELAY LINE*FULL SCART INTERFACE.

*H & V SYNC PROCESSIG*FULL IIC BUS CONTROLL FOR:*AUTO CUT-OFF*ALL ANALOGUE FUCTIONS*GEOMETRY CORRECTION*FEATURES INTERFACE

IIC bus

IIC bus

4

H DRIVE

FEATURES MODULE

TDA4566 (CTI)SAA4981 (16:9 TO 4:3)

VERTICALTDA8351

U V

E-W POWER

F19 BLOCK DIAGRAM

SAA5297ABUK474200A

DRIVERTRAFO

E-W DRIVE COIL

CRT

VERTICALFEEDBACK

E-W LOAD COILSAWFILTER

TUNER

PLL

L.O.T.

BU 508 D

VIDEO AMPL.

TDA5112

2 x 7 W

HEADPHONE

OPTION

OPTION

IIC BUS ONE CHIP VIDEO PROCESSOR

AUDIO POWER

2ND SCART FULL SCART

A/V/ CINCH (OPTION)

LINE OUT (OPTION)

TDA 9811 (nicam) TDA 9870A (TDA9875A (nicam)

E-W-

PIP

5 V

AUDIO SCART SWITCH HEF4053

F 19 INTERCARRIER

VIDEO

AUDIO

I.F.

IIC bus

RGB

VIDEO & AUDIOAUDIO

AUDIO

H. DRIVER

V.

H.

EAT

110°

AUDIO STEREO (NICAM) PROCESSOR


VIDEOSCARTSWITCH LA7955

RGB

BC 338

H. DEFL.& E H T TRAFO

F19BDE&P.DRWE.G. 22/04/2000

TDA1521

PIP (RGB)

RGB

CUT-OFF

TXT & OSD R B G

A/V INA /V OUT

A/V IN/OUT

150 V26 V

12 V8 VTDA 4605 & STH7N90F1

POWER SUPPLY

E T T

MICROCONTROLLER& 8 PAGES TELETEXT

I.R. INPUT

LOCAL KEY BOARD

EEPROMPCF8584 /ST2404CB

TDA 8843 (4)

SAA5297A orSAA5553M3

*IF VIDEO & PLL DEM*AGC & AFC, MUTE*AUDIO PLL DEM *PAL/NTSC (SECAM) DEC.*B.B CHROMA DELAY LINE*FULL SCART INTERFACE.

*H & V SYNC PROCESSIG*FULL IIC BUS CONTROLL FOR:*AUTO CUT-OFF*ALL ANALOGUE FUCTIONS*GEOMETRY CORRECTION*FEATURES INTERFACE

IIC bus

IIC bus

4

H DRIVE

FEATURES MODULE

TDA4566 (CTI)SAA4981 (16:9 TO 4:3)

VERTICALTDA8351

U V

E-W POWER

F19.1 BLOCK DIAGRAM

BUK474200A

DRIVERTRAFO

E-W DRIVE COIL

CRT

VERTICALFEEDBACK

E-W LOAD COILSAWFILTER

TUNER

PLL

L.O.T.BU 508 D

VIDEO AMPL.

TDA5112

2 x 7 W

HEADPHONE

OPTION

OPTION

IIC BUS ONE CHIP VIDEO PROCESSOR

AUDIO POWER

2ND SCART FULL SCART

A/V/ CINCH (OPTION)

LINE OUT (OPTION)

TDA 9811 (nicam) TDA 9870A (TDA9875A (nicam)

E-W-

PIP

5 V

AUDIO SCART SWITCH HEF4053F 19.1 I

NTERCARRIER

VIDEO

AUDIO

I.F.

F19 TUNINGF19 TUNING&&

TELETEXTTELETEXT

E.G.Data creazione 01/11/99 17.27 8 / 30 F19MANU.doc

SAA529XA FAMILY MAIN CHARACTERISTICS

FEATURES

General

• Single chip microcontroller with integrated teletext decoder

• Single +5 V power supply

• Single crystal oscillator for teletext decoder, display and microcontroller

• Teletext function can be powered-down independent of microcontroller function for

reduced power consumption in standby

• Pin compatibility throughout family.

Microcontroller

• 80C51 microcontroller core

• 16/32/64 kbyte mask programmed ROM

• 256/768/1280 bytes of microcontroller RAM

• Eight 6-bit Pulse Width Modulator (PWM) outputs for control of TV analog signals

• One 14-bit PWM for Voltage Synthesis Tuner control

• Four 8-bit Analog-to-Digital converters

• 2 high current open-drain outputs for directly driving LEDs etc.

• I 2 C-bus interface

• External ROM and RAM capability on QFP80 package version.

Teletext acquisition

• 1 page and 10 page Teletext version

• Acquisition of 525-line and 625-line World System Teletext, with automatic selection

• Acquisition and decoding of VPS data (PDC system A)

• Page clearing in under 64 s (1 TV line)

• Separate storage of extension packets (SAA5296/7, SAA5296/7A and SAA5496/7)

• Inventory of transmitted Teletext pages stored in the Transmitted Page Table (TPT)

end Subtitle Page Table (SPT) (SAA5296/7, SAA5296/7A and SAA5496/7)

• Automatic detection of FASTEXT transmission

1 2 3 4 5 6 7 8 91011121314151617181920212223242526

5251504948474645444342414039383736353433323130292827

V TUN.DSCSWT. L/L'CTI STS.16:9 STSSWT. S1/S2COPY SWT.SWT. CI/S1AV1 STS.AV2 STS.H.P. STS.SYSTEMVSS M+TUHFTV / AVP0.3P0.4P0.5ON / OFFVHF HVHF LVSSACVBS0CVBS1BLACKIREF

SWT 16:9OSC. SWT.

MSDAMSCLSDA 1 INTOSCL 1

AM/FMVDDMRESET

OSCOUTOSCIN

OSCGNDVDDTVDDA

VSYNCHSYNC

BLKRGB

RGBREFPIP STS

INT. TESTFRAME

SAA5297A

2,5 V

5 V

QZ10012 MHz

5 V from ST-BY

I.R.

MAIN IIC BUS

TO CHANGE ASPECT RATIO

MENU V - V + P - P +

MICRO & TXT Block Diagram

SAA5297A.DRWE.G . 17 / 10 / 99

LOCAL KEY BOARD

PAGE RAM

DISPLAY

TIMIN

G

DISPL

AY

OSCILLATOR

8051CORE

PORT

2

PORT

1

PORT

0

PORT3

BUS

ROM RAM TIMER

A/ D

PWM

TXTINT

TO SWITCH S.C.FROM 4.43 TO 3.58 MHz

IIC BUSFOR EEPROM

SOUND STANDARDSWITCH

FROM RESESET CIRCUIT

VERTICALFLYBACK

HORIZONTAL FLYBACK PULSE

TO TDA884X

RGB REFERENCE VOLTAGE

PIP DETECTOR

NOT CONNECTED

NOT CONNECTED

TO CURRENT INTEGRATORVOLTAGE SINTESYS ONLY

TO X13

FRANCE STD. SWITCH

CTI DETECTOR

16 : 9 DETECTOR

SCART1 / SCART2 SWITCHSCART 1 / TVTO SCART 2 SWITCH

FRONT CINCH / SCART1 SWITCH

SCART 1 INPUT DETECTOR


HEAD PHONES DETECTOR

STANDARD SWITCH

UHF SUPPLY (VOLTAGE SINTESYS ONLY)

TV ON / OFF SWITCH

TUNER SUPPLY (V.S. ONLY)

TUNER SUPPLY(V.S. ONLY)

TV / AV SWITCH

CVBS FROM ANTENNA

CVBS FROM SCART

DATA SLICER REF.PIN

T X T DATASLICER &ACQUISITION

1 2 3 4 5 6 7 8 91011121314151617181920212223242526

5251504948474645444342414039383736353433323130292827


SWT 16:9OSC. SWT.


AM/FMVDDMRESET

OSCOUTOSCIN

OSCGNDVDDTVDDA

VSYNCHSYNC

BLKRGB

RGBREFPIP STS

INT. TESTFRAME

SAA5553M3

2,5 V

3 V

QZ10012 MHz

5 V from ST-BY

I.R.

MAIN IIC BUS

TO CHANGE ASPECT RATIO


MICRO & TXT Block Diagram

LOCAL KEY BOARD

PAGE RAM

DISPL

AY

TIMIN

G

DISPL

AY

OSCILLATOR

8051CORE

PORT

2

PORT

1

PORT

0

PORT3

BUS

ROM RAM TIMER

A/ D

PWM

TXTINT

TO SWITCH S.C.FROM 4.43 TO 3.58 MHz

IIC BUSFOR EEPROM

SOUND STANDARDSWITCH

FROM RESESET CIRCUIT

VERTICALFLYBACK

HORIZONTAL FLYBACK PULSE

TO TDA884X

RGB REFERENCE VOLTAGE

PIP DETECTOR

NOT CONNECTED

NOT CONNECTED

TO CURRENT INTEGRATORVOLTAGE SINTESYS ONLY

TO X13

FRANCE STD. SWITCH

CTI DETECTOR

16 : 9 DETECTOR

SCART1 / SCART2 SWITCHSCART 1 / TVTO SCART 2 SWITCH

FRONT CINCH / SCART1 SWITCH



HEAD PHONES DETECTOR

STANDARD SWITCH

UHF SUPPLY (VOLTAGE SINTESYS ONLY)

TV ON / OFF SWITCH

TUNER SUPPLY (V.S. ONLY)

TUNER SUPPLY(V.S. ONLY)

TV / AV SWITCH

CVBS FROM ANTENNA

CVBS FROM SCART

DATA SLICER REF.PIN

T X T DATASLICER &ACQUISITIONSAA5553.DRW

E.G 22/ 04 / 2000


• Real-time packet 26 engine for processing accented (and other) characters

• Comprehensive Teletext language coverage

• Video signal quality detector.

Teletext Display

• 525-line and 625-line display

• 12 10 character matrix

• Double height, width and size On-Screen Display (OSD)

• Definable border colour

• Enhanced display features including meshing and shadowing

• 260 characters in mask programmed ROM

• Automatic FRAME output control with manual override

• RGB push-pull output to standard decoder ICs

• Stable display via slave synchronisation to horizontal sync and vertical sync.

Additional features of SAA529xA devices

• Wide Screen Signalling (WSS) bit decoding (line 23).

2 GENERAL DESCRIPTION

The SAA529x, SAA529xA and SAA549x family of microcontrollers are a derivative of the

Philips’ industry-standard 80C51 microcontroller and are intended for use as the central

control mechanism in a television receiver. They provide control functions for the television

system and include an integrated teletext function.

The teletext hardware has the capability of decoding and displaying both 525-line and 625-

line World System Teletext. The same display hardware is used both for Teletext and On-

Screen Display, which means that the display features give greater flexibility to

differentiate the TV set.

The family offers both 1 page and 10 page Teletext capability, in a range of ROM sizes.

Increasing display capability is offered from the SAA5290 to the SAA5497.

TELETEXT DECODER

Data slicer


The data slicer extracts the digital teletext data from the incoming analog waveform. This

is performed by sampling the CVBS waveform and processing the samples to extract the

teletext data and clock.

Acquisition timing

The acquisition timing is generated from a logic level positive-going composite sync signal

VCS. This signal is generated by a sync separator circuit which adaptively slices the sync

pulses. The acquisition clocking and timing are locked to the VCS signal using a digital

phase-locked-loop. The phase error in the acquisition phase-locked-loop is detected by a

signal quality circuit which disables acquisition if poor signal quality is detected.

Teletext acquisition

This family is capable of acquiring 625-line and 525-line World System Teletext see “World

System Teletext and Data Broadcasting System”. Teletext pages are identified by seven

numbers: magazine (page hundreds), page tens, page units, hours tens, hours units,

minutes tens and minutes units. The last four digits, hours and minutes, are known as the

subcode, and were originally intended to be time related, hence their names.

For the ten page device, each packet can only be written into one place in the teletext

RAM so if a page matches more than one of the page requests the data is written into

the area of memory corresponding to the lowest numbered matching page request.

At power-up each page request defaults to any page, hold on and error check Mode 0.

Rolling headers and time

When a new page has been requested it is conventional for the decoder to turn the header

row of the display green and to display each page header as it arrives until the correct

page has been found.

Error checking

Before teletext packets are written into the page memory they are error checked. The error

checking carried out depends on the packet number, the byte number, the error check

mode bits in the page request data and the TXT1.8 BIT bit. If an uncorrectable error

occurs in one of the Hamming checked addressing and control bytes in the page header

or in the Hamming checked bytes in packet 8/30, bit 4 of the byte written into the memory

is set, to act as an error flag to the software. If uncorrectable errors are detected in any

other Hamming checked data the byte is not written into the memory.


Packet 26 processing

One of the uses of packet 26 is to transmit characters which are not in the basic teletext

character set. The family automatically decodes packet 26 data and, if a character

corresponding to that being transmitted is available in the character set, automatically

writes the appropriate character code into the correct location in the teletext memory. This

is not a full implementation of the packet 26 specification allowed for in level 2 teletext, and

so is often referred to as level 1.5.

By convention, the packets 26 for a page are transmitted before the normal packets. To

prevent the default character data overwriting the packet 26 data the device incorporates a

mechanism which prevents packet 26 data from being overwritten.

Fastext detection

When a packet 27, designation code 0 is detected, whether or not it is acquired, the

TXT13.FASTEXT bit is set. If the device is receiving 525-line teletext, a packet X/0/27/0 is

required to set the flag. The flag can be reset by writing a logic 0 into the SFR bit.

When a packet 8/30 is detected, or a packet 4/30 when the device is receiving a 525-line

transmission, the TXT13.Pkt 8/30 is set. The flag can be reset by writing a logic 0 into the

SFR bit.

THE DISPLAY

Introduction

The capabilities of the display are based on the requirements of level 1 teletext, with some

enhancements for use with locally generated on screen displays. The display consists of

25 rows each of 40 characters, with the characters displayed being those from rows 0 to

24 of the basic page memory. If the TXT7.STATUS ROW TOP bit is set row 24 is

displayed at the top of the screen, followed by row 0, but normally memory rows are

displayed in numerical order. The teletext memory stores 8 bit character codes which

correspond to a number of displayable characters and control characters, which are

normally displayed as spaces. The character set of the device is described in more detail

below.

D PL

CZ

A HR

Y

EAST EUROPE CHARACTER SETNATIONAL OPTION FOR:

POLISHGERMANESTONIANSERBO-CROATCZECHSLOVAKIARUMANIAN

(OPTION BYTE 1BIT 3 SETTED TO 0

WEST EUROPE CHARACTER SETNATIONAL OPTION FOR:

ENGLISHGERMANSWEDISHITALIANFREANCHSPANISHTURKISH

F19 E&WCS.DRWE.G. 7/11/99

(OPTION BYTE 1BIT 6 SETTED TO 1

WEST EAST


Character matrix

Each character is defined by a matrix 12 pixels wide and 10 pixels high. When displayed,

each pixel is 1 12 s wide and 1 TV line, in each field, high.

East/West selection

In common with their predecessors, these devices store teletext pages as a series of 8 bit

character codes which are interpreted as either control codes (to change colour, invoke

flashing etc.) or displayable characters. When the control characters are excluded, this

gives an addressable set of 212 characters at any given time.

National option characters

The meanings of some character codes between 20H and 7FH depend on the C12 to C14

language control bits from the teletext page header.

The interpretation of the C12 to C14 language control bits is dependent on the East/West

bit.

On-Screen Display characters

Character codes 80H to 9FH are not addressed by the teletext decoding hardware. An

editor is available to allow these characters to be redefined by the customer. The

alternative character shapes in columns 8a and 9a (SAA549x only) can be displayed when

the ‘graphics’ serial attribute is set. This increases the number of customer definable

characters to 64.

Clock generator

The oscillator circuit is a single-stage inverting amplifier in a Pierce oscillator configuration.

The circuitry between XTALIN and XTALOUT is basically an inverter biased to the transfer

point. A crystal must be used as the feedback element to complete the oscillator circuitry.

It is operated in parallel resonance. XTALIN is the high gain amplifier input and XTALOUT

is the output. To drive the device externally XTALIN is driven from an external source and

XTALOUT is left open-circuit.

5251504948474645444342414039383736353433323130292827


SWT 16:9OSC. SWT.


AM/FMVDDMRESET

OSCOUTOSCIN

OSCGNDVDDTVDDA

VSYNCHSYNC

BLKRGB

RGBREFPIP STS

CORINT. TEST

FRAME

SAA5297A

QZ10012 MHz

MICRO & TXT PERIPHERALSTR500

TUNUNG VOLTAGETO PIN 2TUNER

TO X13

TR219

AMSOUNDFILTER

TR218

SOUND I.F.

12 V

12V

F204

5V

R174

R128TO PIN 4 IC 201

TO PIN 8 IC 201 R140 R141

TR110

TO PIN 10, 11 IC 200

FRON PIN 8 SCART 1

FROM PIN 8 SCART 2

5V

R146

TR111TR210

TR209

CVBS PIN 6IC 204

TR200

TR201

F576

F575

TO PIN 1IC 204


1 2 3 4 5 6 7 8 91011121314151617181920212223242526

TR2TO PIN 4IC 10

CVBSFROM SCART

TR203

TR107

TO STEREO NICAMMODULE

TO SWITC INT/EX SOUND

TV ON / OFF

TR 502

TR 501

TR503 TR211

CVBS FROMANTENNAT

O

TUNER

PIN 5

PIN 3

PIN 45V

TO CTI &16:9 MOULE

TR 109

TOPIN 35IC 204

4.43 MHz

3.58MHzTR206

TR 205

TR 208

IIC BUS

IIC BUSIRR100EEPROMIC 101

TR 1055V ST-BYTR 108

D 105

TO PIN 10IC 102

SOUND STDANDARD SWITCH

5 V R 106

D 108 D 102FLYBACK PULSEFROM EHT

VERTICALBLANKINGFROM PIN 8IC 5

TR 101

TR 102

TR 103

TO PIN23, 24, 25IC 204

R1675V

FOR VOLTAGE SISTETIZER ONLY

F19MTPER.DRWE.G. 24 /10 /99


SWT 16:9OSC. SWT.


AM/FMVDDMRESET

OSCOUTOSCIN

OSCGNDVDDTVSSA

VSYNCHSYNC

BLKRGB

RGBREFPIP STS

CORINT. TEST

FRAME

SAA 5553

QZ10012 MHz

MICRO & TXT PERIPHERALSTR500

TUNUNG VOLTAGETO PIN 2TUNER

TO X13

TR219

AMSOUNDFILTER

TR218

SOUND I.F.

12 V

12V

F204

5V

R174

R128TO PIN 4 IC 201

TO PIN 8 IC 201 R140 R141

TR110

TO PIN 10, 11 IC 200

FRON PIN 8 SCART 1

FROM PIN 8 SCART 2

5V

R146

TR111TR210

TR209

CVBS PIN 6IC 204

TR200

TR201

F576

F575

TO PIN 1IC 204


TR2TO PIN 4IC 10

CVBSFROM SCART

TR203

TR107

TO STEREO NICAMMODULE

TO SWITC INT/EX SOUND

TV ON / OFF

TR 502

TR 501

TR503 TR211

CVBS FROMANTENNAT

O

TUNER

PIN 5

PIN 3

PIN 45V

TO CTI &16:9 MOULE

TR 109

TOPIN 35IC 204

4.43 MHz

3.58MHzTR206

TR 205

TR 208

IIC BUS

IIC BUSIRR100EEPROMIC 101

TR 105

3,3 V

TR 108

D 105

TO PIN 10IC 102

SOUND STDANDARD SWITCH

5 V

D 108

D 102FLYBACK FROM EHT

VERTICALBLANKINGFROM PIN 8IC 5

TR 101

TR 102

TR 103

TO PIN23, 24, 25IC 204

R1675V

FOR VOLTAGE SISTETIZER ONLY

F19PAPER.DRWE.G. 22 / 04 /2000

1 2 3 4 5 6 7 8 91011121314151617181920212223242526

5251504948474645444342414039383736353433323130292827

5 V

3,3 V

2,5V

TR8

TR7

R40

R39

D5

PAINTER

SIGNAL

PROCESSING

VIDEO

SIGNAL

PROCESSING

VIDEO

EF

IIC TRANSRECEIVER

SOUNDPROCES.(MONO)

I.F. VIDEO

AGCAFC

DEM.IDENT

MSDPAL

(SECAM)NTSC

C.D. & RGB

MATRIXVIDEO

CONTROL

EXT RGBSWITCH& RGBDRIVE

SYNCPROCES.V. & H.

TIME BASE

TDA884XSIF

AUDEXT

NC

NC

PLLIF

IFVIDEO OUT

SCL

SDA

DECOUPLING

CHR.IN

EX.CVBS/Y IN

VP1

INT CVBS IN

GND

AUDIO OUT

DECOUPLING

EX. CVBS IN

BLKIN

B OUT

G OUT

R OUT

BCL/VG

R IN

G IN

B IN

RGB INSERT.

Y IN

Y OUT

1

2

34

5

6

78

9

10

1112

13

14

1516

17

1819

20

21

2223

24

25

2627

28

TR200

EFEFIICTR201

EF

EF

TR202

TR204

EF

TR203

TO PIN 33IC100CVBS FOR TXT

VIDEO INCINCH

19

8

1511716

TO PIN 9IC 100AV1STATUS

1

3

5

9

7

4

82

6

1/3 0F IC201LA7955

TR211

20

TO PIN 24IC 100(CVBS FOR TXT)

EFFROM PIN 6IC100 AV1 / AV2SWITCH

FROM PIN 7IC100 AV1 / TV SWITCHTO AV2

EF

20 19

12 V

TR212

CVBS IN

CVBS OUT

TVCVBS

CVBS IN

8

TO PIN 10IC 100AV2 STATUS

RGB AMPLIFIERMODULE

TO CRT

DECOUPLING

DEENPHASISAGC OUT

DECOPLING

I REF

VERT. RAMPEHT PROTEC.

IF IN 2

IF IN 1

V. DRIVE AV. DRIVE BE - W OUT

GND 2

PH. 1 FILTER

PH. 2 FILTERH. IN, S.C. OUT

HOR. OUT

DECOUPLINGCVBS 1 OUT

V P 2

DET FILTERX TAL 2

X TAL 1

S.C. REF OUT

R - Y INB - Y IN

R - Y OUT

B - Y OUT

56

55

5453

52

5150

49

48

4746

45

4443

42

4140

39

38

3736

35

3433

32

3130

29

8 V

TR208

TR206

TR205

4.43MHz

3.58MHz

3,57MHz

1

2

3

4

5

6

7

8

9

10

11

12

12 V

A10

C T I

&

4 : 3

TO

16 : 95 V

FROM PIN 52IC 100 4:3 TO 16:9SWITCH

8 V

FROM EHT

∫∫TR500

5 VTR501

TR503

TR502

FROM IC 100

PIN 14, 20, 21BAND SWITCHING

FROMPIN 51

IC 100

TR105

FROM PIN 1IC 100UV

FOR VOLTAGE SINTHESIS ONLY

IIC

1

2

3

4

5

6

7

8

9

10

11

UHF

VHF H

VHF L

F 19

VIDEO SIGNAL PATH

SCART 2

SCART 1

F19VIDEP.DRWE.G. 14 / 11 / 99


Reset signal

The externally applied RESET signal (active HIGH) is used to initialize the microcontroller

core, in addition to the teletext decoder. However, the teletext decoder incorporates a

separate internal reset function which is activated on the rising edge of the analog supply

pin, VDDA . The purpose of this internal reset circuit is to initialize the teletext decoder when

returning from the “text standby mode”.

TDA884X FAMILY SPECIFICATION

FEATURES

The following features are available in all IC’s:

• Multi-standard vision IF circuit with an alignment-freePLL demodulator without external

components

• Alignment-free multi-standard FM sound demodulator(4.5 MHz to 6.5 MHz)

• Audio switch

• Flexible source selection with CVBS switch andY(CVBS)/C input so that a comb filter can

be applied

• Integrated chrominance trap circuit

• Integrated luminance delay line

• Asymmetrical peaking in the luminance channel with a(defeatable) noise coring function

• Black stretching of non-standard CVBS or luminancesignals

• Integrated chroma band-pass filter with switchablecentre frequency

• Dynamic skin tone control circuit

• Blue stretch circuit which offsets colours near whitetowards blue

• RGB control circuit with “Continuous CathodeCalibration” and white point adjustment

• Possibility to insert a “blue back” option when no videosignal is available

• Horizontal synchronization with two control loops andalignment-free horizontal

oscillatoroptimised N2 application.Functionally the IC series is split up is 3 categories,

viz:

V. SYNCSEPARATOR

OUTPUT

IF & TUNER A G C

CHROMACLOCHE &BANDPASS

VIDEO IFAMPLIFIER

A F C

AUDIOLIMITER

VIDEOAMPLIFIER

VIDEOMUTE

AUDIOPLL DEM.

CVBS & Y/CSWITCH

BASE BANDCHROMADELAY LINE

RGB CONTROLAUTO CUT-OFF& OUTPUT

R-Y & B-YMATRIXSAT CONTR.BLACK STRETCHSKIN TINT CORR.RGB SWITCH

I.F IN

48

5

PLLFILTER

Y DELAY,C. TRAP,Y PEAKING

54TUNERAGC

TUNER T.O.P

53

49

AFW

AFAAFB

gating

PLLDEMOD.& VCO

VIDEOIDENT.

6

calibrationI.F. value

B.P.F.1 A 10 MHz

CVBS OUTPUT

SensitivityMODPos./Neg.

INTER-CARRIER IN

EXTERNAL AUDIO IN

2

1

55

Deenphasis

56

SoundDecoupling

EXTERNALAUDIO SWITCH

DEENPHASIS LINEInternalAudio

AVL SWITCH &VOLUME

AUDIO PREAMPLIFIER& MUTE

AVLDecoupling

MONO AUDIO OUTPUT

(45)

15A.F.

AVL

Volume

13 17 11 10 38

CVBS (int) INCVBS (ext) IN

CVBS / Y INCHROMA IN

CVBS OUT(comb filter)

ChromaLuma

To

Sync

PAL / NTSC SECAMDECODER

BURST PHASEDETECTOR & VCXO Fsc

33

34 35

36

28

29

30

Y

B-Y

R-Y

27

31

32

Y

B-Y

R-Y

23

24

25

R

G

B

INPUT

R

G

B

BlackCurrente

Input

26F.B.

SWT

GAI

SAT

MAT

DSA

AUTOSYSTEMIDENT.MANAGER

H. SYNCSEPARATOR

PHI 1DETECTOR

LINEOSCILL.

43 41 40

Phi 1filter

Flyback inSand CastleOut

LinePulseOut

VERTICALDEVIDER

V. syncH. sync

PHI 2LINE OUTS.C. GENER.

Phi 2filter

42

VERTICALSAWTOOTHGENERATOR

E - WGEOMETRY

19

20

21

18

45

E-WDRIVEVertical

Sawtooth Reference

51 52

46

47

50

VERTICALDRIVE

EHTOvervoltage

VerticalDriveOutput

XtalLoop filterPhaseDetector

CON

BRI

22

V- Guard &B.C. limiter

16

Secam Decoupling

Subcarrier

IICTRANS-RECEIVER

7 8

SCL SDA

IIC

GroundBandGapDecoupling Supply

8 V8 V Main Supply

9 12 37 14

TDA 8844

TDA8844BLDIA.DRWE.G. 17 /10 / 99


• Versions intended to be used in economy TV receiverswith all basic functions (envelope:

S-DIP 56 and QFP 64)

• Versions with additional features like E-W geometrycontrol, H-V zoom function and YUV

interface which are intended for TV receivers with 110° picture tubes(envelope: S-DIP 56)

• Versions which have in addition a second RGB inputwith saturation control and a second

CVBS output (envelope: QFP 64)

• Vertical count-down circuit

• Vertical driver optimised for DC-coupled vertical outputstages

GENERAL DESCRIPTION

The various versions of the TDA 884X/5X series areI 2 C-bus controlled single chip TV

processors which are

intended to be applied in PAL, NTSC, PAL/NTSC and multi-standard television receivers.

The N2 version is pin and application compatible with the N1 version, however,a new

feature has been added which makes the N2 more attractive. The IF PLL demodulator has

been replaced byan alignment-free IF PLL demodulator with internal VCO (no tuned circuit

required). The setting of the variousfrequencies (33.4, 33.9, 38, 38.9, 45,75 and 58.75

MHz) can be made via the I 2 C-bus.

Because of this difference the N2 version is compatiblewith the N1, however, N1 devices

cannot be used in an optimized N2 application

Functionally the IC series is split up is 3 categories, viz:

• Versions intended to be used in economy TV receivers with all basic functions (envelope:

S-DIP 56 and QFP 64)

• Versions with additional features like E-W geometry control, H-V zoom function and YUV

interface which areintended for TV receivers with 110° picture tubes (envelope: S-DIP 56)

• Versions which have in addition a second RGB input with saturation control and a

second CVBS output (envelope: QFP 64)

FUNCTIONAL DESCRIPTION

Vision IF amplifier

The IF-amplifier contains 3 ac-coupled control stages with a total gain control range which

is higher then 66 dB. The sensitivity of the circuit is comparable with that of modern


IF-IC’s.

The video signal is demodulated by means of an alignment-free PLL carrier regenerator

with an internalVCO. This VCO is calibrated by means of a digital control circuit which

uses the X-tal frequency of the colour decoder as a reference. The frequency setting for

the various standards (33.4, 33.9, 38, 38.9, 45.75 and 58.75 MHz) is realised via the I 2 C-

bus. To get a good performance for phase modulated carrier signals the control speed of

the PLL can be increased by means of the FFI bit.

The AFC output is generated by the digital control circuit of the IF-PLL demodulator and

can be read via the I 2 C-bus.

For fast search tuning systems the window of the AFC can be increased with a factor 3.

The setting is realised with the AFW bit. The AFC data is valid only when the horizontal

PLL is in lock (SL = 1)

Depending on the type the AGC-detector operates on top-sync level (single standard

versions) or on top sync and top white- level (multi standard versions). The demodulation

polarity is switched via the I 2 C-bus. The AGC detector time-constant capacitor is

connected externally. This mainly because of the flexibility of the application. The time-

constant of the AGC system during positive modulation is rather long to avoid visible

variations of the signal amplitude. To improve the speed of the AGC system a circuit has

been included which detects whether the AGC detector is activated every frame period.

When during 3 field periods no action detected the speed of the system is increased. For

signals without peak white information the system switches automatically to a gated black

level AGC. Because a black level clamp pulse is required for this way of operation the

circuit will only switch to black level AGC in the internal mode.

The circuits contain a video identification circuit which is independent of the

synchronisation circuit. Therefore search tuning is possible when the display section of the

receiver is used as a monitor. However, this ident circuit cannot be made as sensitive as

the slower sync ident circuit (SL) and we recommend to use both ident outputs to obtain a

reliable search system. The ident output is supplied to the tuning system via the I 2 C-bus.

The input of the identification circuit is connected to pin 13 (S-DIP 56 devices), the

“internal” CVBS input (see Fig.6).

This has the advantage that the ident circuit can also be made operative when a

scrambled signal is received (descrambler connected between pin 6 (IF video output) and

pin 13). A second advantage is that the ident circuit can be used when the IF amplifier is

not used (e.g. with built-in satellite tuners).


The video ident circuit can also be used to identify the selected CBVS or Y/C signal. The

switching between the 2 modes can be realised with the VIM bit.

Video switches

The circuits have two CVBS inputs (internal and external CVBS) and a Y/C input. When

the Y/C input is not required the Y input can be used as third CVBS input. The switch

configuration is given in Fig.6. The selection of the various sources is made via the I 2 C-

bus.

For the TDA 884X devices the video switch configuration is identical to the switch of the

TDA 8374/75 series. So the circuit has one CVBS output (amplitude of 2 VP-P for the

TDA884X series) and the I 2 C-bus control is similar to that of the TDA 8374/75. For the

TDA 885X IC’s the video switch circuit has a second output (amplitude of 1 VP-P ) which

can be set independently of the position of the first output. The input signal for the decoder

is also available on the CVBS1-output.

Therefore this signal can be used to drive the Teletext decoder. If S-VHS is selected for

one of the outputs the luminance and chrominance signals are added so that a CVBS

signal is obtained again.

Sound circuit

The sound bandpass and trap filters have to be connected externally. The filtered

intercarrier signal is fed to a limiter circuit and is demodulated by means of a PLL

demodulator. This PLL circuit tunes itself automatically to the incoming carrier signal so

that no adjustment is required.

The volume is controlled via the I 2 C-bus. The deemphasis capacitor has to be connected

externally. The non-controlled audio signal can be obtained from this pin (via a buffer

stage).

The FM demodulator can be muted via the I 2 C-bus. This function can be used to switch-

off the sound during a channel change so that high output peaks are prevented.

The TDA 8840/41/42/46 contain an Automatic Volume Levelling (AVL) circuit which

automatically stabilises the audio output signal to a certain level which can be set by the

viewer by means of the volume control. This function prevents big audio output fluctuations

due to variations of the modulation depth of the transmitter. The AVL function can be

activated via the I 2 C-bus.

Synchronisation circuit


The sync separator is preceded by a controlled amplifier which adjusts the sync pulse

amplitude to a fixed level. These pulses are fed to the slicing stage which is operating at

50% of the amplitude. The separated sync pulses are fed to the first phase detector and to

the coincidence detector. This coincidence detector is used to detect whether the line

oscillator is synchronised and can also be used for transmitter identification. This circuit

can be made less sensitive by means of the STM bit. This mode can be used during

search tuning to avoid that the tuning system will stop at very weak input signals. The first

PLL has a very high statical steepness so that the phase of the picture is independent of

the line frequency.

The horizontal output signal is generated by means of an oscillator which is running at

twice the line frequency. Its frequency is divided by 2 to lock the first control loop to the

incoming signal. The time-constant of the loop can be forced by the I 2 C-bus (fast or

slow). If required the IC can select the time-constant depending on the noise content of the

incoming video signal.

The free-running frequency of the oscillator is determined by a digital control circuit which

is locked to the reference signal of the colour decoder. When the IC is switched-on the

horizontal output signal is suppressed and the oscillator is calibrated as soon as all sub-

address bytes have been sent. When the frequency of the oscillator is correct the

horizontal drive signal is switched-on. To obtain a smooth switching-on and switching-off

behaviour of the horizontal output stage the horizontal output frequency is doubled during

switch-on and switch-off (slow start/stop). During that time the duty cycle of the output

pulse has such a value that maximum safety is obtained for the output stage.

To protect the horizontal output transistor the horizontal drive is immediately switched off

when a power-on-reset is detected. The drive signal is switched-on again when the normal

switch-on procedure is followed, i.e. all sub-address bytes must be sent and after

calibration the horizontal drive signal will be released again via the slow start procedure.

When the coincidence detector indicates an out-of-lock situation the calibration procedure

is repeated.

The circuit has a second control loop to generate the drive pulses for the horizontal driver

stage. The horizontal output is gated with the flyback pulse so that the horizontal output

transistor cannot be switched-on during the flyback time.

Via the I 2 C-bus adjustments can be made of the horizontal and vertical geometry. The

vertical sawtooth generator drives the vertical output drive circuit which has a differential

output current. For the E-W drive a single ended current output is available. A special


feature is the zoom function for both the horizontal and vertical deflection and the vertical

scroll function which are available in some versions. When the horizontal scan is reduced

to display 4:3 pictures on a 16:9 picture tube an accurate video blanking can be switched

on to obtain well defined edges on the screen.

Overvoltage conditions (X-ray protection) can be detected via the EHT tracking pin. When

an overvoltage condition is detected the horizontal output drive signal will be switched-off

via the slow stop procedure but it is also possible that the drive is not switched-off and that

just a protection indication is given in the I 2 C-bus output byte.

The choice is made via the input bit PRD. The IC’s have a second protection input on the

ϕ2 filter capacitor pin. When this input is activated the drive signal is switched-off

immediately and switched-on again via the slow start procedure. For this reason this

protection input can be used as “flash protection”.

The drive pulses for the vertical sawtooth generator are obtained from a vertical

countdown circuit. This countdown circuit has various windows depending on the incoming

signal (50 Hz or 60 Hz and standard or non standard). The countdown circuit can be

forced in various modes by means of the I 2 C-bus. During the insertion of RGB signals

the maximum vertical frequency is increased to 72 Hz so that the circuit can also

synchronise on signals with a higher vertical frequency like VGA. To obtain short switching

times of the countdown circuit during a channel change the divider can be forced in the

search window by means of the NCIN bit. The vertical deflection can be set in the de-

interlace mode via the I 2 C bus. To avoid damage of the picture tube when the vertical

deflection fails the guard output current of the TDA 8350/51 can be supplied to the beam

current limiting input. When a failure is detected the RGB-outputs are blanked and a bit is

set (NDF) in the status byte of the I 2 C-bus. When no vertical deflection output stage is

connected thisguard circuit will also blank the output signals. This can be overruled by

means of the EVG bit.

Chroma and luminance processing

The circuits contain a chroma bandpass and trap circuit. The filters are realised by means

of gyrator circuits and

they are automatically calibrated by comparing the tuning frequency with the X-tal

frequency of the decoder. The luminance delay line and the delay for the peaking circuit

are also realised by means of gyrator circuits. The centre frequency of the chroma

bandpass filter is switchable via the I 2 C-bus so that the performance can be optimised for


“front-end” signals and external CVBS signals. During SECAM reception the centre

frequency of the chroma trap is reduced to get a better suppression of the SECAM carrier

frequencies. All IC’s have a black stretcher circuit which corrects the black level for

incoming video signals which have a deviation between the black level and the blanking

level (back porch). The timeconstant for the black stretcher is realised internally.

The resolution of the peaking control DAC has been increased to 6 bits. All IC’s have a

defeatable coringfunction in the peaking circuit. Some of these IC’s have a YUV interface

(see table on page 2) so that picture improvement IC’s like the TDA 9170 (Contrast

improvement), TDA 9177 (Sharpness improvement) and TDA 4556/66 (CTI) can be

applied. When the CTI IC’s are applied it is possible to increase the gain of the luminance

channel by means of the GAI bit in subaddress 03 so that the resulting RGB output signals

are not affected.

Colour decoder

Depending on the IC type the colour decoder can decode PAL, PAL/NTSC or

PAL/NTSC/SECAM signals. The PAL/NTSC decoder contains an alignment-free X-tal

oscillator, a killer circuit and two colour difference demodulators. The 90° phase shift for

the reference signal is made internally.

The IC’s contain an Automatic Colour Limiting (ACL) circuit which is switchable via the I 2

C-bus and which prevents that oversaturation occurs when signals with a high chroma-to-

burst ratio are received. The ACL circuit is designed such that it only reduces the chroma

signal and not the burst signal. This has the advantage that the colour sensitivity is not

affected by this function. The SECAM decoder contains an auto-calibrating PLL

demodulator which has two references, viz: the 4.4 MHz sub-carrier frequency which is

obtained from the X-tal oscillator which is used to tune the PLL to the desired free-running

frequency and the bandgap reference to obtain the correct absolute value of the output

signal. The VCO of the PLL is calibrated during each vertical blanking period, when the IC

is in search or SECAM mode.

The frequency of the active X-tal is fed to the Fsc output (pin 33) and can be used to tune

an external comb filter (e.g. the SAA 4961).

The base-band delay line (TDA 4665 function) is integrated in the PAL/SECAM IC’s and in

the NTSC IC TDA 8846A. In the latter IC it improves the cross colour performance

(chroma comb filter). The demodulated colour difference signals are internally supplied to

the delay line. The colour difference matrix switches automatically between PAL/SECAM

and NTSC, however, it is also possible to fix the matrix in the PAL standard.


The “blue stretch” circuit is intended to shift colour near “white” with sufficient contrast

values towards more blue to obtain a brighter impression of the picture.

Which colour standard the IC’s can decode depends on the external X-tals. The X-tal to be

connected to pin 34 must have a frequency of 3.5 MHz (NTSC-M, PAL-M or PAL-N) and

pin 35 can handle X-tals with a frequency of 4.4 and 3.5 MHz. Because the X-tal frequency

is used to tune the line oscillator the value of the X-tal frequency must be given to the IC

via the I 2 C-bus. It is also possible to use the IC in the so called “Tri-norma” mode for

South America. In that case one X-tal must be connected to pin 34 and the other 2 to pin

35. The switching between the 2 latter X-tals must be done externally. This has the

consequence that the search loop of the decoder must be controlled by the µ-computer.

To prevent calibration problems of the horizontal oscillator the external switching between

the 2 X-tals should be carried out when the oscillator is forced to pin 34. For a reliable

calibration of the horizontal oscillator it is very important that the X-tal indication bits (XA

and XB) are not corrupted. For this reason the X-tal bits can be read in the output bytes so

that the software can check the I 2 C-bus transmission.

Under bad-signal conditions (e.g. VCR-playback in feature mode), it may occur that the

colour killer is activated although the colour PLL is still in lock. When this killing action is

not wanted it is possible to overrule the colour killer by forcing the colour decoder to the

required standard and to activate the FCO-bit (Forced Colour On) in the control-5

subaddress.

The IC’s contain a so-called “Dynamic skin tone (flesh) control” feature. This function is

realised in the YUV domain by detecting the colours near to the skin tone. The correction

angle can be controlled via the I 2 C-bus.

RGB output circuit and black-current stabilisation

The colour-difference signals are matrixed with the luminance signal to obtain the RGB-

signals. The TDA 884X devices have one (linear) RGB input. This RGB signal can be

controlled on contrast and brightness (like TDA 8374/75). By means of the IE1 bit the

insertion blanking can be switched on or off. Via the IN1 bit it can be read whether the

insertion pin has a high level or not.

The TDA 885X IC’s have an additional RGB input. This RGB signal can be controlled on

contrast, saturation and brightness. The insertion blanking of this input can be switched-off

by means of the IE2 bit. Via the IN2 bit it can be read whether the insertion pin has a high

level or not.


The output signal has an amplitude of about 2 volts black-to-white at nominal input signals

and nominal settings of the controls. To increase the flexibility of the IC it is possible to

insert OSD and/or teletext signals directly at the RGB outputs. This insertion mode is

controlled via the insertion input (pin 26 in the S-DIP 56- and pin 38 in the QFP-64

envelope). This blanking action at the RGB outputs has some delay which must be

compensated externally.

To obtain an accurate biasing of the picture tube a “Continuous Cathode Calibration”

circuit has been developed. This function is realised by means of a 2-point black level

stabilisation circuit. By inserting 2 test levels for each gun and comparing the resulting

cathode currents with 2 different reference currents the influence of the picture tube

parameters like the spread in cut-off voltage can be eliminated.

This 2-point stabilisation is based on the principle that the ratio between the cathode

currents is coupled to the ratio between the drive voltages according to:

[ Iki / Ik2 ] = [ Vdr1 / Vdr2 ]

The feedback loop makes the ratio between the cathode currents Ik1 and Ik2 equal to the

ratio between the reference currents (which are internally fixed) by changing the (black)

level and the amplitude of the RGB output signals via 2 converging loops. The system

operates in such a way that the black level of the drive signal is controlled to the cut-off

point of the gun so that a very good grey scale tracking is obtained. The accuracy of the

adjustment of the black level is just dependent on the ratio of internal currents and these

can be made very accurately in integrated circuits. An additional advantage of the 2-point

measurement is that the control system makes the absolute value of Ik1 and Ik2 identical

to the internal reference currents. Because this adjustment is obtained by means of an

adaption of the gain of the RGB control stage this control stabilises the gain of the

complete channel (RGB output stage and cathode characteristic).

As a result variations in the gain figures during life will be compensated by this 2-point

loop.

An important property of the 2-point stabilisation is that the off-set as well as the gain of

the RGB path is adjusted by the feedback loop. Hence the maximum drive voltage for the

cathode is fixed by the relation between the test pulses, the reference current and the

relative gain setting of the 3 channels. This has the consequence that the drive level of the

CRT cannot be adjusted by adapting the gain of the RGB output stage. Because different

picture tubes may require different drive levels the typical “cathode drive level” amplitude

can be adjusted by means of an I 2 C-bus setting. Dependent on the chosen cathode drive


level the typical gain of the RGB output stages can be fixed taking into account the drive

capability of the RGB outputs (pins 19 to 21). More details about the design will be given in

the application report.

The measurement of the “high” and the “low” current of the 2- point stabilisation circuit is

carried out in 2 consecutive fields. The leakage current is measured in each field. The

maximum allowable leakage current is 100 µA When the TV receiver is switched-on the

RGB output signals are blanked and the black current loop will try to set the right picture

tube bias levels. Via the AST bit a choice can be made between automatic start-up or a

start-up via the µ-processor. In the automatic mode the RGB drive signals are switched-on

as soon as the black current loop

has been stabilised. In the other mode the BCF bit is set to 0 when the loop is stabilised.

The RGB drive can than be switched-on by setting the AST bit to 0. In the latter mod some

delay can be introduced between the setting of the BCF bit and the switching of the AST

bit so that switch-on effects can be suppressed. It is also possible to start-up the devices

with a fixed internal delay (as with the TDA 837X and the TDA884X/5X N1). This mode is

activated with the BCO bit.

The vertical blanking is adapted to the incoming CVBS signal (50 Hz or 60 Hz). When the

flyback time of the vertical output stage is longer than the 60 Hz blanking time the blanking

can be increased to the same value as that of the 50 Hz blanking. This can be set by

means of the LBM bit.

For an easy (manual) adjustment of the Vg2 control voltage the VSD bit is available. When

this bit is activated the black current loop is switched-off, a fixed black level is inserted at

the RGB outputs and the vertical scan is switched-off so that a horizontal line is displayed

on the screen. This line can be used as indicator for the Vg2 adjustment. Because of the

different requirements for the optimum cut-off voltage of the picture tube the RGB output

level is adjustable when the VSD bit is activated. The control range is 2.5 ± 0.7 V and can

be controlled via the brightness control DAC. It is possible to insert a so called “blue back”

back-ground level when no video is available. This feature can be activated via the BB bit

in the control2 subaddress.

EF

IIC TRANSRECEIVER

SOUNDPROCES.(MONO)

I.F. VIDEO

AGCAFC

DEM.IDENT

MSDPAL

(SECAM)NTSC

C.D. & RGB

MATRIXVIDEO

CONTROL

EXT RGBSWITCH& RGBDRIVE

SYNCPROCES.V. & H.

TIME BASE

TDA884XSIF

AUDEXT

NC

NC

PLLIF

IFVIDEO OUT

SCL

SDA

DECOUPLING

CHR.IN

EX.CVBS/Y IN

VP1

INT CVBS IN

GND

AUDIO OUT

DECOUPLING

EX. CVBS IN

BLKIN

B OUT

G OUT

R OUT

BCL/VG

R IN

G IN

B IN

RGB INSERT.

Y IN

Y OUT

1

2

34

5

6

78

9

10

1112

13

14

1516

17

1819

20

21

2223

24

25

2627

28

TR200

EFEFIICTR201

EF

EF

TR202

TR204

EF

TR203

TO PIN 33IC100CVBS FOR TXT

VIDEO INCINCH

19

8

1511716

TO PIN 9IC 100AV1STATUS

1

3

5

9

7

4

82

6

1/3 0F IC201LA7955

TR211

20

TO PIN 24IC 100(CVBS FOR TXT)

EFFROM PIN 6IC100 AV1 / AV2SWITCH

FROM PIN 7IC100 AV1 / TV SWITCHTO AV2

EF

20 19

12 V

TR212

CVBS IN

CVBS OUT

TVCVBS

CVBS IN

8

TO PIN 10IC 100AV2 STATUS

RGB AMPLIFIERMODULE

TO CRT

DECOUPLING

DEENPHASISAGC OUT

DECOPLING

I REF

VERT. RAMPEHT PROTEC.

IF IN 2

IF IN 1

V. DRIVE AV. DRIVE BE - W OUT

GND 2

PH. 1 FILTER

PH. 2 FILTERH. IN, S.C. OUT

HOR. OUT

DECOUPLINGCVBS 1 OUT

V P 2

DET FILTERX TAL 2

X TAL 1

S.C. REF OUT

R - Y INB - Y IN

R - Y OUT

B - Y OUT

56

55

5453

52

5150

49

48

4746

45

4443

42

4140

39

38

3736

35

3433

32

3130

29

8 V

TR208

TR206

TR205

4.43MHz

3.58MHz

3,57MHz

1

2

3

4

5

6

7

8

9

10

11

12

12 V

A10

C T I

&

4 : 3

TO

16 : 95 V

FROM PIN 52IC 100 4:3 TO 16:9SWITCH

8 V

FROM EHT

∫∫TR500

5 VTR501

TR503

TR502

FROM IC 100

PIN 14, 20, 21BAND SWITCHING

FROMPIN 51

IC 100

TR105

FROM PIN 1IC 100UV

FOR VOLTAGE SINTHESIS ONLY

IIC

1

2

3

4

5

6

7

8

9

10

11

UHF

VHF H

VHF L

F 19

VIDEO SIGNAL PATH

SCART 2

SCART 1

F19VIDEP.DRWE.G. 14 / 11 / 99

200 V12 V

R613R614R615

R215R216R217

FASTBLK.IN

RGBOUT

R17,R18,R19

3 X

D800, D801, D802

R600

RGBIN

RGB IN FROM SCART

E.F.

STV 5112

1/3/4

6/11/14

9/12/15

7/10/13

132

4 / 5 / 6

TO G1 TRC

TORGBKATODE

IC204 TDA884X

26 19/20/21 1823/24/25

F19 RGB AMPLIFIER

F19 RGBCO.DRWE.G. 14 / 11 /99

R604R605R606

52

F 19 FEATURE MODULE

Colour Transient Improvment

&

4 : 3 to 16 : 9 Signal Processing

SAA4981 16:9 TO 4:3 PROCESSOR Pagina 1 di 3 e.g.SAA4981R.doc

SAA4981

Monolithic integrated 16 : 9Compressor

FEATURES

• Fixed horizontal compression by a factor of 4 ¤3 for most video standards

• Three fixed screen positions (left, centre and right)

• 5 MHz bandwidth

• Bypass function

• Inputs for luminance and chrominance of side panels

• Standard video inputs and outputs (Y, (Β-Y) and (Ρ-Y))

• Horizontal and vertical sync signals are not processed

• Pre filters and post filters on chip.

GENERAL DESCRIPTION

The integrated 16 : 9 compressor is an IC which compresses the active part of a video line

by a factor of 4 ¤3 from, for example, 52 ms to 39ms. This is necessary to display 4:3

video software on a 16 : 9 tube in the correctproportion. The capacitively coupled video

inputs are Y, (Β-Y) and (Ρ-Y).

The synchronisation input HREF is a line frequencyreference signal. The bandwidth of the

IC is up to 5 MHz and the signal delay is realized with SC Line Memories (Switched

Capacitors Line Memories). The output of the 16 : 9 compressor also has the format Y,

(Β Y) and (Ρ-Y) and provides the following two possibilities:

1. Bypass function (the input signal is not compressed)

2. Compressed video by a factor of 4 ¤3 with three different fixed screen positions (left,

centre and right). The luminance and chrominance of the side panels are determined by

the external signals YSIDE, BYSIDE and RYSIDE.

The horizontal compression is a time discrete and amplitude continuous signal processing.

This provides pre and post filters which are realized on-chip.


1995O

ct053

Philips S

emiconductors

Prelim

inary specification

Monolithic integrated 16 : 9 com

pressorS

AA

4981

BLO

CK

DIA

GR

AM

hand

book

, ful

l pag

ewid

th3

3

SC LINE MEMORY

SC LINE MEMORY

MUX SC LINE

MEMORIES

6.7 MHz LOW-PASS FILTER

5 MHz LOW-PASS FILTER

CLAMPMUX Y

SC LINE MEMORY

SC LINE MEMORY

MUX SC LINE

MEMORIES



CLAMPMUX BY

SC LINE MEMORY

SC LINE MEMORY

MUX SC LINE

MEMORIES



HORIZONTAL SEPARATION

54 MHz PLL

CLAMP

MUX RY

C1 C2 C3

C1 C2 C3

C1 C2 C3

YSIDEBYSIDE

RYSIDE

CONTROLLER

CLAMP REFERENCE

TEST CTRL2

CTRL1 CTRL3CLMY

CLMBY

CLMRYBGREF

CLAOUT

C1

C2

C3

YOUT

(B-Y)OUT

(R-Y)OUT

18

17

16

YIN

(B-Y)IN

(R-Y)IN

HREF6

21

22

23

11 1 2 3 24 5 15 14 1310912

20 19 8 7 4

VCCA VEEA VCCD VEED SUB

SAA4981

MHA277

Fig.1 Block diagram.


Applicable video standards

The integrated 16 : 9 compressor can be used for the following video standards; B, C, D,

G, H, I, K, K1, L, M and N. standards D, I, K, K1 and L will show a reducedvideo bandwidth

above 5 MHz.

Clamping circuit

The clamping circuits clamp the video input signals Y, (Β-Y) and (Ρ-Y) to the DC level of

the clamp reference signal fed from the clamp reference circuit. This is necessary to

ensure that the input signals are in the correct input voltage range for the 5 MHz low-pass

filters and the SC line memories.

Internal pre filters

Before the signals are sampled in the time discrete and amplitude continuous area, low-

pass filtering is necessary to avoid any aliasing. Even if the inputs have already been low-

pass filtered further filtering is advantageous for the electromagnetic compatibility (EMC).

The same transfer function is used for all three low-pass filters because of the same

bandwidth for the luminance and chrominance signals (up to 5 MHz)

SC line memories

After the low-pass filters the input signals are fed to the SC line memories. The signals are

sampled at a clock frequency of 13.5 MHz. One video line later the signals are read with a

clock frequency of 18 MHz in the compression mode. The result of the different clock

frequencies is a horizontal compression by a factor of 4 ¤3 . The clocks and the horizontal

starting pulses for the SC line memories are fed from the controller.

Two line memories are required for each signal path because in the compression mode, in

one video line the signals are sampled to the SC line memories with 13.5 MHz and one

video line later the signals are read with 18 MHz. In the bypass mode, via the SC line

memories, in one video line the signals are sampled with 13.5 MHz and one video line

later the signals are read with 13.5 MHz.

The SC line memories are suitable for signals with a bandwidth up to 5 MHz. With a

multiplexer (MUX) behind the SC line memories, the sampled video signal is connected to

the internal post filters.

Output multiplexer MUX Y, MUX (Β-Y) and MUX (Ρ-Y)


The output multiplexers are controlled via C1 and C2 fed from the controller. The

multiplexers are used to connect one of the four input signals to the output and, also,

enable fast switching.

The input signals of the multiplexers for one component

• The output signal of the post filter

• The uncompressed signal after the input clamping

• The clamping reference signal

• The signal for the side panel determined by YSIDE, BYSIDE and RYSIDE.

The horizontal separation circuit

The 54 MHz horizontal PLL is locked to the positive edge of the digital HREF signal, which

is generated in the positive edge of the burst key of a sandcastle signal.

54 MHz horizontal PLL

The 13.5 MHz clock frequency for the sampling clock and the 18 MHz clock frequency for

the reading clock are generated in the 54 MHz horizontal PLL. The 13.5 MHzclock and the

18 MHz clock are line locked.

Clamp reference

Reference voltages are generated In the clamp reference block. These DC signals are

used in the clamping circuits as input signals for the output multiplexers and as reference

voltages for the SC line memories. Four external capacitors at the pins CLMY , CLMBY ,

CLMRY and BGREF respectively are necessary to provide smoothing for the reference

voltages. A black level reference signal is available at CLAOUT.

Controller

The controller generates the clocks and the horizontal start signals for the SC line

memories and, also, the control signals for the output multiplexers. The timing for the start

reading signal for three different screen positions (left, centre and right) and the control

signals for the multiplexers (C1 and C2) is fixed. For the uncompressed signals a bypass

via the SC line memories and a bypass not via the SC line memories is available. When

the signals do not pass the line memories, the frequencyresponse is not affected by the si-

function.

1995 Oct 05 7

Philips Semiconductors Preliminary specification

Monolithic integrated 16 : 9 compressor SAA4981

Fig.3 Horizontal timing.

(1) Nominal timing for a 52 µs active video signal to generate a centred compressed video signal.

(2) Worst case picture position for a 52 µs active video signal to generate no visible blanking between side panels and compressed video.

handbook, full pagewidth HREF

sampled video

compressed video

(centre position)

side

panel

side

panel

side

panel

compressed video

(left position)

bypassed video

bypassed video

(bypass via the Line Memories)

(full bypass not through the Line Memories)

side

panel

64 µs1.5 µs

1.5 µs

49 µs (used for compression)

52 µs

36.75 µs

6.3 µs

(1)

(2)

(1)

(2)(2)

(2)

compressed video

(right position)

MHA278

TDA4566 CTI Pagina 1 di 1e.g.TDA4566R.doc

TDA4566

Colour transient improvement circuit

GENERAL DESCRIPTION

The TDA4566 is a monolithic integrated circuit for colour-transient improvement (CTI) and

luminance delay line in gyrator technique in colour television receivers.

Features

• Colour transient improvement for colour difference signals (R-Y) and (B-Y) with transient

detecting-, storage- and switching stages resulting in high transients of colour difference

output signals

• A luminance signal path (Y) which substitutes the conventional Y-delay coil with an

integrated Y-delay line

• Switchable delay time from 550 ns to 820 ns in steps of 90 ns and additional fine

adjustment of 37 ns

• Two Y output signals; one of 180 ns less delay

March

19913

Philips S

emiconductors

Prelim

inary specification

Colour transient im

provement circuit

TD

A4566Fig.1 Block diagram.

12 V

5 V

IC 1 SAA4981

CLAMPLPF LPF

MUX MUXLINE MEMORY

LINE MEMORY

CLAMPLPF LPF

MUX MUXLINE MEMORY

LINE MEMORY

CLAMPLPF LPF

MUX MUXLINE MEMORY

LINE MEMORY

HOR.SEPAR.

54 MHzPLL

CONTROLLERCLAMP

REFERENCE

23

22

21

6

18

17

16

15

14

13

1247 20 19 1 2 3 524

5 V

20 8

DUAL MONOSTABLE MULTIVIBRATOR

10M.M. M.M.

15

14

8 V

13

16R4

C10

EF

3 5168 1

C9

R2

T2

2

IC 4 HEF 4538

S.C INPUT

H REF

Y

R-Y

B-Y

R-Y

B-Y

Y

11 10 9

TR1

IC2 TDA4566

CLAMP

dV/dt

dV/dt

INTEGRATOR& PULSEFORMER

GYRATORDELAY CELLS

7 x 90 nst = 180 ns

SWT. &STORE

SWT. &STORE

THESHOLD SWT.

17

1

2 3 4 5 6 9 18

15 13 14 10

12

11

8

7

Y OUT

R-Y OUT

B-YOUT

16:9 TO 4:3 SWITCH SIGNAL

7

4

3

10

12

8

9

6

1

2

11

5

12 V8 V

D1

F19 CTI & 16:9 TO 4 : 3 COMPRESSOR

JS 7JS 6JS 5

note:If CTI ( IC 2 TDA4566 IS NOT PRESENT THAN JS 5, JS 6 & JS7MUST BE INSERTED

F19FEAT.DRWE.G. 12/12/99

SCANNING

SECTION

SCANNING

SECTION

TDA8351 VERTICAL OUTPUT Pagina 1 di 2 e.g.TDA8351R

TDA8351

DC-coupled vertical deflectionCircuit

FEATURES

Few external components

Highly efficient fully DC-coupled vertical output bridge circuit

Vertical flyback switch

Guard circuit

Protection against:

• short-circuit of the output pins (7 and 4)

• short-circuit of the output pins to VP

• Temperature (thermal) protection

• High EMC immunity because of common mode inputs

• A guard signal in zoom mode.

•

GENERAL DESCRIPTION

The TDA8351 is a power circuit for use in 9and 11 colour deflection systems for

field frequencies of 50 to 120 Hz. The circuit provides a DC driven vertical deflection

output circuit, operating as a highly efficient class G system.


The vertical driver circuit is a bridge configuration. The deflection coil is connected

between the output amplifiers, which are driven in phase opposition. An external resistor

(RM ) connected in series with the deflection coil provides internal feedback information.

The differential input circuit is voltage driven. The input circuit has been adapted to enable

it to be used with the TDA9150, TDA9151B, TDA9160A, TDA9162, TDA8366 and

TDA8376 which deliver symmetrical current signals. An external resistor (RCON )

connected between the differential input determines the output current through the

deflection coil.

TDA8351 VERTICAL OUTPUT Pagina 2 di 2 e.g.TDA8351R

The relationship between the differential input current and the output current is defined by:

Idiff RCON =Icoil RM .

The output current is adjustable from 0.5 A (p-p) to 3 A(p-p) by varying RM . The maximum

input differential voltage is 1.8 V. In the application it is recommended that Vdiff = 1.5 V

(typ). This is recommended because of the spread of input current and the spread in the

value of RCON .

The flyback voltage is determined by an additional supply voltage VFB . The principle of

operating with two supply voltages (class G) makes it possible to fix the supply voltage VP

optimum for the scan voltage and the second supply voltage VFB optimum for the flyback

voltage. Using this method, very high efficiency is achieved.

The supply voltage VFB is almost totally available as flyback voltage across the coil, this

being possible due to the absence of a decoupling capacitor (not necessary, due to the

bridge configuration). The output circuit is fully protected against the following:

thermal protection

• short-circuit protection of the output pins (pins 4 and 7)

• short-circuit of the output pins to VP .

A guard circuit VO(guard) is provided. The guard circuit is activated at the following

conditions:

• during flyback

• during short-circuit of the coil and during short-circuit of the output pins (pins 4 and 7)

to VP or ground

• during open loop

• when the thermal protection is activated. This signal can be used for blanking the

picture tubescreen.

January 1995 3


DC-coupled vertical deflection circuit TDA8351

ORDERING INFORMATION

BLOCK DIAGRAM

TYPE NUMBERPACKAGE

NAME DESCRIPTION VERSION

TDA8351 SIL9P plastic single-in-line power package; 9 leads SOT131-2


handbook, full pagewidth

MBC988- 1

5

V

9VI(fb)

VO(B)

VO(A)VO(A)

VO(B)

VO(guard)

7

4

VFB

VP

VP

VP

VP

83 6

1

2

I drive(pos)

I drive(neg)

TDA8351

GND

CURRENTSOURCE

IS

I

I

S

T

IT

January 1995 4


DC-coupled vertical deflection circuit TDA8351

PINNING

SYMBOL PIN DESCRIPTION

Idrive(pos) 1 input power-stage (positive);includes II(sb) signal bias

Idrive(neg) 2 input power-stage (negative);includes II(sb) signal bias

VP 3 operating supply voltage

VO(B) 4 output voltage B

GND 5 ground

VFB 6 input flyback supply voltage

VO(A) 7 output voltage A

VO(guard) 8 guard output voltage

VI(fb) 9 input feedback voltage

Fig.2 Pin configuration.

Metal block connected to substrate pin 5.

Metal on back.

handbook, 2 columns1

2

3

4

5

6

7

8

9

TDA8351

I drive(pos)

VI(fb)

VP

VO(B)

GND

V FB

VO(A)

VO(guard)

I drive(neg)

MBC989


The vertical driver circuit is a bridge configuration. Thedeflection coil is connected between the output amplifiers,which are driven in phase opposition. An external resistor(RM) connected in series with the deflection coil providesinternal feedback information. The differential input circuitis voltage driven. The input circuit has been adapted toenable it to be used with the TDA9150, TDA9151B,TDA9160A, TDA9162, TDA8366 and TDA8376 whichdeliver symmetrical current signals. An external resistor(RCON) connected between the differential inputdetermines the output current through the deflection coil.The relationship between the differential input current andthe output current is defined by: Idiff × RCON = Icoil × RM.The output current is adjustable from 0.5 A (p-p) to 3 A(p-p) by varying RM. The maximum input differentialvoltage is 1.8 V. In the application it is recommended thatVdiff = 1.5 V (typ). This is recommended because of thespread of input current and the spread in the value ofRCON.

The flyback voltage is determined by an additional supplyvoltage VFB. The principle of operating with two supplyvoltages (class G) makes it possible to fix the supplyvoltage VP optimum for the scan voltage and the secondsupply voltage VFB optimum for the flyback voltage. Usingthis method, very high efficiency is achieved.

The supply voltage VFB is almost totally available asflyback voltage across the coil, this being possible due tothe absence of a decoupling capacitor (not necessary, dueto the bridge configuration). The output circuit is fullyprotected against the following:

• thermal protection

• short-circuit protection of the output pins (pins 4 and 7)

• short-circuit of the output pins to VP.

A guard circuit VO(guard) is provided. The guard circuit isactivated at the following conditions:

• during flyback

• during short-circuit of the coil and during short-circuit ofthe output pins (pins 4 and 7) to VP or ground

• during open loop

• when the thermal protection is activated.

This signal can be used for blanking the picture tubescreen.

EHT

FOCUS

VG2

C154

HEATER

VOLTAGE

SERVICEFLYBACKPULSE TO:PIPTUNINGOSD SYNC

PIN 3TDA8351

T 3

146 V

200 VVIDEO

SUPPLAYLINE

YOKE

20 mS

64 /uS

D 53

F19 VERTICAL & LINE OUTPUTPLUS E-W CORRECTION

9

3

F19 V&HDF.DRWE.G. 27/12/99

1

11

12

10

16 V C51

7

6

5 5

8

TDA8844PIN22PIN 50

B.C.L.

EHT P.

R35

PIN6TDA8351

C52

50 V

LINEARITYL22

L26

L25

L20

D24

D25

C71TR12

BUK474

TR18BU508D

4

3

2

EF

TR207

TR15

28 V

T 2

VERTICALYOKE

1

2

3

4

5

6

7

8

9

IC 5

T

DA

8351

47 46 45 40

IC 204TDA8844

15

14

10

11

2

1

12

13

AUDIO CINCH IN

FROM PIN8 IC 100 SCART/CINCH SWITCH

IC200 (2/3) HEF 4053

IC 400 TDA2613

9 8 7 6 5 4 3 2 1

28 V

6 2

TR525

55

2

15

IC 204

TDA844X

1 3

TR575

EXT. IN

SCARTOUT

AUDIO OUT

SCART 1

TR110

F19 AUDIO MONO SIGNAL PATH

EF

EF

1SOUNDIF IN

TR201TR202

FROM PIN 12IC100SAA5297A

TR209

F575

F576

8 V

R208

R239

R242

TR210

F19AMSPH.DRWE.G. 29/12799

CVBS & INTERCARRIER OUT

6


TDA 9870A & TDA9875A MAIN CHARACTERISTICS

FEATURES

Demodulator and decoder section

• Sound IF (SIF) input switch e.g. to select between terrestrial TV SIF and SAT SIF

sources SIF AGC with 24 dB control range SIF 8-bit Analog-to-Digital Converter

(ADC)

• DQPSK demodulation for different standards, simultaneously with 1-channel FM

demodulation NICAM decoding (B/G, I and L standard) Two-carrier

multistandard FM demodulation (B/G, D/K and M standard

• Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite

sound Optional AM demodulation for system L, simultaneously with NICAM

• Programmable identification (B/G, D/K and M standard) and different identification

times.

• DSP section

• Digital crossbar switch for all digital signal sources and destinations

• Control of volume, balance, contour, bass, treble,

• pseudo stereo, spatial, bass boost and soft-mute

• Plop-free volume control

• Automatic Volume Level (AVL) control

• Adaptive de-emphasis for satellite

• Programmable beeper

• Monitor selection for FM/AM DC values and signals, with peak detection option I 2 S-bus

interface for a feature extension (e.g. Dolby surround) with matrix, level adjust and

mute.

• Analog audio section

• Analog crossbar switch with inputs for mono and stereo


• (also applicable as SCART 3 input), SCART 1

• input/output, SCART 2 input/output and line output

• User defined full-level/3 dB scaling for SCART outputs

• Output selection of mono, stereo, dual A/B, dual A or Dual B

• 20 kHz bandwidth for SCART-to-SCART copies

• Standby mode with functionality for SCART copies

• Dual audio digital-to-analog converter from DSP to analog crossbar switch, bandwidth

15 kHz Dual audio ADC from analog inputs to DSP Two dual audio Digital-to-

Analog Converters (DACs) for loudspeaker (Main) and headphone (Auxiliary) outputs;

also applicable for L, R, C and S in the Dolby Pro Logic mode with feature extension.

GENERAL DESCRIPTION

The TDA9875A is a single-chip Digital TV Sound Processor (DTVSP) for analog and

digital multi-channel sound systems in TV sets and satellite receivers.

Supported standards

The multistandard/multi-stereo capability of the TDA9875A is mainly of interest in Europe,

but also in Hong Kong/Peoples Republic of China and South East Asia. This includes

B/G, D/K, I, M and L standard. In other application areas there exists only subsets of those

standard combinations otherwise only single standards are transmitted.

M standard is transmitted in Europe by the American Forces Network (AFN) with European

channel spacing (7 MHz VHF, 8 MHz UHF) and monaural sound. The AM sound of L/L’ standard

is normally demodulated in the 1st sound IF. The resulting AF signal has to be entered into the

mono audio input of the TDA9875A. A second possibility is to use the internal AM demodulator

stage, however this gives limited performance. Korea has a stereo sound system similar to Europe

and is supported by the TDA9875A. Differences include deviation, modulation contents and

identification. It is based on M standard.


Description of the demodulator and decoder section

SIF INPUT


Two input pins are provided, SIF1 e.g. for terrestrial TV and SIF2 e.g. for a satellite tuner.

For higher SIF signal levels the SIF input can be attenuated with an internal switchable

10 dB resistor divider. As no specific filters are integrated, both inputs have the same

specification giving flexibility in application. The selected signal is passed through an AGC

circuit and then digitized by an 8-bit ADC operating at 24.576 MHz.

AGC

The gain of the AGC amplifier is controlled from the ADC output by means of a digital

control loop employing hysteresis. The AGC has a fast attack behaviour to prevent ADC

overloads and a slow decay behaviour to prevent AGC oscillations. For AM demodulation

the AGC must be switched off. When switched off, the control loop is reset and fixed gain

settings can be chosen from Table 15 (subaddress 0).

MIXER

The digitized input signal is fed to the mixers, which mix one or both input sound carriers

down to zero IF. A 24-bit control word for each carrier sets the required frequency. Access

to the mixer control word registers is via the I 2 C-bus. When receiving NICAM programs,

a feedback signal is added to the control word of the second carrier mixer to establish a

carrier-frequency loop.

FM AND AM DEMODULATION

An FM or AM input signal is fed via a band-limiting filter to a demodulator that can be used

for either FM or AM demodulation. Apart from the standard (fixed) de-emphasis

characteristic, an adaptive de-emphasis is available for encoded satellite programs. A

stereo decoder recovers the left and right signal channels from the demodulated sound

carriers. Both the European and Korean stereo systems are supported.

FM IDENTIFICATION

The identification of the FM sound mode is performed by AM synchronous demodulation of

the pilot signal and narrow-band detection of the identification frequencies. The result is

available via the I 2 C-bus interface. A selection can be made via the I 2 C-bus for B/G,

D/K and M standard and for three different modes that represent different trade-offs

between speed and reliability of identification.

NICAM DEMODULATION

The NICAM signal is transmitted in a DQPSK code at a bit rate of 728 kbit/s. The NICAM

demodulator performs DQPSK demodulation and feeds the resulting bitstream and clock

signal onto the NICAM decoder and, for evaluation purposes, to PCLK (pin 1) and NICAM


(pin 2). A timing loop controls the frequency of the crystal oscillator to lock the sampling

rate to the symbol timing of the NICAM data.

NICAM DECODER

The device performs all decoding functions in accordance with the “EBU NICAM 728

specification”. After locking to the frame alignment word, the data is descrambled by

applying the defined pseudo-random binary sequence; the device will then synchronize to

the periodic frame flag bit C0.

The status of the NICAM decoder can be read out from the NICAM status register by the

user. The OSB bit indicates that the decoder has locked to the NICAM data. The VDSP bit

indicates that the decoder has locked to the NICAM data and that the data is valid sound

data. The C4 bit indicates that the sound conveyed by the FM mono channel is identical to

the sound conveyed by the NICAM channel. The error byte contains the number of sound

sample errors, resulting from parity checking, that occurred in the past 128 ms period.

NICAM AUTO-MUTE

This function is enabled by setting bit AMUTE LOW subaddress 14 Upper and lower error

limits may be defined by writing appropriate values to two registers in the I 2 C-bus section

(subaddresses 16 and 17; . When the number of errors in a 128 ms period exceeds the

upper error limit the auto-mute function will switch the output sound from NICAM to

whatever sound is on the first sound carrier (FM or AM). When the error count is smaller

than the lower error limit the NICAM sound is restored. The auto-mute function can be

disabled by setting bit AMUTE HIGH. In this condition clicks become audible when the

error count increases; the user will hear a signal of degrading quality.

A decision to enable/disable the auto-muting is taken by the microcontroller based on an

interpretation of the application control bits C1, C2, C3 and C4 and, possibly, any

additional strategy implemented by the set maker in the microcontroller software.

For NICAM L applications, it is recommended to demodulate AM sound in the first sound

IF and connect the audio signal to the mono input of the TDA9875A. By setting the AMSEL

bit subaddress 14. the auto-mute function will switch to the audio ADC instead of switching

to the first sound carrier.

CRYSTAL OSCILLATOR

The digital-controlled crystal oscillator (DCXO) is illustrated in Fig.8 (see Chapter 12). The

circuitry of the DCXO is fully integrated, only the external 24.576 MHz crystal is needed.


TEST PINS

Both test pins are active HIGH, in normal operation of the device they are wired to VSSD1

Test functions are for manufacturing tests only and are not available to customers. Without

external circuitry these pads are pulled down to LOW level with internal resistors.

POWER FAIL DETECTOR

The power fail detector monitors the internal power supply for the digital part of the device.

If the supply has temporary been lower than the specified lower limit, the power-on reset

bit POR, transmitter register subaddress 0 will be set to HIGH. The CLRPOR bit, slave

register subaddress 1 resets the power-on reset flip-flop to LOW. If this is detected, an

initialization of the TDA9875A has to be carried out to ensure reliable operation.

LEVEL SCALING

All input channels to the digital crossbar switch (except for the loudspeaker feedback path)

are equipped with a level adjust facility to change the signal level in a range of 15 dB. It

is recommended to scale all input channels to be 15 dB below full scale (15 dB full scale)

under nominal conditions.

NICAM PATH

The NICAM path has a switchable J17 de-emphasis.

FM (AM) PATH

A high-pass filter suppresses DC offsets from the FM demodulator due to carrier frequency

offsets and supplies the monitor/peak function with DC values and an unfiltered signal, e.g.

for the purpose of carrier detection. The de-emphasis function offers fixed settings for the

supported standards (50 µs, 60 µs 75 µs and J17). An adaptive de-emphasis is available

for Wegener-Panda 1 encoded programs. A matrix performs the dematrixing of the A2

stereo, dual and mono signals.

NICAM AUTO-MUTE

If NICAM B/G, I, D/K is received, the auto-mute is enabled and the signal quality becomes

poor, the digital crossbar switch switches automatically to FM and switches the matrix to

channel 1. The automatic switching depends on the NICAM bit error rate.

The auto-mute function can be disabled via the I 2 C-bus. For NICAM L applications, it is

recommended to demodulate AM sound in the first sound IF and connect the audio signal

to the mono input of the TDA9875A. By setting the AMSEL bit subaddress 14 (see Section

10.3.11), the auto-mute function will switch to the audio ADC instead of switching to the


first sound carrier. The ADC source selector subaddress 23 (see Section 10.3.20) should

be set to mono input, where the AM sound signal should be connected.

LOUDSPEAKER (MAIN) CHANNEL

The matrix provides the following functions; forced mono, stereo, channel swap, channel

1, channel 2 and spatial effects.

There are fixed coefficient sets for spatial settings of 30%, 40% and 52%.

The Automatic Volume Level (AVL) function provides a constant output level of 23 dB full

scale for input levels between 0 and 29 dB full scale. There are some fixed decay time

constants to choose from, i.e. 2, 4 and 8 seconds.

Pseudo stereo is based on a phase shift in one channel via a 2nd-order all-pass filter.

There are fixed coefficient sets to provide 90 degrees phase shift at frequencies of 150,

200 and 300 Hz.

Volume is controlled individually for each channel ranging from +24 to -83 dB with 1 dB

resolution. There is also a mute position. For the purpose of a simple control software in

the microcontroller, the decimal number that is sent as an I 2 C-bus data byte for volume

control is identical to the volume setting in dBs (e.g. the I 2 C-bus data byte +10 sets the

new volume value to +10 dB).

Balance can be realized by independent control of the left and right channel volume

settings.

Contour is adjustable between 0 and +18 dB with 1 dB resolution. This function is linked to

the volume setting by means of microcontroller software.

Bass is adjustable between +15 and -12 dB with 1 dB resolution and treble is adjustable

between +/-12 dB with 1 dB resolution.

For the purpose of a simple control software in the microcontroller, the decimal number

that is sent as an I 2 C-bus data byte for contour, bass or treble is identical to the new

contour, bass or treble setting in dBs (e.g. the I 2 C-bus data byte +8 sets the new value to

+8 dB). Extra bass boost is provided up to 20 dB with 2 dB resolution. The implemented

coefficient set serves merely as an example on how to use this filter.

The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The

frequency can be selected via the I 2 C-bus. The beeper output signal is added to

theloudspeaker and headphone channel signals. The beeper volume is adjustable with


respect to full scale between 0 and 93 dB with 3 dB resolution. The beeper is not

effected by mute.

Soft-mute provides a mute ability in addition to volume control with a well defined time (32

ms) after which the soft-mute is completed. A smooth fading is achieved by a cosine

masking.

HEADPHONE (AUXILIARY) CHANNEL

The matrix provides the following functions; forced mono, stereo, channel swap, channel

and channel 2 (or C and S in Dolby Surround Pro Logic mode). Volume is controlled

individually for each channel in a range from +24 to 83 dB with 1 dB resolution. There is

also a mute position. For the purpose of a simple control software in the microcontroller,

the decimal number that is sent as an I 2 C-bus data byte for volume control is identical to

the volume setting in dB (e.g. the I 2 C-bus data byte +10 sets the new volume value to

+10 dB). Balance can be realized by independent control of the left and right channel

volume settings.

Bass is adjustable between +15 and -12 dB with 1 dB resolution and treble is adjustable

between +/- 12 dB with 1 dB resolution.

For the purpose of a simple control software in the microcontroller, the decimal number

that is sent as an I 2 C-bus data byte for bass or treble is identical to the new bass or

treble setting in dB (e.g. the I 2 C-bus data byte +8 sets the new value to +8 dB).

The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The

frequency can be selected via the I 2 C-bus. The beeper output signal is added to the

loudspeaker and headphone channel signals. The beeper volume is adjustable with

respect to full scale between 0 and 93 dB with 3 dB resolution. The beeper is not

effected by mute.

Soft-mute provides a mute ability in addition to volume control with a well defined time (32

ms) after which the soft-mute is completed. A smooth fading is achieved by a cosine

masking.

SCART INPUTS

The SCART specification allows for a signal level of up to 2 V (rms). Because of signal

handling limitations, due to the 5 V supply voltage of the TDA9875A, it is necessary to

have fixed 3 dB attenuators at the SCART inputs to obtain a 2 V input. This results in a +3

dB SCART-to-SCART copy gain. If 0 dB copy gain is preferred (with maximum 1.4V input),

there are +3 dB/0 dB amplifiers at the outputs of SCART 1 and SCART 2 and at the line


output. The input attenuator is realized by an external series resistor in combination with

the input impedance, both of which form a voltage divider. With this voltage divider the

maximum SCART signal level of 2 V (rms) is scaled down to 1.4 V (rms) at the input pin.

EXTERNAL AND MONO INPUTS

The 3 dB input attenuators are not required for the external and mono inputs, because

those signal levels are under control of the TV designer. The maximum allowed input level

is 1.4 V (rms). By adding external series resistors, the external inputs can be used as an

additional SCART input.

SCART OUTPUTS

The SCART outputs employ amplifiers with two gain settings. The gain can be set to +3

dB or to 0 dB via the I 2 C-bus. The +3 dB position is needed to compensate for the 3 dB

attenuation at the SCART inputs should SCART-to-SCART copies with 0 dB gain be

preferred [under the condition of 1.4 V (rms) maximum input level]. The 0 dB position is

needed, for example, for an external-to-SCART copy with 0 dB gain.

LINE OUTPUT

The line output can provide an unprocessed copy of the audio signal in the loudspeaker

channels. This can be either an external signal that comes from the dual audio ADC, or a

signal from an internal digital audio source that comes from the dual audio DAC. The line

output employs amplifiers with two gain settings. The +3 dB position is needed to

compensate for the attenuation at the SCART inputs, while the 0 dB position is needed, for

example, for non-attenuated external or internal digital signals (see Section 6.3.4).

DAC

DAC

AUDIO PROCESSINGA

NA

LO

GU

E C

RO

SS BA

R SW

ITC

H

TEST

DEMATRDEEMPH

LEVEL ADJ.

NICAM DEC.

QPSKDEM.

LEVEL ADJ.

CHANNELSELECTION

FM DEM(AM DEM)

IDENT

I / OPORT

L.S.AVL,VOL

CONTOURBASS

TREBLEPSEUDO

BASS CORR

H.P.VOL.BASSTREB.

IICIN / OUT

PEAKDETEC.

VCXOCLOCK

IIS

ENC.

DEC.

DAC DAC

INPUT SWITCHAGC ADC

123456789

1011121314151617181920212223242526272829303132

PLCKNICAMADDR1

SCLSDA

VSSA1VDEC1

IrefP1

SIF2VrefSIF1

ADDR2Vssd1Vdd1

CRESETVssd4

XTAL1XTAL0

P2SYSLCK

SCKWS

SDO2SDO1SDI2SDI1

TEST1MONOIN

TEST2EXT/REXT/L

6463626160595857565554535251504948474645444342414039383736353433

VDD2LORLOLMOLMORVdda

AUXOLAUXOR

Vssa3pcaplpcapr

vREF3SCOL2SCOR2Vssa4Vssd2

SCOL1SCOR2Vref2

i.c.i.c.

Vssa2i.c.i.c.

Vref(n)Vref(p)Vdec2SCIL2SCIR2Vssd3SCIL1SCIR1TDA9875A

IIC BUS

TR8

TO PIN 9 IC1

TDA9811

STD SWITCH

6 V

TO L/L' FILTER

SWITCH

L /L' SWITCH

II S

EF

TR8

TR6

AM AUDIO

FROM PIN 22 IC1

TDA9811

EFINTERCARRIER

FROM PIN 20 IC1

TDA9811

AUDIO FROM SCART

AUDIO OUT TO SCART

AUDIO LINE OUT

TR9

TR10

TR11

TR12

TO AUDIO

AMPLIFIER

TO HEADPHONES

APLIFIER

IC4

TDA2822M

6 V

6 V

TDA9875A PINOUT & PERIPHERALS TDA9875A.DRW

E.G. 7/11/99

TDA9811 QSS Pagina 1 di 4 e.g. TDA9811R

TDA9811

Multistandard VIF-PLLwith QSS-IF and AM demodulator

FEATURES

• 5 V supply voltage

• Two switched VIF inputs, gain controlled wide band VIF-amplifier (AC-coupled)

• True synchronous demodulation with active carrier regeneration (very linear

demodulation, good intermodulation figures, reduced harmonics, excellent pulse

response)

• Gated phase detector for L/L accent standard VCO frequency switchable between L

and L accent (alignment external) picture carrier frequency

• Separate video amplifier for sound trap buffering with high video bandwidth VIF AGC

detector for gain control, operating as peak sync detector for B/G (optional external

AGC) and peak white detector for L; signal controlled reaction time for L

• Tuner AGC with adjustable takeover point (TOP)

• AFC detector without extra reference circuit

• SIF input for single reference QSS mode (PLL controlled); SIF AGC detector for gain

controlled SIF amplifier; single reference QSS mixer able to operate in high

performance single reference QSS mode

• AM demodulator without extra reference circuit

• AM mute (especially for NICAM)

• Stabilizer circuit for ripple rejection and to achieve constant output signals.

GENERAL DESCRIPTION

The TDA9811 is an integrated circuit for multistandard vision IF signal processing and

sound AM demodulation, with single reference QSS-IF in TV and VCR sets.

1995 Oct 03

4

Philips S

emiconductors

Prelim

inary specification

Multistandard V

IF-P

LLw

ith QS

S-IF

and AM

demodulator

TD

A9811

BLO

CK

DIA

GR

AM

dbook, full pagewidth

SINGLE REFERENCE MIXER AND

AM DEMODULATOR

VCO TWD AFC DETECTORTUNER AND VIF-AGC

VIF input switch

FPLL VIDEO DEMODULATOR AND AMPLIFIER

SIF AMPLIFIER

SIF-AGCINTERNAL VOLTAGE

STABILIZER

VIF AMPLIFIER AND

INPUT SWITCH

SIF

VIFB

VIFA

TDA9811

29 27 26 9 8

10

21

22

12

2324257192830 63

5

4

2

1

32

31

5 V

VP1/2

CAGC

standard switch

20 17

13

14

AF AMPLIFIER AND SWITCH

AF/AM

n.c.

n.c.1811

n.c.

16

n.c.

15

n.c.

VIDEO BUFFER

CVBS 2 V (p-p)

video 1 V (p-p)

AFC

2 x fPCtuner AGC

loop filter

TOPCAGC CBL

MHA046

mute switch, AM(2nd SIF) Vo QSS

L′/L switch

Vi(vid)




Vision IF amplifier and input switch The vision IF amplifier consists of three AC-coupled

differential amplifier stages. Each differential stage comprises a feedback network

controlled by emitterdegeneration. T

The first differential stage is extended by two pairs of emitter followers to provide two IF

input channels. The VIF input can be selected by pin 30

Tuner and VIF AGC

The AGC capacitor voltage is transferred to an internal IF control signal, and is fed to the

tuner AGC to generate the tuner AGC output current (open-collector output).

The tuner AGC takeover point can be adjusted. This allows the tuner and the SWIF filter to

be matched to achieve the optimum IF input level.

The AGC detector charges/discharges the AGC capacitorto the required voltage for setting

of VIF and tuner gain in order to keep the video signal at a constant level.

Therefore for negative video modulation the sync level and for positive video modulation

the peak white level of the video signal is detected. In order to reduce the reaction

time for positive modulation, where a very large time constant is needed, an additional

level detector increases the discharging current of the AGC capacitor (fast mode)

in the event of a decreasing VIF amplitude step. The additional level information is given

by the black-level detector voltage.

Frequency Phase Locked Loop detector (FPLL)

The VIF-amplifier output signal is fed into a frequency detector and into a phase detector

via a limiting amplifier.

During acquisition the frequency detector produces a DC current proportional to the

frequency difference between the input and the VCO signal. After frequency lock-in the

phase detector produces a DC current proportional to the phase difference between the

VCO and the input signal. The DC current of either frequency detector or phase detector is

converted into a DC voltage via the loop filter, which controls the VCO frequency. In the

event of positive modulated signals the phase detector is gated by composite sync in order

to avoid signal distortion for overmodulated VIF signals.


VCO, Travelling Wave Divider (TWD) and AFC

The VCO operates with a resonance circuit (with L and C in parallel) at double the PC

frequency. The VCO is controlled by two integrated variable capacitors.

The control voltage required to tune the VCO from its free-running frequency to actually

double the PC frequency is generated by the frequency-phase detector and fed via the

loop filter to the first variable capacitor (FPLL). This control voltage is amplified and

additionally converted into a current which represents the AFC output signal. The VCO

centre frequency can be decreased (required for L accent standard) by activating an

additional internal capacitor. This is achieved by using the L accent switch. In this event

the second variable capacitor can be controlled by a variable resistor at the L accent

switch for setting the VCO centre frequency to the required L accent value. At centre

frequency the AFC output current is equal to zero.

The oscillator signal is divided-by-two with a TWD which generates two differential output

signals with a 90 degree phase difference independent of the frequency.

Video demodulator and amplifier

The video demodulator is realized by a multiplier which is designed for low distortion and

large bandwidth. The vision IF input signal is multiplied with the ‘in phase’ signal of the

travelling wave divider output. In the demodulator stage the video signal polarity can be

switched in accordancewith the TV standard. The demodulator output signal is fed via an

integrated low-pass filter for attenuation of the carrier harmonics to the video amplifier. The

video amplifier is realized by an operational amplifier with internal feedback and high

bandwidth. A low-pass filter is integrated to achieve an attenuation of the carrier harmonics

for B/G and L standard. The standard dependent level shift in this stage delivers the same

sync level for positive and negative modulation. The video output signal is 1 V (p-p) for

nominal vision IF modulation.

Video buffer

For an easy adaption of the sound traps an operational amplifier with internal feedback is

used in the event of B/G and L standard. This amplifier is featured with a high bandwidth

and 7 dB gain. The input impedance is adapted output stage delivers a nominal 2 V (p-p)

positive video signal. Noise clipping is provided.


SIF amplifier and AGC

The sound IF amplifier consists of two AC-coupled differential amplifier stages. Each

differential stage comprises a controlled feedback network provided by emitter

degeneration. The SIF AGC detector is related to the SIF input signals (average level of

AM or FM carriers) and controls the SIF amplifier to provide a constant SIF signal to the

AM demodulator and single reference QSS mixer. The SIF AGC reaction time is set to

‘slow’ for nominal video conditions. But with a decreasing VIF amplitude step the SIF AGC

is set to ‘fast’ mode controlled by the VIF AGC detector. In FM mode this reaction time is

also set to ‘fast’ controlled by the standard switch.

Single reference QSS mixer The single reference QSS mixer is realized by a multiplier.

The SIF amplifier output signal is fed to the single reference QSS mixer and converted to

intercarrier frequency by the regenerated picture carrier (VCO).

The mixer output signal is fed via a high-pass for attenuation of the video signal

components to the output pin 20. With this system a high performance hi-fi stereo

sound processing can be achieved.

AM demodulator

The AM demodulator is realized by a multiplier. The modulated SIF amplifier output signal

is multiplied in phase with the limited (AM is removed) SIF amplifier output signal. The

demodulator output signal is fed via an integrated low-pass filter for attenuation of the

carrier harmonics to the AF amplifier.

Internal voltage stabilizer and 1 ¤2 VP -reference

The bandgap circuit internally generates a voltage of approximately 1.25 V, independent of

supply voltage and temperature. A voltage regulator circuit, connected to this voltage,

produces a constant voltage of 3.6 V which is used as an internal reference voltage.

For all audio output signals the constant reference voltage cannot be used because large

output signals are required.

1995 Oct 03 5


Multistandard VIF-PLLwith QSS-IF and AM demodulator

TDA9811

PINNING


Vi VIF1 1 VIF differential input signal voltage 1


CBL 3 black level detector



TADJ 6 tuner AGC takeover adjust (TOP)

TPLL 7 PLL loop filter

CSAGC 8 SIF AGC capacitor

STD 9 standard switch

Vo CVBS 10 CVBS output signal voltage

LSWI 11 L/L accent switch

Vo AF 12 AM audio voltage frequency output

n.c. 13 not connected




MUTE 17 AM mute


TAGC 19 tuner AGC output

Vo QSS 20 single reference QSS output voltage

Vo(vid) 21 composite video output voltage

Vi(vid) 22 video buffer input voltage

AFC 23 AFC output

VCO1 24 VCO1 reference circuit for 2fPC

VCO2 25 VCO2 reference circuit for 2fPC

Cref 26 1⁄2VP reference capacitor

GND 27 ground

CVAGC 28 VIF AGC capacitor

VP 29 supply voltage

INSWI 30 VIF input switch

Vi SIF1 31 SIF differential input signal voltage 1

Vi SIF2 32 SIF differential input signal voltage 2Fig.2 Pin configuration.

andbook, halfpage

TDA9811

MHA047

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

V

V

C

TADJ

T

C

STD

V

LSWI

V

n.c.

n.c.

n.c.

n.c.

V

V

V

C

GND

INSWI

C

VCO2

VCO1

AFC

V

V

V

TAGC

n.c.

o AF

o CVBS

SAGC

PLL

BL

i VIF2

i VIF1

V

Vi VIF4

i VIF3 P

i SIF1

i SIF2

VAGC

ref

MUTE

o QSS

o(vid)

i(vid)

TDA9830

TV sound AM-demodulator and audio source switch

FEATURES • Adjustment free wideband synchronous AM demodulator • Audio source-mute switch (low noise) • Audio level according EN50049 • 5 to 8 V power supply or 12 V alternative • Low power consumption. GENERAL DESCRIPTION The TDA9830, a monolithic integrated circuit, is designed for AM-sound demodulation used in L- and L’-standard. The IC provides an audio source selector and also mute switch. FUNCTIONAL DESCRIPTION Sound IF input The sound IF amplifier consists of three AC-coupled differential amplifier stages each with approximately 20 dB gain. At the output of each stage is a multiplier for gain controlling (→ current distribution gain control). The overall control range is approximately -6 to +60 dB and the frequency response (-3 dB) of the IF amplifier is approximately 6 to 70 MHz. The steepness of gain control is approximately 10 mV/dB. IF AGC The automatic gain control voltage to maintain the AM demodulator output signal at a constant level is generated by a mean level detector. This AGC-detector charges and discharges the capacitor at pin 3 controlled by the output signal of the AM-demodulator compared to an internal reference voltage. The maximum charge/discharge current is approximately 5 mA. This value in combination with the value of the AGC capacitor and the AGC steepness determines the lower cut-off audio frequency and the THD-figure at low modulation frequency of the whole AM-demodulator. Therefore a large time constant has to be chosen which leads to slow AGC reaction at IF level change. To speed up the AGC in case of IF signal jump from low to high level, there is an additional comparator built in, which can provide additional discharge current from the AGC capacitor up to 5 mA in a case of overloading the AM demodulator by the internal IF signal. AM-demodulator The IF amplifier output signal is fed to a limiting amplifier (two stages) and to a multiplier circuit. However the limiter output signal (which is not any more AM modulated) is also fed to the multiplier, which provides AM demodulation (in phase demodulation). After lowpass filtering (fg ≈ 400 kHz) for carrier rejection and buffering, the demodulator output signal is present at pin 6. The AM demodulator operates over a wide frequency range, so that in

June1994

3

Philips S

emiconductors

Product specification

TV

sound AM

-demodulator and audio

source switch

TD

A9830Fig.1 Block diagram.

combination with the frequency response of the IF amplifier applications in a frequency range from approximately 6 MHz up to 70 MHz are possible. Audio switch This circuit is an operational amplifier with three input stages and internal feedback network determining gain (0 dB) and frequency response (fg ≈ 700 kHz). Two of the input stages are connected to pin 7 and pin 9, the third input stage to an internal reference voltage. Controlled by the switching pins 10 and 12, one of the three input stages can be activated and a choice made between two different AF signals or mute state. The selected signal is present at pin 8. The decoupling capacitors at the input pins are needed, because the internally generated bias voltage for the input stages must not be influenced by the application in order to avoid DC-plop in case of switching. The AM demodulator output is designed to provide almost the same DC voltage as the input bias voltage of the audio switch. But there may be spread between both voltages. Therefore it is possible to connect pin 6 directly to pin 7 (without a decoupling capacitor), but in this event the DC-plop for switching can increase up to 100 mV. Reference circuit This circuit is a band gap stabilizer in combination with a voltage regulation amplifier, which provides an internal reference voltage of about 3.6 V nearly independent from supply voltage and temperature. This reference voltage is filtered by the capacitor at pin 4 in order to reduce noise. It is used as a reference to generate all important voltages and currents of the circuit. For application in 12 V power supply concepts, there is an internal voltage divider in combination with a Darlington transistor in order to reduce the supply voltage for all IC function blocks to approximately 6 V. This is necessary because of use of modern high frequency IC technology, where most of the used integrated components are only allowed to operate at maximum 9 V supply voltage.

INPUTSWITCH

AGC

ADC FM DEM(AM DEM)

DEMATRDEEMPH

CHANNELSELECTION

DAC

VCXOCLOCK

LEVEL ADJ.

DAC

DAC

DAC

AUDIOPROCESSING

L.S .AVL, VOL

CONTOUR, BASSTREB, PSEUBASSCORR

BEEPER

H.P.VOL, BEEP.BASS, TREB.

IIC IDENT

IIS

TDA9870A

ANALOGUE CROSS BAR SWITCH

29 31 32 33 34 35 36 3747 48

5051 52 62 63

49 59 64

VDDA3VDDD2

60

61

4

5

SCL

SDA3IIC ADDRES.

6 7 8

I / OPORT

9

10

12

11 132° IIC ADDRESS

14 15 1617 2018 19

PEAKDETECT.

22 23 24 2526 27

IISENC / DEC.

21

TEST

28

30

38 39

6 V

VSSA2

VSSA3VSSA4

VSSD2 49

43

5650

A3

57

58

TR10

TR9TR12

TR11

HEADPHONES

AMPLIFIERTDA2822M

1

3

KIA7812

IC 5

IC 4

2 4

7 6

1 23

12 V

6 V

6V

7 512 8 11 96 10

A1

2 1 4 3

8

9

5

6

1

2

3

4

7

10

IIC

26V

A2

F19STEREO A2MODULE F19STA2 .DRV

E.G 5/11/99

EXT. IN

SCART SOUND OUT

INTE

RC

AR

RIE

R IN

PUT

IIC

VSSA1

MONO INPUT SCART OUT

LINE OUT

IIS

INPUTSWITCH

AGC

ADC

NICAM DEC.

FM DEM

(AM DEM)

QPSKDEM.

DEMATRDEEMPH

LEVEL ADJ.

CHANNELSELECTION

DAC

VCXOCLOCK

LEVEL ADJ.

DAC

DAC

DAC

AUDIOPROCESSING

L.S .AVL, VOL

CONTOUR, BASSTREB, PSEUBASSCORR

BEEPER

H.P.VOL, BEEP.BASS, TREB.

IIC IDENT

IIS

TDA9875A ANALOGUE CROSS BAR SWITCH

29 31 32 33 34 35 36 3747 48

5051 52 62 63

49 59 64

VDDA3VDDD2

60

61

4

5

SCL

SDA3 IIC ADDR.

PLK

NICAM

DATA

1

2

6 7 8

I / OPORT

9

10

12

11 132° IIC ADDRESS

14 15 1617 2018 19

PEAK

DETECT.

22 23 24 2526 27

IIS

IICIIS

ENC / DEC.

21

TEST28

30

38 39

6 V

VSSA2VSSA3VSSA4

VSSD2 49

435650

A3

EF

57

58

TR10

TR9TR12

TR11

HEADPHONESAMPLIFIERTDA2822M

1

3

KIA7812

IC 5

IC 42 4

7 6

12

3

12 V

26 V

6 V

1

2

31

32

IF AMPL.&

VIDEOSWITCH

TUNER & VIF AGC

28 3 6 19

VCO AFC

VIDEODEMOD.

AF AMPL.& SWT.

SIFAMPL.

FPLL

FM MIXER& AM DEM.

21

10

22

12

17

2330

TDA 9811 29 27

9 11

TR7

R20STD

TR8 L/L'

24 25

L1

20

5 V

8 V

TR1

TR6

MUTE

8V

VIF SWT.

IC 1

FOS 1

FOS2

4

5

EF

2

1

3TR2

TR3

12 V

D2

D1

R5

R6

6V

R7

R6

L /L'

EF

TR5 TR4

6V 12V

7 5 12 8 11 96 10

A12 1 4 3

8

9

5

6

1

2

3

4

7

10

IIC

26V

A2IF IN

F19NICAMMODULEF

19N

ICA

M.D

RV

E.G

5/

11/9

9

STEREO INTERCARRIER ONLY

EXT. IN

SCART SOUND OUT

FROMPIM 7A2

15

14

12

13

19

18

17

4

8

20

16

11

15

14

10

11

2

1

12

13

AUDIO CINCH IN

FROM PIN8 IC 100 SCART/CINCH SWITCH

IC200 (2/3) HEF 4053

SCART 1

TR110

F19ASSPH.DRWE.G. 29/12799

1 973 4

STEREO MODULE CONNECTOR

SCART 2

82

1

3

2

6

6 2 1 3

FROM PIN 7 IC 100TV/AV SWITCHTO AV2

FROM PIN 6 IC 100AV1 / AV2SWITCH

IC201 (2/3 OF LA7955)

FROM PIN 11TUNER (I.F.)

F19 AUDIO STEREO SIGNAL PATH

IC 400 TDA1521A9 8 7 6 5 4 3 2 1

TDA4605 SMPS CONTRO I.C. Pagina 1 di 6e.g.tda4605R.doc

TDA4605

Control IC for Switched-Mode Power Supplies

using MOS-Transistors

Features

• Fold-back characteristic provides overload protection for external components

• Burst operation under short-circuit conditions

• Loop error protection

• Switch-off if line voltage is too low (undervoltage switch-off)

• Line voltage compensation of overload point

• Soft-start for quiet start-up

• Chip-over temperature protection (thermal shutdown)

• On-chip parasitic transformer oscillation suppression circuitry

Functional desciption

The IC TDA 4605-1 controls the MOS-power transistor and performs all necessary

regulation and monitoring functions in free running flyback converters. Since good load

regulation over a wide load range is attained, this IC is applicable tor consumer and

industrial power supplies.

The serial circuit of power transistor and primary winding of the flyback transformer is

connected to the input voltage. During the switch - on period of the transistor, energy is

stored in the transformer and during the switch - off period it is fed to the load via the

secondary winding. By varying switch-ontime of the power transistor, the IC controls each

portion of energy transferred to the secondary side such that the output voltage remains

nearly independent ot load variations.

The required control information is taken from the input voltage during the switch-on period

and from a regulation winding during the switch-off period.

In the different load ranges the switched-mode power supply (SMPS) behaves as follow:


No load operation:

The power supply unit oscillates at its resonant frequency typ. 100 kHz to 200 kHz.

Depending upon

the transformator windings the output voltage can be slightly above nominal value.

Nominal operation:

The switching frequency declines with increasing load and decreasing AC-voltage. The

duty factor primarly depends on the AC-voltage. The output voltage is load-dependent

only.

Overload point:

Maximal output power is available at this point ot the output characteristic.

Overload:

The energy transferred per operation cycle is limited at the top. Therefore the output

voltage declines by secondary overloading..Semiconductor Group 35

TDA 4605 Pin Definitions and Functions

Pin No. Function

1 Regulating Voltage: Information input concerning secondary voltage. By

comparing the regulating voltage - obtained from the regulating winding ot the transformer

- with the internal reference voltage, the output impulse width on pin 5is adapted to the

load ot the secondary side (normal, overload, short-circuit, no load).

2 Primary Current Simulation: Information input regarding the primary current.

The primary current rise in the primary winding is simulated at pin 2 as a voltagerise by

means ot external RC-element. When a value is reached that is derivedfrom the regulating

voltage at pin 1, the output impulse at pin 5 is terminated. TheRC-element serves to set

the maximum power at the overload point set.

3 Input for Primary Voltage Monitoring: In the normal operation V 3 is moving

between the thresholds V 3H and V 3L (V 3H > V 3 > V 3L ). V 3 < V 3L : SMPS is

switched OFF (line voltage too low). V 3 > V 3H : Compensation of the overload point

regulation (controlled by pin 2) starts at V 3H : V 3L = 1.7.


4 Ground

5 Output: Push-pull-output provides 1 A for rapid charge and discharge of the

gate capacitance ot the power MOS-transistor.

5 Supply Voltage Input: A stable internal reference voltage V REF is derived from

the supply voltage also the switching thresholds V 6A , V 6E , V 6 max and V 6 min for the

supply voltage detector. If V 6 > V 6E then V REF is switched on and swiched off when V

6 < V 6A . In addition the logic is only enable for V 6 min < V 6 < V 6 max .

7 Soft-Start: Input for soft-start. Start-up will begin with short pulses by connecting a

capacitor from pin 7 to ground.

8 Zero Detector: Input tor the oscillation feedback. After starting oscillation, every

zero transit of the feedback voltage (falling edge) triggers an output impulse at

pin 5. The trigger threshold is at + 50 mV typical..Semiconductor Group 36

TDA 4605 Application Circuit

Application circuit shows a flyback converter for video recorders with a power rating of 50

W. The circuit is designed as a wide-range power supply tor AC-line voltages ot 90 to 270

V. The AC-input voltage is rectified by bridge rectifier GR1 and smoothed by C 1 . The

NTC limits the rush in current.In the period before the switch-on threshold is reached the

IC is supplied via resistor R 1 ; during the start-up phase it uses the energy stored in C 2 ,

under steady-state conditions the IC receives its supply voltage from transformer winding n

1 via diode D1. The switching transistor T1 is a BUZ 90.

The parallel-connected capacitor C 3 and the inductance ot primary winding 112 determine

the system resonance frequency. The R 2 - C 4 - D2 circuitry limits overshoot peaks, and

R 3 protects the gate of T1 against static charges.

While T1 conducts, the current rise in the primary winding depends on the winding’s

inductance and the V C1 voltage. A voltage reproduction ot the current rise is tabbed using

the R 4 - C 5 network and forwarded into pin 2 ot the IC. The RC-time constant ot R 4 , R 5

must be dimensioned correctly in order to prevent driving the transformer core into

saturation.

The R 10 /R 11 divider ratio provides the line voltage threshold controlling the

undervoltage control circuit in the IC. The voltage present at pin 3 also determines the

overload. Detection of overload together with the current characteristic at pin 2 controls the

on period ot T1. This keeps the cut-off point stable even with higher AC-line voltages.


Pin 3 The down-divide primary voltage applied there stabilizes the overload point. In

addition the logic is disabled in the event of low voltage by comparison with the internal

stable voltage V V in the primary voltage monitor block.

Pin 4 Ground

Pin 5 In the output stage the output signals produced by the logic are shifted to a leved

suitable for MOS-power transistors.

Pin 6 From the supply voltage V 6 are derived a stable internal reference V REF and the

switching threshold V 6A , V 6E , V 6 max and V 6 min for the supply voltage monitor. All

reference values (V R , V 2B , V ST ) are derived from V REF . If V 6 > V VE the V REF is

switched on and switched off when V 6 < V 6A . In addition, the logic is released only for V

6 min < V 6 < V 6 max .

Pin 7 The output of the overload amplifier is connected to pin 7. A load on this output

causes a reductio in maximal impulse duration. This function can be used to implement a

soft start, when pin 7 is connected to ground by a capacitor

Pin 8 The zero detector controlling the logic block recognizes the transformer being

discharged by positive to negative zero crossing of pin 8 voltage and enables the logic for

a new pulse. Parasitic oscillations occurring at the end of a pulse cannot lead to a new

pulse (double-pulsing), because an internal circuit inhibits the zero detector for a finite time

t UL after the end of each pulse.

Start-Up Behaviour

The start-up behaviour of the application circuit per sheet 48 is represented on sheet 50

for a line voltage barely above the lower acceptable limit voltage value (without soft-start).

After applying the line voltage at the time t 0 to the tollowing voltages built up:

– V 6 corresponding to the half-wave charge current over R 1

– V 2 to V 2 max (typically 6.6 V)

– V 3 to the value determined by the divider R 10 /R 11 .

The current drawn by the IC in this case is less than 1.6 mA. If V 6 reaches the threshold V

6E (time point t 1 ), the IC switches on the internal reference voltage. The currentdraw

max. rises to 12 mA.

The primary current- voltage reproducer regulates V 2 down to V 2E and the starting

impulse generator generates the starting impulses from time point t 5 to t 6 . The feedback

to pin 8 starts the next impulse and so on. All impulses including the starting impulse are


controlled in width by regulating voltage of pin 1. When switching on this corresponds to a

short-circuit event, i.e. V 1 = 0.

Hence the IC starts up with "short-circuit impulses" to assume a width depending on the

regulating voltage feedback (the IC operates in the overload range). The maximum pulse

width is reached at time point t 2 (V 2 = V 2 max ). The IC operates at the overload point.

Thereafter the peak values ot V 2 decrease rapidly, as the IC is operating within the

regulation range. The regulating loop has built up. If voltage V 6 falls below the switch-off

threshold V 6 min before the reversal point is reached, the starting attempt is aborted (pin

5 is switched to low). As the IC remains switched on, V 6 further decreases to V 6 . The IC

switches off; V 6 can rise again (time point 14) and a new start-up attempt begins at time

point t 1 . If the rectified alternating line voltage (primary voltage) collapses during load, V

3 can fall below V 3A , as is happening at time point t 3 (switch-on attempt when voltage is

too low). The primary voltage monitor then clamps V 3 to V 3S until the IC switches off (V

6 < V 6A ). Then a new start-up attempt begins at time point t

Regulation, Overload and No-Load Behaviour

When the IC has started up, it is operating in the regulation range. The potential at pin 1

typically is 400 mV. If the output is loaded, the regulation amplifier allows broader impulses

(V 5 = H). The peak voltage value at pin 2 increases up to V 2S max . If the secondary

load is further increased, the overload amplifier begins to regulate the pulse width

downward. This point is referred to as the overload point of the power supply. As the IC

supply voltage V 6 is directly proportional to the secondary voltage, it goes down in

accordance with the overload regulation behaviour. If V 6 falls below the value V 6 min ,

the IC goes into burst operation. As the time constant of the half-wave charge-up is

relatively large, the short-circuit power remains small. The overload amplifier cuts back

to the pulse width t pk . This pulse width must remain possible, in order to permit the IC to

start-up without problems from the virtual short circuit, which every switching on with V 1 =

0 represents. If the secondary side is unloaded, the loading impulses (V 5 = H) become

shorter. The frequency increases up to the resonance frequency of the system. If the load

is further reduced, the secondary voltages and V 6 increase. When V 6 = V 6 max , the

logic is blocked. The IC converts to burst operation. This renders the circuit absolutely safe

under no-load conditions.


Regulation of the switched-mode power supply is via pin 1. The control voltage of winding

n 1 during the off-period of T1 is rectified by D3, smoothed by C 6 and stepped down at an

adjustable ratio by R 5 , R 6 and R 7 . The R 6 - C 7 network suppresses parasitic

overshoots (transformer oscillation).

The peak voltage at pin 2, and thus the primary peak current, is adjusted by the IC so that

the voltage applied across the control winding, and hence the output voltages, are at the

desired level.

When the transformer has supplied its energy to the load, the control voltage passes

through zero.

The IC detects the zero crossing via series resistors R 9 connected to pin 8. But zero

crossings are also produced by transformer oscillation after T1 has turned off if output is

short-circuited. Thereforethe IC ignores zero crossings occurring within a specitied period

of time after T1 turn-off.

The capacitor C 8 connected to pin 7 causes the power supply to be started with shorter

pulses to keep the operating ftrequency outside the audible range during start-up.

On the secondary side, tive output voltages are produced across winding n 3 to n 7

rectified by D4 to D8 and smoothed by C 9 to C 13 . Resistors R 12 , R 14 and R 19 to R

21 are used as bleeder resistors.

Fusable resistors R 15 to R 18 protect the rectifiers against short circuits in the output

circuits, which are designed to supply only small loads..

TDA 4605 Block Diagram

Pin 1 The regulating voltage forwarded to this pin is compared with a stable internal

reference voltage V R in the regulating and overload amplifier. The output of this stage

is ted to the stop comparator.

Pin 2 A voltage proportional to the drain current ot the switching transistor is generated

there by theexternal RC-combination in conjunction with the primary current transducer.

The output of this transducer is controlled by the logic and referenced to the internal stable

voltage V 2B . If the voltage V 2 exceeds the output voltage of the regulating amplifier, the

logic is reset by the stop comparator and consequently the output ot pin 5 is switched to

low potential. Further inputs tor the logic stage are the output for the start impulse

generator with the stable reference potential V ST and the supply voltage monitor.

Semiconductor Group 36

TDA 4605

Block Diagram

15

3

11

9

8

5

MAINSINPUT

4 2

7 8

1

OVER LOADPROTECTION

ON

OFFFROM PIN 19IC 100SAA5297A

5 V

12 V

26 V

26 V148 V (110°)

128 V

TR 4

TR 2

TR 1STH7N80FI

T 1

line output stage

sound power

line driver

signalprocessing

stand by

NON MAINS ISOLATED SECTOR

5 V

F 19 S.M.P.S.

F19SMPS.DRWE.G. 7/11/99

SMPS CONTROLIC1 TDA 4605

6

3

2

4

10

6 / 16

12

D8

R14

D13

D6R1

SUPPLY VOLTAGEADJUSTMENT

ZERO CROSSINGDETECTOR

PRIMARY VOLTAGE & CURRENTSENSING

SOFTSTART

DRIVEOUTPUTPULSE

START-UP

8,5v

12

5

4

8

9

TR3

TR5

TR6

(CONFIGURATION WITHOUTZERO POWER STAND BY MODULE)

15

3

11

9

8

ON

OFF

FROM PIN 19IC 100SAA5297A

12 V

26 V

26 V148 V (110°)

128 V

TR 4

TR 2

T 1

line output stage

sound power

line driver

signalprocessing stand by

5 V

F 19 LOW POWERSTAND-BYCONFIGURATION

F19LPSBC.DRWE.G. 14 /11/99

2

4

10

6 / 16

12 8,5v

12

5

4

8

9

TR3

TDA8183

IC10

1

5

9

7L7805CV

1

2

3

IC2 IL410

X1

X2

X3

ON-OFF

5 V ST-BY

A12

IC 1

5 V

TR2 BT808T1

FROMMAINS SWITCH

MAINS TO MAIN BOARD

STAND-BY MODULE

SERVICE MODESERVICE MODEF19 F19


For the description of the use of the TV make use of the Instruction Manual

Service mode

As already mentioned in the summary the remote control can be used to set all

parameter and to adjust the TV set without to open the back cover.

There are two ways to enter the "SERVICE MODE" that are to use the LOCAL

KEYBOARD or to have a precial prepared REMOTE CONTROL.

FIRST METHOD. (If the special remote control is available use the button following the

indication of the Table 1

Table 1 List of command of the "SERVICE REMOTE CONTROL"

BUTTON RC5 Sub

System

Decimal Coce Function

0 0 0 Vertical Slope

1 0 1 Vertical Amplitude

2 0 2 Vertical Shift

3 0 3 Vertical S Correctio

4 0 4 Horizontal Shift

5 0 5 HorizontalAmplitude

6 0 6 E-W parabola

7 0 7 E-W Corner

8 0 8 E-W Trapezium

9 0 9 AGC

Pr + 0 32 Up Carousel of all Service Parameter

Pr - 0 33 Down Carousel of all Service Parameter

Vol + 0 16 Adjust Parameter Value (UP)

Vol - 0 17 Adjust Parameter Value (Down)

TV 0 63 Leave SERVICE MODE" without to store

MEM 0 50 Leave SERVICE MODE with store

MENU 0 53 Wred

SERVICE 7 58 SERVICE MODE ENTER


Table 2 Parameter and value to be adjusted in "SERVICE MODE"

PARAMETER VALUE DESCRIPTION

init ctvfor v0.6 on/ off Default Initialization

vg2test on/off Cut -off adjustment

txtbri 0--63 Adjust TXT brightness

txtcon 0--63 Adjust TXT Contrast

884c04 Bit (FSU) Increase blue stretch and the dynamic skin

884c03 Bit (FSU) Adj. acl (automatic colour limiter - and cathode drive level.

88c02 Bit (FSU) Adj.(black stretch), blue stretch, and the blue back

optionb1 Bit (FSU) Select TV standard and TXT character set

optionb2 Bit (FSU) Scart type selections (

optionb3 Bit (FSU) (*) Hotel mode setting

nicamuperror 0--63 Nicam sensitivity (upper limit)

nicamlowerror 0--63 Nicam sensitivity (Lower limit).

nicamcon Bit (FSU) Tda9875 CONTROL

pipcontrast 0--15 PIP Contrast control

wblue 0--63 Blue channel gain

wgreen 0--63 “Green channel gain

wred 0--63 “Red channel gain

ydelaypal 0--63 Luma chroma delay

ewtrapeze 0--63 E-W- Trapezium adjustment

ewcorner 0--63 E-W- Corner Adjustment

ewparab 0--63 E-W- Parabola Adjustment

ewwidth 0--63 Horizontal Amplitude

h-shift 0--63 Horizontal shift

s-corr 0--63 Vertical S-Correction

v-shift 0--63 Shift Vertical

v-ampl 0--63 Vertical Amplitude

v-slope 0--63 Slope Vertical

agc 0--63 AGC adjustment

if xx afc 2/3 0--63 (FSU) Factory set up

LEGENDA: (FSU)= FACTORY SET UP (*) REDUCE OF A QUANITY 4 TO GET HOTEL MODE

WARNING!! Do not change value for those parameter that are highlighted please


Note 1

If during the installation of the TV set the AUTOSTORE" method is used, it is

fundamental, before to start the function, to select the name of the country as the criteria of

listing the broadcasters names is fixed by EBU table that are related to the country itself. It

is possible to find more channels of the same broadcaster on the Arial. In this case the

system will place first the signal having TXT with the strongest signal level than the others

and finally, with the found sequence the weakest one without TXT.

Note 2

To get HOTEL MODE it is necessary to enter "SERVICE MODE" and to change the

parameter "optionb3". Read the original value e subtract 4 (decimal). In HOTEL MODE all

tuning systems are not possible, the volume is pre fixed and the MENU from the LOCAL

KEY BOARD is not accessible.

Note 3

For fast programming (in case of installation of several TV set in Shops or Hotels a

"Black Box" is available on request. The procedure for a quick program is as follows:

1. Install and tune all channel storing it in the program sequence you want

2. Switch off the Set with the remote control and leave it in Stand-by mode

3. Switch on the "Black Box" and connect it to Scart

4. Press the button corresponding to the chassis to be programmed and at the same time

press the button "Read" for a while. (corresponding LED will be on.

5. When the LED "Write" became off (after few seconds) disconnect the "Black Box"

6. Insert the Black Box in the new TV set (in stand by condition)

7. Press F19 and "Write" buttons at same time. Corresponding "Write" LED will light

8. After few seconds when the "Write" LED will switch-off the procedure is finished .

9. Repeat points from 6 to 8 to program others TV set

WARNING!!!!! The above procedure can be appliedonly to TV set specially prepared for this functions


Table 4 List of languages that can be reproduced as a function of the TXT characters set

setting with the optionb1 (bit number 6)

WEST EUROPE CHARACTER SET

LANGUAGES

EAST EUROPE CHARACTER SET

LANGUAGES

ENGLISH POLISH

GERMAN GERMAN

SWEDISH ESTONIA

ITALIAN SERB-CROAT

FRENCH CZECH

SPANISH RUMEN

TURKISH

Just to give an example how to set the option byte 1, 2, and 3 we can start from

a TV set for BG standard, with hyperband tuner to be sold in a country using West

European character set.

Locking at the table 3 Optionb1 we have the following condition:

BIT OPTIONB1

NUMBER 0 1 VALUE WEIGHT

0 BG 1 1

1 L/L' 0

2 I 0

3 DK 0

4 X 0

5 X 0

6 E.E.TXT W.E. TXT 1 64

7 CATV 1 128

If we want to change from West Europe character set to East Europe, bit 6

became 0 that is the new value is 129 (128 plus 1)that in hexadecimal format is 41

REMEMBER TO INSERT COUNTRY TABLE

Adding the value of thelast column we get 193in decimal form and C!in hexadecimal.This means that wehave to choose thisvalue (C1) for theoptionb1 in servicemode


THE SECOND METHOD to enter service mode is to use the LOCAL KEY BOARD

as describe here below

1. Starting from TV off press VOLUME + on the LOCAL KEYBOARD and in the

mean time switch on the TV with the mains switch

2. Within three second switch on the TV using the "SWITCH-OFF" button on the

Remote Control

3. A small windows with black background and yellow characters will appear in the

middle of the screen.

4. Using the Remote control, program + / - (top bottom) will change the

"PARAMETER" and the VOLUME + / - (left / right) will change the value

5. Each parameter can be stored, leaving the service mode, by using the MEM

(yellow) button on the remote control

6. To leave "SERVICE MODE" without to store the new value use the TV button.

7. It is not necessary to store each value one by one this means that you can

change all value you need and finally leave the SERVICE MODE pressing the

YELLOW button MEM.

In the Table 3 we can find all parameter and related value to be seated. Some

parameter have to adjusted with a simple on-off value, others are just factory option and

more others must be adjusted with value that are expressed in hexadecimal form ranging

from 0 to FF (that is from 0 to 63 in decimal form ).

Table 3 represent the value to be assigned to three parameter to properly set options:

Table 3 Option bye (1, 2 and 3) value and related meaning

BIT OPTIONB1 OPTIONB2 OPTIONB3

WEIGHT 0 1 0 1 0 1

0 BG 2° SCART FSU

1 L/L' MUST BE 1 BACKGROUND

2 I CINCH HOTEL

3 DK SVHS NTSC M

4 X RGB UV1316

5 X X V. GUARD

6 E.E.TXT W.E.TXT X

7 CATV X

PARAMETER VALUE

PICTURE IN PICTUREMODULE

SDA 9288X P.I.P. Pagina 1 di 4 e.g. sda9288xR.doc

SDA 9288X

PICTURE IN PICTURE

1 General Description

The Picture-in-Picture Processor SDA 9288X A141 generates a picture of reduced size of

a video signal (inset channel) for the purpose of combining it with another video signal

(parent channel). The easy implementation of the IC in an existing system needs only a

few additional external components. There is a great variety of application facilities

professional and consumer products (TV sets, supervising monitors, multi-media, …)

Data Sheet

• 212 luminance and 53 chrominance pixels per inset line for picture size 1/9

• 6-bit amplitude resolution for each incoming signal component

• Field and frame mode display

• Horizontal and vertical filtering

• Special antialias filtering for the luminance signal

16:9 compatibility

• Operation in 4:3 and 16:9 sets

• 4:3 inset signals on 16:9 displays or v.v. with picture size 1/9 and 1/16, respectively

Analog inputs

• Y, + (B-Y), + (R-Y) or Y, -(B-Y), -(R-Y)

Analog outputs

• Y, + (B-Y), + (R-Y) or Y, – (B-Y), – (R-Y) or RGB

• 3 RGB matrices: EBU, NTSC (Japan), NTSC (USA)

Free programmable position of inset picture

• Steps of 1 pixel and 1 line

• All PIP and POP positions are possible

2 picture sizes

• 1/9 or 1/16 of normal size

High resolution display

13.5 MHz/27 MHz display clock frequency

Freeze pictureI 2 C Bus control


Threefold PIP/POP facility

• Three different I 2 C-addresses (pin-programmable)

System Description

AD Conversion, Inset Synchronization

The inset video signal is fed to the SDA 9288X A141 as analog luminance and

chrominance components 1) . The polarity of the chrominance signals is programmable.

After clamping the video components are AD-converted with an amplitude resolution of 6

bit. The conversion is done using a 13.5 MHz clock for the luminance signal and a 3.375

MHz clock for the chrominance signals.

For the adaption to different application the clamp timing for the analog inputs can be

chosen (CLPS; CLPFIX). Setting this bits to ‘1’ can be useful for non-standard input

signals.

For inset synchronization it is possible to feed either a special 3-level signal via pin HVI

(detection of horizontal and vertical pulses) or separate signals via pins SCI for horizontal

and VI for vertical synchronization. SCI is the horizontal synchron signal of the inset

channel. If the burst gate pulse of the sandcastle is used it must be adapted to TTL

compatible levels by a simple external circuit. Centering of the displayed picture area is

possible by a programmable delay for the horizontal synchronization signal (HSIDEL).

The inset horizontal synchronization signals are sampled with 27 MHz. This 27 MHz clock

and the AD converter clocks are derived from the parent horizontal synchronization pulse

or from the quartz frequency converted by a factor of 4/3.

Delay differences between luminance and chrominance signals at the input of the IC

caused by chroma decoding are compensated by a programmable luminance delay line

(YDEL) of about – 290 ns … 740 ns (at decimation input

By analyzing the synchronization pulses the line standard of the inset signal source is

detected and interference noise on the vertical sync signal is removed. For applications

with fixed line standard (only 625 lines or 525 lines) the automatic detection can be

switched off.

The phase of the vertical sync pulse is programmable (VSIDEL; VSPDEL). By this way a

correct detection of the field number is possible, an important condition for frame mode

display.

Input Signal Processing


This stage performs the decimation of the inset signal by horizontal and vertical filtering

and sub-sampling. A special antialias filter improves the frequency response of the

luminance channel. It is optimized for the use of the horizontal decimation factor 3:1.

A window signal, derived from the sync pulses and the detected line standard, defines the

part of the active video area used for decimation. For HSIDEL = ‘0’ the decimation window

is opened about 104 clock periods (13.5 MHz) after the horizontal synchronization pulse.

For the 625 lines standard the 36th video line is the first decimated line, for the 525 lines

standard decimation starts in the 26th video line.

The realized chrominance filtering allows omitting the color decoder delay line for PAL and

SECAM demodulation if the color decoder supplies the same output voltages independent

of the kind of operation. In case of SECAM signals an amplification of the chrominance

signals by a factor of 2 is necessary because just every second line a signal is present.

This chrominance amplification is programmable via pin SYS or I 2 C Bus (AMSEC). The

horizontal and vertical decimation factors are free programmable (DECHOR, DECVER).

Using different decimations horizontal and vertical 16:9 applications become realizable:

DECHOR = ‘1’, DECVER = ‘0’: picture size 1/9 for 4:3 inset signals on 16:9 displays

DECHOR = ‘0’, DECVER = ‘1’: picture size 1/16 for 16:9 inset signals on 4:3 displays

PIP Field Memory

The on-chip memory stores one decimated field of the inset picture. Its capacity is 169 812

bits. The picture size depends on the horizontal and vertical decimation factors.

In field mode display just every second inset field is written into the memory, in frame

mode display the memory is continuously written. Data are written with the lower inset

clock frequency depending on the horizontal decimation factor (4.5 MHz or 3.375 MHz).

Normally the read frequency is 13.5 MHz and 27 MHz for scan conversion systems.

For progressive scan conversion systems and HDTV displays a line doubling mode is

available (LINEDBL). Every line of the inset picture is read twice. Memory writing can be

stopped by program (FREEZE), a freeze picture display results (one field).

Having no scan conversion and the same line numbers in inset and parent channel (625

lines or 525 lines both) frame mode display is possible. The result is a higher vertical and

time resolution because of displaying every incoming field. For this purpose the standards

are internally analysed and activating of frame mode display is blocked automatically when

the described restrictions are not fulfilled.

As in the inset channel a field number detection is carried out for the parent channel.


Depending on the phase between inset and parent signals a correction of the display

raster for the read out data is performed by omitting or inserting lines when the read

address counter outruns the write address counter.

The display position of the inset picture is free programmable (POSHOR, POSVER).

The first possible picture position (without frame) is 54 clock periods (13.5 MHz or 27 MHz)

after the horizontal and 4 lines after the vertical synchronization pulses. Starting at this

position the picture can be moved over the whole display area. Even POP-positions

(Picture Outside Picture) at 16:9 applications are possible.

Horizontal Decimation PIP PIXELS per Line

Having different line standards in inset and parent channels we have a so called mixed

mode display. It causes deformations in the aspect ratio of the inset picture. A special

mixed mode display is available for the picture size 1/9 (MIXDIS):

Synchronization of memory reading with the parent channel is achieved by processing

the parent horizontal and vertical synchronization signals in the same way as described

for the inset channel. The synchronization signals are fed to the IC at pin HP/SCP for

horizontal synchronization and pin VP for vertical synchronization. In the same way as

described for the inset channel the burst gate of the sandcastle signal can be used for

horizontal synchronization. In scan conversion systems also the inputs HPD/SCI and

VPD/VI are available if the input HVI is activated for inset synchronization.

2.4 Output Signal Processing

At the memory output the chrominance components are demultiplexed and linearly

interpolated to the luminance sample rate. Different output formats are available:

luminance signal Y with inverted or non-inverted chrominance signals (B-Y), (R-Y) or RGB.

For the RGB conversion 3 matrices are integrated: Matrix selection is done by pin SYS or I

2 C Bus. The matrices are designed for the following input voltages (100 % white, 75 %

color saturation):

SDA 9288X

Semiconductor Group 11 03.96

1.4 Functional Block Diagram

Figure 2

SDA 9288X

Semiconductor Group 42 03.96

4.2.5 Application Circuit (R, G, B-mode)

Figure 10

TDA8310A CHROMA DECODER FOR PIP Pagina 1 di 2 e.g. TDA8310A.doc

TDA8310A

PAL/NTSC colour processorfor PIP applications

FEATURES

• Video switch with 2 CVBS inputs. One input can beswitched between CVBS and Y/C and the circuit can

automatically detect whether the incoming signal is CVBS or Y/C

• Integrated chrominance trap and bandpass filters (automatically calibrated)

• Integrated luminance delay line

• Automatic PAL/NTSC decoder which can decode all standards available in the world

• Easy interfacing with the TDA8395 (SECAM decoder) for multistandard applications

• Horizontal PLL with an alignment-free horizontal oscillator

• Vertical count-down circuit

• RGB/YUV and fast blanking switch with 3-state output and active clamping

• Low dissipation (560 mW)

• Small amount of peripheral components compared with competition Ics

GENERAL DESCRIPTION

The TDA8310A is an alignment-free PAL/NTSC colour processor for Picture-in-Picture (PIP) applications.

The main difference between the TDA8310 and the TDA8310A is that the vision IF amplifier has been omitted

in the TDA8310A. Therefore, the circuit contains an input signal selector, a PAL/NTSC colour decoder, horizontal

and vertical synchronization and an RGB/YUV switch.

The input signal selector has 2 CVBS inputs. One of the inputs can be switched between CVBS and Y/C and the

circuit can automatically detect whether the incoming signal is CVBS or Y/C. The output signals for the PIP

processor are:

• Luminance signal

• Colour difference signals (U and V)

• Horizontal and vertical synchronization pulses.

• The RGB/YUV switch can select between two RGB or YUV sources, e.g. between the PIP processor and the

SCART input signal.

• The supply voltage for the IC is 8 V. It is available in a 52-pin SDIP package.


CVBS switch

The circuit contains a 2 input CVBS switch and one of the inputs can be switched between CVBS and Y/C.

The circuit contains an identification circuit which can automatically switch between the CVBS and Y/C signals.

It is also possible to force the switch to CVBS or Y/C.

TDA8310A CHROMA DECODER FOR PIP Pagina 2 di 2 e.g. TDA8310A.doc

Synchronization circuit

The sync separator is preceded by a voltage controlled amplifier which adjusts the sync pulse amplitude to a fixed

level. The sync pulses are fed to the slicing stage (separator) which operates at 50% of the amplitude.

The separated sync pulses are fed to the first phase detector and to the coincidence detector. The coincidence

detector is used to detect whether the line oscillator is synchronized and for transmitter identification. The first

PLL has a very high static steepness this ensures that the phase of the picture is independent of the line

frequency.

The line oscillator operates at twice the line frequency. The oscillator network is internal. Because of the spread of

internal components an automatic adjustment circuit has been added to the IC.

The circuit compares the oscillator frequency with that of the crystal oscillator in the colour decoder. This results in

a free-running frequency which deviates less than 2% from the typical value.

The horizontal output pulse is derived from the horizontal oscillator via a pulse shaper. The pulse width of the

output pulse is 5.4 ms, the front edge of this pulse coincides with the front edge of the sync pulse at the input.

The vertical output pulse is generated by a count-down circuit. The pulse width is approximately 380 ms. Both the

horizontal and vertical output pulses will always be available at the outputs even when no input signal is

available. In addition to the horizontal and vertical sync pulse outputs

the IC has a sandcastle pulse output which contains burst key and blanking pulses.

Integrated video filters

The circuit contains a chrominance bandpass and trap circuit. The filters are realised by gyrator circuits that are

automatically tuned by comparing the tuning frequency with the crystal frequency of the decoder. When a Y/C

signal is supplied to the input the chrominance trap is automatically switched off by the Y/C detection circuit

however, it is also possible to force the filters in the CVBS or Y/C position.

The luminance delay line is also realised by gyrator circuits.

Colour decoder

The colour decoder contains an alignment-free crystal oscillator, a colour killer circuit and colour difference

demodulators. The 90° phase shift for the reference signal is achieved internally.

The colour decoder is very flexible. Together with the SECAM decoder (TDA8395) an automatic multistandard

decoder can be designed but it is also possible to use it for one standard when only one crystal is connected to the

IC.

The decoder can be forced to one of the standards via the ‘forced mode’ pins. The crystal pins which are not used

must be connected to the positive supply line via a 8.2 κΩ resistor. It is also possible to connect the non-used pins

with one resistor to the positive supply line. In this event the resistor must have a value of 8.2 κΩ divided by the

number of pins.

The chrominance output signal of the video switch is externally available and must be used as an input signal

for the SECAM decoder.

RGB/YUV switch

The RGB/YUV switch is for switching between two RGB or YUV video sources. The outputs of the switch can be

set to high-impedance state so that other switches can be used in parallel.

The switch is controlled via pins 13 and 52.

1996Jan

254

Philips S

emiconductors


PA

L/NT

SC

colour processorfor P

IP applications

TD

A8310A

BLO

CK

DIA

GR

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hand

book

, ful

l pag

ewid

thMGD12846 45

PLL XTAL4

REF

44

XTAL3

43

XTAL2

42

XTAL1

R/W

COLOUR1

27 26

COLOUR2

25

LOGIC1

24

LOGIC2

23

B Y

R Y

50 51

GND1 GND3

18 38

LUMINANCE DELAY LINE Y

49

HUE28

4 IDENT

SECAM

484716

CHROMAI

917

INPUT SELECTOR

20

GND2 CVBSINT SYSTSW CHROMAO

CVBSEXT

31

AUTOMATIC Y/C

DETECTOR

15DECFT

32

33, 34

CHROMINANCE BANDPASS

CHROMINANCE TRAP

FILTER TUNING

SYNC SEPARATOR

VERTICAL SYNC

SEPARATOR

PAL/NTSC DECODER

VCO +

CONTROL

PHASE DETECTOR

COINCIDENCE/ NOISE

DETECTOR

n.c.

22, 29i.c.

CVBSSW

37

PH1LF

35

DECBG

21

DECDIG

41

VP2

30

INTB

19

VP1

HORIZONTAL/ VERTICAL DIVIDER

PULSE SHAPER

39

HOUT

36

VOUT

SANDCASTLE GENERATOR

40

SAND

TDA8310A

BLANK252

B23

G22

R21

BLANK5

B6

G7

R8

CLAMP14

BLANK113

B112

G111

R110

RGB/YUV SWITCH


1996 Jan 25 5

Philips Semiconductors Product specification

PAL/NTSC colour processorfor PIP applications

TDA8310A

PINNING


R2 1 RED input 2 (PIP)

G2 2 GREEN input 2 (PIP)

B2 3 BLUE input 2 (PIP)

IDENT 4 colour standard identification output

BLANK 5 blanking output

B 6 BLUE output

G 7 GREEN output

R 8 RED output

SYSTSW 9 CVBS/system switch

R1 10 RED input 1

G1 11 GREEN input 1

B1 12 BLUE input 1

BLANK1 13 blanking input 1

CLAMP 14 clamping pulse input

DECFT 15 decoupling filter tuning

CHROMAI 16 chrominance input

CVBSEXT 17 external CVBS/Y input

GND1 18 ground 1 (0 V)

VP1 19 supply voltage 1 (+8 V)

CVBSINT 20 internal CVBS input

DECDIG 21 decoupling digital supply rail

i.c. 22 internally connected (test purposes)

LOGIC2 23 crystal logic 2 input/output

LOGIC1 24 crystal logic 1 input/output

COLOUR2 25 colour system logic 2 input/output

COLOUR1 26 colour system logic 1 input/output

R/W 27 read/write selection input

HUE 28 HUE control input

i.c. 29 internally connected (test purposes)

INTB 30 internal bias


CVBSSW 32 CVBS positive/negative modulationcontrol switch input



DECBG 35 bandgap decoupling

VOUT 36 vertical sync output pulse

PH1LF 37 phase 1 loop filter


HOUT 39 horizontal sync output pulse

SAND 40 sandcastle pulse output

VP2 41 supply voltage 2 (+8 V)

XTAL1 42 4.4336 MHz crystal

XTAL2 43 3.5820 MHz crystal for PAL-N

XTAL3 44 3.5756 MHz crystal for PAL-M

XTAL4 45 3.5795 MHz crystal for NTSC

PLL 46 PLL colour filter

CHROMAO 47 chrominance output for TDA8395

SECAM 48 SECAM reference output

Y 49 Y output

B−Y 50 B−Y output

R−Y 51 R−Y output

BLANK2 52 blanking/insertion input 2 (PIP)


Secam secoder TDA8395 Pagina 1 di 2 e.g.TDA8395R

TDA8395

SECAM DECODER

FEATURES

• Fully integrated filters

• Alignment free

• For use with baseband delay

GENERAL DESCRIPTION

The TDA8395 is a self-calibrating, fully integrated SECAM decoder. The IC should

preferably be used in conjunction with the PAL/NTSC decoder TDA8362 or TDA8366 and

with the switched capacitor baseband delay circuit TDA4660. The IC incorporates HF and

LF filters, a demodulator and an identification circuit (luminance is not processed in this

IC). The IC needs no adjustments and very few external components are required. A

highly stable reference frequency is required for calibration and a two-level sandcastle

pulse for blanking and burst gating.


The TDA8395 is a self-calibrating SECAM decoder designed for use with a baseband

delay circuit.

During frame retrace a 4.433619 MHz reference frequencyis used to calibrate the filters

and the demodulator. Thereference frequency should be very stable during this period.

The Cloche filter is a gyrator-capacitor type filter theresonance frequency of which is

controlled during the calibration period and offset during scan; this ensures thecorrect

frequency during calibration.

The demodulator is a Phase-Locked Loop (PLL) type demodulator which uses the

frequency reference and the bandgap reference to force the PLL to the required

demodulation characteristic.

The low frequency de-emphasis is matched to the PLL and is controlled by the tuning

voltage of the PLL.

October 1991 3


SECAM decoder TDA8395


Fig.2 Pin configuration

PINNING


fref/ IDENT 1 reference frequencyinput/identification input

TEST 2 test output

VP 3 positive supply voltage



GND 6 ground

CLOCHEref 7 Cloche reference filter

PLLref 8 PLL reference

−(R−Y) 9 −(R−Y) output

−(B−Y) 10 −(B−Y) output





SAND 15 sandcastle pulse input

CVBS 16 video (chrominance) input

Secam secoder TDA8395 Pagina 2 di 2 e.g.TDA8395R

A digital identification circuit scans the incoming signal for SECAM (only line-identification

is implemented). The identification circuit needs to communicate with theTDA8362 to

guarantee that the output signal from the decoder is only available when no PAL signal

has been identified. If a SECAM signal is decoded a request for colour-on is transmitted to

pin 1 (current is sunk). If the signal request is granted (i.e. pin 1 is HIGH therefore no

PAL) the colour difference outputs (-(Β-Y) and -(Ρ-Y)) from the TDA8362 are high

impedance and the output signals from the TDA8395 are switched ON. If no SECAM

signal is decoded during a two-frame period the demodulator will be initialized before

another attempt is made also during a two-frame period. The CD outputs will be blanked or

high-impedance depending on the logic level at pin 1.

A two-level sandcastle pulse generates the required blanking periods and, also, clocks the

digital identification pulse on the falling edge of the burst gate pulse. To enable The

calibration period to be defined the vertical retrace is discriminated from the horizontal

retrace, this is achieved by measuring the width of the blanking period.

TEA6415C video matrix switch Pagina 1 di 1 e.g. TEA6415C.doc

TEA6415C

BUS-CONTROLLED VIDEO MATRIX SWITCH

DESCRIPTION

• 20MHz BANDWIDTH

• CASCADABLE WITH ANOTHER TEA6415C (INTERNAL ADDRESS CAN BE

CHANGED BY PIN 7VOLTAGE)

• INPUTS (CVBS, RGB, MAC, CHROMA, ...)

• POSSIBILITY OF MAC OR CHROMA SIGNAL

• FOR EACH INPUT BY SWITCHING-OFF THE

• CLAMP WITH AN EXTERNAL RESISTOR BRIDGE

• BUS CONTROLLED

• 6.5dB GAIN BETWEEN ANY INPUT AND OUT-PUT

• -55dB CROSSTALK AT 5MHz

• FULLY ESD PROTECTED

GENERALDESCRIPTION

The mainfunctionof the IC is to switch 8 video input sources on 6 outputs.

Each output can be switched on only one of each input. On each input an alignment of the

lowest level of the signal is made (bottom of synch. top for CVBS or black level for RGB

signals).

Each nominal gain between any input and output is 6.5dB. For D2MAC or Chroma signal

the align-ment is switched off by forcing, with an external resistor bridge, 5 VDC on the

input. Each input can be used as a normal input or as a MAC or Chroma input (with

external resistor bridge). All the switch-ing possibilities are changed through the BUS.

Driving 75Ω load needs an external transistor. It is possible to have the same input

connected to several outputs.

The starting configuration upon power on (power supply : 0 to 10V) is undetermined. In

this case, 6 words of 16 bits are necessary to determine one configuration. In other case, 1

word of 16 bits is necessary to determine one configura-tion

TDA4665 Crhroma Delay line Pagina 1 di 3 e.g.TDA4665.doc

TDA4665

Baseband delay line

FEATURES

• Two comb filters, using the switched-capacitor technique, for one line delay time (64 ms)

• Adjustment-free application

• No crosstalk between SECAM colour carriers (diaphoty)

• Handles negative or positive colour-difference input signals

• Clamping of AC-coupled input signals (±(Ρ-Y) and ±(Β-Y))

• VCO without external components

• 3 MHz internal clock signal derived from a 6 MHz CCO, line-locked by the sandcastle

pulse (64 ms line)

• Sample-and-hold circuits and low-pass filters to suppress the 3 MHz clock signal

• Addition of delayed and non-delayed output signals

• Output buffer amplifiers

• Comb filtering functions for NTSC colour-difference signals to suppress cross-colour

GENERAL DESCRIPTION

The TDA4665 is an integrated baseband delay line circuit with one line delay. It is suitable

for decoders with colour-difference signal outputs ±(Ρ-Y) and ±(Β-Y).

1996D

ec17

3

Philips S

emiconductors


Baseband delay line

TD

A4665

BLO

CK

DIA

GR

AM


handbook, full pagewidth

SANDCASTLE DETECTOR

FREQUENCY PHASE

DETECTOR

DIVIDER BY 192

LP

VP2

3 MHz shifting clock

1digital supply

LINE MEMORY

SIGNAL CLAMPING

SAMPLE- AND-HOLD

6 MHz CCO

DIVIDER BY 2

LP

addition stages

output buffers

colour-difference output signals

colour-difference input signals

12

2

5

10

GND1

3

n.c.6

n.c.13

n.c.15

n.c.

7i.c.

4, 8

±(B−Y)

±(R−Y)

±(R−Y)

±(B−Y)

VP1

sandcastle pulse input

GND2

9

14

LINE MEMORY

TDA4665

SIGNAL CLAMPING

pre-amplifiers

SAMPLE- AND-HOLD

LP

11

16

analog supply

MED848

SAA55xxStandard TV microcontrollers with On-Screen Display (OSD)

1 FEATURES

• Single-chip microcontroller with integrated On-Screen Display (OSD)

• Versions available with integrated data capture

• One Time Programmable (OTP) memory for both program Read Only Memory (ROM)

and character sets

• Single power supply: 3.0 to 3.6 V

• 5 V tolerant digital inputs and I/O

• 29 I/O lines via individual addressable controls

• Programmable I/O for push-pull, open-drain and quasi-bidirectional

• Two port lines with 8 mA sink (at <0.4 V) capability, for direct drive of Light Emitting

Diode (LED)

• Single crystal oscillator for microcontroller, OSD and data capture

• Power reduction modes: Idle and Power-down

• Byte level I 2 C-bus with dual port I/O

• Pin compatibility throughout family

• Operating temperature: -20 to +70 °C.

2 GENERAL DESCRIPTION

The SAA55xx standard family of microcontrollers are a derivative of the Philips industry-

standard 80C51 microcontroller, and are intended for use as the central control

mechanism in a television receiver. They provide control functions for the television

system, OSD, and some versions include an integrated data capture and display function.

The data capture hardware has the capability of decoding and displaying both 525 and

625-line World System Teletext (WST), Video Programming System (VPS) and

Wide Screen Signalling (WSS) information. The same display hardware is used both for

Teletext and OSD, which means that the display features available give greater

flexibility to differentiate the TV set.

The SAA55xx standard family offers a range of functionality from non-text, 16-kbyte

program ROM and 256-byte Random Access Memory (RAM), to a 10-page text version,

64-kbyte program ROM and 1.2-kbyte RAM.

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5 6 7 8

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R291K

R2147K

R281K

1

2

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4

5

6

7

8

9

10

11

12

13

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16

17

18

19

20

21

22

23

24

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29

30

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37

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44

45

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47

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49

50

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52

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56

57

58

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60

61

62

63

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IC1 TDA 9870A

R2747K

R221K

R23

1K2

R24

1K2

R1347K

R1247K

R18

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R384,7

R394,7

R810K

R910K

QZ124,576MHZ

5

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L1100µH

R1

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R2

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L2

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L3

100µH

123

IC2KIA7812

TR1BC848

TR2BC848

TR3BC848

TR4BC848

C11470N

C122µ216V

C132µ216V

C142µ216V

C18470µ10V

C152µ216V

C162µ216V

C172µ216V

C1910N

C2010N

C2147µ16V

C222µ216V

C232µ216V

C242µ216V

C25

2µ216V

C26470µ35VC27

2µ216V

C282µ216V

C292N2

C302N2

C3147µ16V

C32

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C43

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C3347µ16V

C34330N

C44

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C35330N

C362µ216V

C372µ216V

C38100µ16V

C39100µ16V

C401000µ16V

C411000µ16V

C421000µ16V

C452µ216V

C462µ216V

06

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Main outR

Main outL

Line outL

AP

Line outR

VDDD2

PCAPL

VDEC1

VSSD4

XTAL OUT

VSSA4

VSSD2

VSSD3

VDEC2

VREF(P)

VREF(N)

Sc1 outL

Sc1 outR

VREF2

VSSA2

I.C.

CUFFIASC1/SC2CINCH

VREF1

SIF2

Port 1

IREF

SIF1

VSSA1

I2C addr1

NICAM data

PCLK

SCL

SDA

I2C addr 2

VSSD1

VDDD1

RESET CAP

I.C.

BB

I.C.

I.C.

Sc2 InL

Sc2 InR

Sc2 outR

Sc1 InL

Sc1 InR

Sc2 outL

Ex InL

Ex InR

XTAL IN

TEST2

MONO IN

PORT2

SYSCLK

SCK

WS

SDO1

SDO2

SDI1

SOI2

TEST1

53

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R6210K

C202µ216V

C592µ216V

C621000µ16V

C631000µ16V

C67100µ16V

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C53330N

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R3847K

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R641K

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L86.8µH

R1022

C412µ216V

C681000µ16V

1234

5 6 7 8

IC4 TDA2822M

R22

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C33100N

C652N2

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R4147K

R4047K

R2022K

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R694,7

R5710K

R5610K

C492µ216V

C482µ216V

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C552µ216V

C4547µ16V

L177,8MHZ

C542µ216V

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C32µ216V

R711K

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C18

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1

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5

6

7

8

9

10

11

12

13

14

15

1617

18

19

20

21

22

23

24

25

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27

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29

30

31

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IC1TDA 9811

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1

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5

6

7

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10

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13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32 33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

IC3 TDA 9875

C3610

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C29100N

10

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8

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9

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6

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7

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1

A2

-A

2

A2

-B

4

A2

-D

10

A2

-J

11

A1

-K

R45

47K

R4847K

R52

1K2

R51470

R431K

TR10BC848

R421K

TR9BC848

L3

100µH

R6510K

R6610K

R681K8

R671K8

C46470µ35V

C321µ16V

C31470N

R34390

C121000µ16VTR5

BF 959

R173K9

R13

150

R12

1K

TR4BF 959

R15120

R1447

C131N

L21µH

R11100

FOS1K9453

R74K7

C10100N

R8

47K

TR3BC848

C9100N

TR2

BC848

R64K7

C71N

C15470µ10V

L4

100µH

R44

12

R722K2

R732K2

C37470N

1

A3

-A

2

A3

-B

3

A3

-C

C382µ216V

C702µ216V

C712µ216V

R36270

C17470N

C51000µ10V

C69470µ16V

6

A1

-F

R37

820

R2

22K

L7

100µH

R74

18

R1220

R771K2

C72

220µ16V

R78100

R75

270F1TPS6,5

TR1BC848

R761K5

L5100µH

R334,7

R32

10K

C27470N

R7910K

R29

100R30

100

D1LL103BA682BA782BA783

D2LL103BA682BA782BA783

FOS2K3953M

C401000µ10V

BB

2

5

4

2

1

3

3

5

4

1

VIF1

VIF2

Cbl

VIF3

VIF4

AP

TAdj

Tpll

CsAgc

STD

CVBS

LSW

NC

NC

NC

NC

NC

SIF2

SIF1

INSW

Vp

CvAgc

GND

CUFFIASC1/SC2CINCH

VREF1

SIF2

Port 1

IREF

SIF1

VSSA1

I2C addr1

NICAM data

PCLK

SCL

SDA

I2C addr 2

VSSD1

VDDD1

RESET CAP

Cref

05

/07

/20

00

VoAf

MUTE

TAGC

VoQss

Sc2 outR

Vo

Vi

Sc2 outL

AFC

VCO1

XTAL IN

VCO2

S

PORT2

SYSCLK

SCK

WS

SDO1

SDO2

SDI1

SOI2

TEST1

MONO IN

TEST2

Ex InR

Ex InL Sc1 InR

Sc1 InL

Sc2 InR

Sc2 InL

I.C.

I.C.

I.C.

I.C.

VSSA2

VREF2

Sc1 outR

Sc1 outL

VREF(N)

VREF(P)

VDEC2

VSSD3

VSSD2

VSSA4

XTAL OUT

VSSD4

VDEC1

PCAPL

VDDD2

Line outR

Line outL

Main outL

Main outR

VDDA3

AUX outL

AUX outR

VSSA3

PCAPR

VREF3

OUTSC

51

1.0

4S

51

1.0

5S

Di M

aio

1.511.05S

Ste

reo

-Nic

am

pe

rTe

laio

F1

9

C62IC5

C50

J3

C49

IC4

C67

FOS1

C66

L8 C68

C38

C72

C53C52

J10

C51

J6

C48

C54

C63

J9C40

IC1

A1 A2R28

C47

L1

FOS2

IC3

L7

J8

F1

C32

C15

IC2

QZ1

J4

TR5

C17

TR4

L2

C45

C55

R20

C4

C3

R33

C71

L4

L3

C58

C59

C60

C61

R59

R60

J2

R30

R29

R37

R44

C46

L5

C12

C5

J5

C39C70

J7

C20

C1

R74

C69

A3

C56

C42

C57

C41

C26

1.511.05S

1 12 1 10

TOP SILK

BOT.E

LEC.

1.511.05S

Industrie Formenti Italia s.p.a.Stabilimento di Sessa Aurunca (CE)

Disegnato: Approvato:

Descr.

Sost.schema:

Cod. Schema:Data:

Scala:

V 1,8Vpp

H 60Vpp

V 3Vpp

H 2VppH 2Vpp

V 45Vpp

V 11Vpp

H 150Vpp

H 12Vpp

V 12Vpp

H 2,5Vpp

V 5Vpp

H 5,6Vpp

1,5Vpp

0,5Vpp

H 1Vpp

H 2,5Vpp

H 2Vpp

H 8Vpp

H 40Vpp

V 5Vpp

H 500Vpp

H 1Vpp

H 10Vpp

H 1200Vpp

H 70Vpp

H 2,5Vpp

H 1,4VppH 1,4VppH 1Vpp

H 8VppH 27Vpp

H 120Vpp

H 100Vpp

H 100Vpp

H 100Vpp

H 2Vpp

V 1Vpp

+5V

+8V

+12V

+28V STBY

+8V

+8V

+12V

+12V

+12V

+12V

+5V

+8V

+12V

+148V/128V

+5VSTBY

+12V

+8V5

+5V

+5VSTBY

+27,8V

+27,8V

+8V5

+12V

+8V

+12V

+12V

+5VSTBY

+8V

+12V

+28V STBY

+148V/128V

+27,8V

+8V5

+8V

+5VSTBY

+12V

+8V

+8V

+12V

+5V

+12V

+5V

+12V

+5VSTBY

+5VSTBY

+5V

+8V

+12V

+5VSTBY

+5V

+3V3

+3V3

+5V

+12V

+5V

+12V +12V +12V +12V

+5V

+5VSTBY

+5V

+5V

+5V

+8V

+12V +12V

+12V

+5V

+5V

+5V

+5V

+5V

+5V

+5V

+5V

+5V

+5V

+5VSTBY

+12V

+5V

+5V

+12V

+5V

+5V +12V

+12V

+8V

+12V

+8V

+8V

+5V

+3V3

+3V3

CH3AUDIO

RIGHT IN

CH2AUDIOLEFT IN

7

25

R105

1

C612220

D203ZTK33B

R24110K

R243

4K7

D202

BA 157

46

48

C4041n

6

TR575BC848

19

R620 120K

C2631n

R70

0,1

13

L261,2mH

R526330

1

A4

R67

82K

54

51

13

48

49

C26100n

R104

4K7

C21647n

TR208BC 548B

TR108BC 548B

C2662µ2100V

2

A4

C4051n

29

J53

JS201

F576

TR502BC858

C288330n

28

C242100n

R242

680

C2931n

F575

30

3

C26710µ100V

R25075

R151

470

TR205BFS 19

R27812K

TR501BC858

TR215BC 548BC506

100

15

3

A4

TR7BC547B

4

R14215K

R14310K

R50233K

C290330n

R50112K

TR216BC 548B

TR217BC 548B

C113100n

D1011N4148

C2321µ16V

43

JS10

C503100n

C504100n

R10310K

TR503BC858

C502330N

C112100n

C505100n

R87

0,39

C23147µ16V

91317

R50610K

C10318

1814

R619100

3A601-C

C105100n

QZ10012MHZ

C10218

R267

12KD104

1N4148

X3

26

JS501C501330n

R88

0,1

R600

1K

C601100n

R296

1K

31

C224100n

R297

100

C53 68n

54

32

78

1

H1

C107100µ10V

10

1

2A601-B

39

2 9

C2342n2

76

3

A11

C10068n

C500100n

TR8BC547B

R5034K7

R1715K6

TR213BF 959

R5124K7

R5114K7

R513

2K2

D5ZPD2V7

R504

2K2

R1705K6

12

R505

2K2

R617

1K8

R618

1K8

R40560

R391K

C150100n

C106100µ10V

C615100

R113

1

D6011N4148

14

20

21

18

53

8

7

44

D607ZPD9V1

R6041K

R6051K

27

31

32

R6061K

1

A6

00

-A

D6021N4148

D6001N4148

D611BAV103

1

A601-A

D103

1N4148

R286120

C23310µ16V

C104100µ10V

R76820

19

D610BAV103

C237100

2

A11

R285

120

C283100µ16V

20

21

4

34

C4061n

C223100n

C222100µ10V

35

R293

150

R245100

18

20

R219

4,7

R237

47K

QZ2014,43

D609BAV103

4A601-D

5A601-E

6

A601-F

C60047µ16V

R62982

2A6

00

-B

3 A600-C

C252100n

R226470K

R225470K

R236470K

JS13

10

A8

R27039K 2%

JS200

C2811n

R1731K

R163

0

6

2

8

4

21

6

R68390

R254 560

C82100µ25V

R253 560

2

5

C215220n

C282100n

R246100

R247100

1714

1395

C212 2n2

21

R251 560

CH1VIDEO IN

R94820

20

36

19

8

16

7

11

15

R184100K

8

R509

5K6

C209 22n

C210 22n

C211 22n

C65470µ35V

R77820

R9222K

R7556

R252 560

R310

47K

R1914K7

R613

68K

R614

68K

R615

68K

C602 22

C6062µ2250V

C605100n250V

C604 27

C603 82

C6072µ2250V

D6081N4004

C608100n250V

C6102n21KV

X10

D6041N4148

D6031N4148

D6051N4148

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

IC600 STV 5112

R860,1

R8439L24

BV53-120

C711µ100V

R8215K

R8315K

L22BV52-105BV52-109

R811K2

D25BA 157

C6922n400V

C78

150n100V

41

C61100n250V

37

52

49

50

TR214BF 959

R2992K7

C295100n

R3002K7

TR218BC848

JS202

4

A1

3-D

3

A1

3-C

R3084K7

4

5

3

2

1

F204L9454M

2

A1

3-B

1

A1

3-A

5

A1

3-E

1 2 3 4 5 6 7 8

910111213141516IC102 TDA 9830

TR219BC848

R230 47

D201

BAT 81

R178

10K

R176

10K

D1061N4148

27

36

C101470n

D1071N4148

D1081N4148

R106

1

41

44

TR101BC848

42

23

24

26

25

C111100n

C110100n

37

40

43

38

3

2

1

5

4

11

10

30

JS105

9

22

39

R17715K

JS1020

R169100K

12R179

47K

R5081K2

R148

47K

R180100K

R18110K

47

45

R155100K

R147

47K

R164

15K

19

C400100n

C4951n

C4822200µ35V

C4812200µ35V

C48368n

C4541n

C401220µ25V

123456789

IC400TDA1521ATDA2613

JS450

JS451

6

A1

3-F

8

A1

3-H

10

A1

3-J 7

A8

11

A8

9

A8

5

A8

12

A8

9

A115

A117

A116

A1110

A11

C29110µ16V

R2984K7

R3122K7

C296100n

R115

1K

33

34

35

R161

10K

TR107BC848

R16515K

R159

47K

15

16

C219 18

C205 18

C221 3N3

51

52

L21

5,6 µHBV53-130

D23

BA 157

1

2

3

4

T2

R80

47

C5610n

1

2

3

4

5

6

7

8

9

IC5TDA 8351

33

C52470µ50V

C5422n

R561,8

C5822n

R574,7

45

R221100

42

40

R280

10K

C277100n

F2005,5

R209 390

F2014,5-6,5

L2056,8µH

R2061K

R208330

R213150

R2101K

R217

100

R216

100

R215

100

C276100

R2902K7

C2643n3

14

56

55

2

1

9

13

38

17

10

23

24

5

28

R551100

R552100

R153100

R101 100

R100 100

R15415K

C57220n

R168

47K

1

A11

JS7

22

R304

47K

R3051K

R30118K

R30347K

R5314K7

R5304K7

C29210µ16V

JS203

C204 100n11

29

D2041N4148

C4071n

L40147MH

C289100n

50R276

100K

TR211BC848

R27347K

C249

10µ16V

R288150

C29710µ16V

C294 10µ16V

C26010µ16V

C24710µ16V

C245

10µ16V

C279100n

C251100N

C2501000µ16V

1

3

7

19

18

17

12

13

14

2 10 6

15

11

16

20

9

5

84

IC201LA7955

R2351K5

C278100N

C280100n

JS9

JS8

C244100n

14 12

13

11

IC200-A

45

3

9

IC200-C

15 2

1

10

IC200-B

16

6 7 8

IC200-D

R26247K

R26347K

R26447K

R26547K

C29810µ16V

C29910µ16V

C2741n

C2751n

C24810µ

16V

C25510µ16V

C2721n

R271150

R27747K

TR212BC848

R279330

C259

10µ16V

R256

560

R255

560

R233

47

R257 560

R258 560

TR103BC848

32

TR102BC848

18

17

16

R2291K

C2381000µ16V

TR204BC848

R2321K

R228

1K

L2063,3µH

TR201

BC858

TR210BC848

C236100

R50

3K3

TR111BC 548B

TR209BC 548B

TR109BC 548B

TR203BC 548B

TR105BC 548B

R7347K

46

47

C2281n

C2291n

TR12BUK474200A

TR15BC 639

D51

BA 157

6

C203100N

TR200BC848

R205330

R313100K

3

1

3

1

R624

1M

TR600

BF 422

C60910µ100V

R85 10

D27BA 157

C75

5n6400V

QZ2003,57954MHZ

R42482

R42582

R5822

L40047MH

L48047µH

L48147µH

R202 100

R203 100

R227

1K

TR202BC848

R21475

R200

390

R890,1

R507220K

TR500BC 550C

R152

0

D1001N4148

R102

15K

C576

68

C5771µ

QZ2023,58205

TR206BFS 19

R238

47K

R79

1,5

R640,1

TR16BU 508D

R90

150K

R114

24KC109100n

R627470K

D6061N4148

R6261K8

R616

1K8

R167

15K

R146

15K

R107

1K

R3061K5

R292120

R2891K

R295120

C2841n

R29447

C285

1n

L2071µH

D105ZPD2V4

R211

47K

R207

100K

C220100n

C2252n2

5

4

3

2

1

F203K3953

JS500

L201BV53-106

1µH

C20847n

C214100n

C24610µ16V

C2731n

C25410µ16V

C25710µ16V

R224

680

R311

8K2

D22BA 157

R188330

R91

150K

C24010µ16V

C23910µ16V

R491 82

R490 82

JS490

R27533K

JS1000

R128

15K

JS1040

R174

15K

X13

R13115K

R287100

C25610µ16V

GND

IR

Vcc

IRR100

R284 220

R283 220

R282 220

R528100

TR525BC848

C265100µ16V

R52547

R5271K

R248100

R6610K

D20

1N4148TR11BC858

C26110µ16V

R244

150

R118

100

R116

100

R117

100

3

4 KEY1-BSEL

7

8KEY1-DP-

9

10 KEY1-EP+

1

2 KEY1-AANA-

5

6 KEY1-CANA+

1 3 2

IC203L7806CV

R5754K7

R5764K7

C575220µ25V

JS525 JS526

R240

100K

C551470µ10V

C550100n

R651K

R15610K

R160100K

R13915K

C2302µ216V

R3071K

R302

47K

R1722K7

R175

15K

C34n7500V

C54n7500V

C24n7500V

D11N4007

C311000µ10V

C1233n630V

R15 4M7

R34K7

R30330K

D8

1N4148

R31330K

C20100µ250V

C271000µ10V

C154n7

C172n2400V

R204K7

JS11

R194K7

C19100n250V

2

3

4

6

8

9

10

11

12

15

16

T1

D21N4007

PTC1

R11220

C7150µ400V

C62n2400V

C114n7

R104K7

C32100

TR1STH7N90FI

R5

4,7

C44n7500V

D4

1N4007

D3

1N4007

C1

10n250V

8765

4 3 2 1

IC1 TDA 4605

D13BA157

C252200µ35V

C24100nX2

D7BYV95C

C144702000V

R268K

C161µ63V

R12

820 R142K2

C847µ25V

R1

150K

D10BYV95C

C21330500V

R16

0,1

L4

L5C10220n

D6

1N4148

R8

390KR9

560K

R13

3K9

R7

10K

R32100K

D9BYV95C

C18330500V

JS1

JS6

R17

0,1

R334,7

R447

D11BYV95C

C22 330500V

R180,1

C23 330500V

D12BYW95A

1 2 3 4 5 6 7 8 9

IC10 TDA 8138

R21

47K

TR5BC 548B

R271K

TR2BC 548B

C301000µ25V

R264K7

C291000µ16V

R242K2

C281000µ16V

TR3BC848

R2310K

TR4TIP 115

1 2 3

IC202L78M08CS

C2411000µ10V

R2247K

R29

4K7

C55220n

C512200µ25V

C731µ250V

C79100n400V

C721µ350V

D26BA 157

31

L20

10MH

L25610µH

L3

BV53-1172*47MH

L247MH

L147MH

C9680N400V

FUS1T2AH250V

C76680n250V

D24BY228

C702n21,6KV

C6810n

1,5KV

C4842µ2100V

C4962µ2100V

C6142n21KV

C2531000µ16V

R190330

R189330

X1

R281 10K

R53

270

R51

33K

TR207BC 338-40

R712K2

R266220

R7810K

C664n7

L23

100µH

C59100µ25V

R28

220

R628 100

C2062µ216V C235

10µ16V

JS3

JS2

JS4

TR220BC848

C243470

C262470

R29147

11

6

8

10 9 5 7 1

R647

R309

4K7

R93

4K7

R5774K7

R26875

R126 5K6

R127 5K6

R18212K

R2232K7

R26118K

R510390

R21275

R239

560

R578390

R26947K

R23175

C21822n

C21722n

JS502

R252K2

C2874µ7

16V

C2864µ7

16V

R22015K

C2261µ16V

C2274n7

C25810µ16V

C672µ2100V

R6110K

R60

220

R13715K

R13815K

R13312K

R13212K

TR110BC848

R18310K

R260330

R14422K

D1021N4148

R18510K

R16615K

TR6BC 638

1

3

5

6

7

8

9

10

11

12

T3

LED1

X12

R192680

R272560

R314560

R27412K

X4

R123

15K

R121

15K

R122

15KX5

R4028,2

C41322n

C4022200µ35V

C4512200µ35V

C45022n

R4508,2

X14X6

X7

X8

1

2

3

45

6

7

8

IC101ST24C04CB

R140 5K6

R141 5K6

C626n8 D50

1N4148

D531N4148

C20118

R621

10M

C8010µ100V

R3747K

R43

10K

R3512K

R550,1

D52BA157

C81680n

R59

39K

R3412K

R36

47K

R38

47K

D21

BA 157

D28

BA 157

JS12

C77150n

C50

47n

R54

27K

C60 68

C213

1000µ10V

C207100n

12

R201

1KR2592K7

C30082

R6101K

R6111K

R6121K

C611220

C613220

R622560

R623560

R62518K

R601 680

R602 680

R603 680

C2681n

C2691n

R249100

C2701n

C2711n

C7410µ250V

D1091N4148

TASTO1

R1581K

R1571K

R1621K

R187270

R186270

R150270

J85

J2

J71

J4

J34

J147

J6

J73

J35

J7

J75

J8

J37

J116

J9

J76

J39

J79

J13

J15

J86

J49

J14

J54

J16

J87

J17

J18

J95

J19

J22

J69

J23

J98

J24

J60

J25

J99

J26

J61

J27

J100

J32

J148

J102

J66

J103

J108

J33J29

J31

J40

J88

J41

J126

J97

J43

J134

J46

J47

J107

J117

J118

J82

J119

J83

J125

J84

J124

J111

J109

J113

J115

J114

J136

J139

J140

J142

J1

J5

J59J70

J104

J10

J20J3

J12J55J96

J105J106

J89

J21

J90

J28

J91

J30J38

J149

J92

J36J65

J94

J42

J93

J44

J45

J101

J110

J48J74

J50

J51

J112J128

J52

J131J132

J133

J56J130

J135

J62

J137

J64

J138

J67

J141

J68

J144

J72

J145

J77

J146

J78

J120J121

J123J127

2 A400-B

1 A400-A

4

A1111

A1112

A118

A11

1

A8

2

A8

4

A8

3

A8

4 A400-D

3 A400-C

1

A7

2

A7

3

A7

4

A7

5

A7

6

A7

10

A10

9

A10

8

A10

7

A10

6

A10

5

A10

4

A10

3

A10

2

A10

1

A10

12

A10

11

A10

9

A1

3-I

7

A1

3-G

2

A1

4-B

1

A1

4-A

1 A15-A

2 A15-B

6

A8

8

A8

10 11543 8

3

A6

2

A1

3

A1 1A1

1

A6

2

A6

2

A2 1A2

2 A3

1

A3

4

A3

3

A3

3

A12

2

A12

1

A12

1

A5

2

A5

3

A5

4

A55

A5

D200ZPD

8V2

1

A9

2

A9

3

A9

4

A9

5

A9

6

A9

J63

R145

22K

R119820

J122

D205

BA 682D206

BA 682

R42 75

R41 75

J57

R6982K

12/09/2000

B-Y in

SYNC SEP.+

1st LOOP

VCO +CONTROL

+1

2V

STEREO NICAM

+6

V

GN

D

INTE

R.

2

L.SC

OU

T

R.S

CO

UT

VdriveB

RSC

in

Solo con modulo zero power

LSC

in

AM

/FM

IN

BASE BANDDELAY LINE

SWTV

/AV

Non inserire con modulo zero power

200V

DRAM3K TO 28K

6V3

RED

H/VDIVIDER

Y in

DEGAUSS

IC100SAA5553M3

IC204

TDA 8844

IF1

LIVE AREACOMPONENTI SOTTO RETE

VSSA

PORT 3

+2

6V

R.A

PO

UT

I ref

SRAM256 Bytes

EX.L

.O

UT

EX.R

.O

UT

CVBS0

CVBS1

FBlank

R-Y in

CHROMA TRAP+

BANDPASS

ROM16K TO 128K

H.Sync

PORT 2

230V

DATASLICER

GN

D

AUDIO out

I2C BUSTRANSCEIVER

FRAME

CORB

V.Sync

X out

VERT. SYNCSEPARATOR

BLACK-CURRENTSTABILISER

VoltageTuning

X in

X gnd

S.FILTER

~

RESET

ACQUISITIONTIMING

TEXTINTERFACE

DISPLAY

VSSP

DSC

L.A

PO

UT

StatusFormato

PLL IF

FILTERTUNING

SWITCHSC1/SC2

REF

LUMA DELAYPEAKINGCORING

POL

SW AM/FM

COL.AUT.SW.XTAL

SCL1

SWB-Y out

CTI - 16:9

3

VIDEOAMPLIFIER

TOP

CVBSSWITCH

CD MATRIXSAT CONTROLBLUE STRETCHSKIN TINT CORR

VIDEOIDENT

+128V

*

TELAIO BASE F19

** MOUNTED L25OR L26

GN

D

5W

+1

2V

1

IDENT

COPYSC1 to SC2

SDA

IF

Tuner AGC

SAT

SCL

1

Y out

IF AGC

BLACK STRETCHRGB MATRIXRGB1 INPUT

REF

Bin

FOC

G2

6

5

PIP

GND

CONTROL DAC1x8 BITs14x6 BITs1x4 BITs

BL.Curr.

3

VHF-L

PAGERAM

GREEN

SOUND MUTE

VHF-H

TELETEXTACQUISITION

VdriveA

4

DISPLAYTIMING

497.06B497.07B

4

+12V

DATA

Gin

SecPllDec

UHF

SC1

Rin

V Iref

RED

SOUNDPRE AMP+MUTE

ADDRESS

SVHS-C

BLUE

RIGHT

1

PLL

LEFT

Blue

2CUTOFF

Digi DEC

5

Vsawtooth

Phi-1

Green

3

3

PLL FMDEMOD.

2

TUN

Red

1

IF1

6

AGC FORIF + TUNER

WHITE P.

IF2

G2

TO RGB

-

6

5

+5V

SVHS-Y

4

3

2

SC2

2

AV

VIDEO IFAMPLIFIER+ PLL DEMOD.

+5V

1

AGC

ADJ.

TS

GND

+148V

BRIG.

CVBS -Y/CSWITCH

SCL

PAL/NTSC

SECAMDECODER

+5VIF2

SDA

1

DI MAIO

+

B

G

R

VIDEOMUTE

Phi-2

EAT

110

FOC

R

G

B

0

INTO

7

SDA1

SW 16/9

StatusCTI

MSCL

MSDA

PORT 1

80C51MICRO-

CONTROLLER

OSCILLATOR

VDDA

3° SYS

+

-

EAT

IF1

+5V

KEY0

TIMER/Ctrs

KEY1

StatusAV2

GREEN

StatusPIP

SWITCHL/L"

KEY2

BLUE

StatusAV1

BLNK

ONLY FORAUTOMATICTESTING

StatusCuffia

PORT 0

ON/OFF

VSSC

VPE

VDDP

SWITCHCINCH/SC

PWM

ADC

I2C

SW TV/AV

CVBS input

CVBS1 out

CVBS int

Supply

VOL.

AGCSW.SWITCH

+VOLUME

AFC

AvlCapEW-drive

VERT.YOKE

IF

VIDEO out

CONTR.

RGB CONTROL

+OUTPUT

Sand.

+33V

SIF

ADD SDA

Bandgap

GND

UHF VHIGH

S.DEC

VLOW

H. out

AFC

Beam Current

EHT

De Emph.

EXT.S.in

HUE

XTAL 3,57

PIP

Chroma Ref

Colour PLL

XTAL 4,43-3,58

VIDEO

MUTE

16V

VERTICALGEOMETRY

2nd LOOP+

HOR. OUT

LIMITER

EW-GEOMETRY

R-Y out

8

FB

AV

VIDEO OUT

RIGHT IN

LEFT IN

LEFT OUT

RIGHT OUT

VIDEO IN

RED IN

GREEN IN

BLUE IN

RIGHT IN

LEFT IN

VIDEO IN

VIDEO OUT

RIGHT OUT

LEFT OUT

IC200HEF4053

BLNK

VCC

MOUNTEDJS1 OR JS6

SCL

S.T.

SOLO PER STEREOSOLO PER MONO BG/L L"

SOLO PER DOPPIA SCARTSOLO CON SINGOLA SCART

9 10

SOLO PER SINTESI DI TENSIONE

11

12

12

SOLO PER SINTESI DI FREQUENZA

SOLO PER MONOSOLO PER MONO BG

A

B

C

D

E

F

G

H

1110987654

A

B

C

D

E

F

G

H

31 2

3

3

2

1

2

VDDC

D60

2

D107

R8

C291

D28

R617

L480

C246

R527

J30

R625

R32

C4

C15

R21

C216

J24

C245

D605

R603

R618

C299

J83

JS11

C401

C52

L22

R100

C267

C76

D7

C208

D60

1

R87

D20

D11

D10

J72

C614

R13

L400

R15

C107

C451

C247

L481

D60

4

C402

X2

R513

C406

C404

C222

R230

A6

DIS

1

C101

R200

R606

J36

R9

D106

R7

R623C32

C256

J42

L1L2

L206

L21

R5

C265

D202

D1

R151

C8

C19

L4

C2

R311

R268

D24

K1

C14

A5

D204C9

R85

D51

IRR100

IC60

0

TR108

L24

R219

C11

K3

R224

R90

R605

D3

C71

C206

C5

L207

C232

R153

K2

A15

C255

R613

R11

R33

C607

L3

C261

R244

C250

R104

R602

C254

R116

IC200

F576

D4

R117R118

F575

C260

C1

R4

A2

A11

R233

C259

A10

C240

IC204

C18

C20

J147

C604

R3

TR8

R159

TR16

C238

D9

TR7

D2

K4

SC2SC1

J110

A7

R25

A601

R601

T1

TR4C57

X1

PTC1

A1

R94

R142

R76

C58

K5

D201

F200

F201

R18

QZ202

C226

QZ201F203

D101

D100

C606

C253

QZ200

X13

IC100

QZ100

C239

C28

R626

R614

C605

D60

0

C252

C481

C577

F204

A8

IC102

C230L201

C213

J50

TR214

TR213

C283

C248

R122

R144

C298

IC201

R102

C55

D13

IC101

C106

C31

R167

IC202

A13

C233

C286

TR217

TR216

R501

TR215

C292

R114

R50

TR111

TR6TR5

TR500

C241

TR208

R89

R101TR109

C501

D104

C231

C287

R26

A12

C3

C56

R58

C12

C104R106

R505

C551

R504

C407

A400

C405

L401R121

T3

TR12

IC5 IC10

IC203IC400

TUN

ER

KEY1

R123

CH2

CH3

CH1

LED

1

C258

TR1

R105

C297C257

C294

IC1

R10

D103

D105

H1

JS12

TR2

C249

C74

A4

L26

C51D

52

L25

C75

R64

D27

R88

D21

R84

R20

R19

D12 C23

C29

R57R56

R70 C54

R91

R82

C72

C73 C79

R83

D26

C68

L20

R86

R55

D25

C70

C69

R79

D23

R80

A3

L5D

6

R1

FUS1

R2

R31R30

C7

R6

C16 D8

R12

C78

R77

R17

C22

C21C30

R92

C61

C65

TR15

T2

D22

R75

C25

C24

R81

J41

TR203

C484

C496

J43

J44

JS10

J19

J92

C482

J18

J37

J122JS7

J128

J130

J25

J35

J93

J70

J140

J139

J138

J5 J102

J133

J17

J94

J16

R152

J26

J14

J81

J65

J1

J3

J71

J22

J109

D203

J132J134

J48J116

J53

J101

J144

J60

J100

J6

J20

J8 J68

J10

J117

J39

J28

J56

J12

J63

J120

R24J115

J113

J55

J32

J27

J46

J112

J38

J45

J54

J4 J124J125

J2

J106

J74

J31

J23

J136

J118

J135

J137

J119

J75

J126

J79 J82

J64

J57

J90

J141

J143

J21

J62

J34

J7

J9

J52

JS1

R188R189

R190

TASTO1

R14

C10

R156

J87

TR105

J77

R276

J108 J86J107

C575

J145

J84 J85J88

J76

R309J105

R181J96

J98J97J89

J91

C502

R147J104

J103

D108

R53

R16

TR207

R71

J66

R266

C67

C66

L23

C27

C59

J67

TR209

C235

R201

J40

L205

J61

C266

J95

JS502

J51D

200

A9

R240

J78

J47J49

J69J73

R145

J59

J148

C50

J146

X3

X5

X14

X6

A14

D50D53

C80

C81

C77

R425

R424R490

R491

JS490

JS450

JS451

J149 D109

C293

X8

C263

JP2

JP1

JP4

JP3

JP5

R619

TR60

0

C608

R620

CRT

A600

R624

R622

C609C6

10

D608

R621

D60

6

C601

R604

D60

7

R615

C602

C603

D60

3

R628

X10

R627

X12

R616

C600

R600

R629

C17

C6

JS13

R113

D102

R243

J127D

5

J131

X4

J121

C82

LA7955

LIVE AREA

F19

T2AH

00 01 02 03 04 05

MICROCONTROLLER

SDA

GND

11Vpp

GN

D

RL

GN

D

GN

D

+12V

GN

D

GN

D

GN

D

GND

230Vac

GN

D

2,5Vpp

45Vpp

1200Vpp

GIALLO

SCL

GN

D

+8V5

+12V

GN

D

VIDE

OIN

SEL

BIANCO

+5V

GN

D

ANA+

GND

+128V

GN

D

+5V STBY

LEFT

IN

GN

D

P+P-

GN

D

G F M A M G L A S O N D

ANA-

GND

GND

+8V5

+12V

GND

GND

+12V

+12V

GND

+12V

+12V

+148V

+5V

+5V

GND

GND

DSC

+5V

+5V

+5V STBY

+8V5

497.07B

GND

GN

D

GN

D

DE

GAU

SS

GN

D

GND

GN

D

GN

D

RGB

GN

D

G2

NVM

+12V

GN

D

AGC

JS6

GN

D

GN

D

5,6Vpp

+5V STBY

SCLSDA

3

1

1

3

123

4

1Vpp

60Vpp

27Vpp

150Vpp

2,5Vpp

+5V

12Vpp

120Vpp

1Vpp

40Vpp

8Vpp

497.

06B

RIGH

TIN RO

SSO

1,8Vpp

3Vpp

1Vpp

10Vpp

500Vpp

5Vpp

2,5Vpp

2,5Vpp

HEF4053

0,5Vpp

12Vpp

+5V

STBY

+5V

+12V

497.07B

F 19 SERVICE MANUAL - Reptips · F 19 SERVICE MANUAL THIS DOCUMENT IS A PROPERTY OF INDUSTRIE...

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Transcript of F 19 SERVICE MANUAL - Reptips · F 19 SERVICE MANUAL THIS DOCUMENT IS A PROPERTY OF INDUSTRIE...