Eye Diagram

Eye Diagram Measurements in ADS

Page 1

The use of Optimization in Signal Integrity Performance Centric High Speed Digital Design Flow

Brahim Bensalem, Intel CorporationLihua Wang, Agilent TechnologiesSanjeev Gupta, Agilent Technologies


Page 2

Agenda

• Channel Complexity and Gaps in Current Design Flow

• Advantage of End to End Eye Centric Design Flow

• Why an Eye Diagram ?

• Eye Diagram Measurements in ADS.

• Optimization of DDR2 Channel.

• Introduction to Batch mode simulation

• ADS near term roadmap for DDR designs


Page 3

Gap in Channel Design FlowConventional Flow Desired Flow

Design TargetEye Mask, TJ, SU/HD Margin, etc.

Chanel ParametersImpedance, Signal spacing,

total length, Rtt, et.

Design TargetEye Mask, TJ, SU/HD Margin, etc.

Chanel ParametersImpedance, Signal spacing,

total length, Rtt, et.

Solution Space ExplorationDOE, Corner Ana., Monte Carlo

TD and/or FD

Post Process/Convertto Design Target

Target Met?

End

Optimize Param. for Max. Eye Performance

No

YES


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Advantage of Eye Centric Design Flow

• Substantial gain in Channel Design Time (More than 3 weeks in our DDR2 case)

• Design is more robust since channel is optimized toward end to end channel performance

• Reduces risk of marginal design or opportunity loss due to over design


Page 5

Eye Diagram Functions In ADS

Why Eye Diagram is Important?


Page 6

Characterizing an Eye DiagramMost commonly used eye diagram measurements

Delay Effect

• Eye level 1 & level 0

• Eye rise/ fall time

• Eye opening

• Eye width

• Eye height

• Eye amplitude

• Peak to peak & RMS jitter

Most of the measurements are statistical in nature


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Slice and DiceEye Binning

Eye Diagram Binning Data


Page 8

Histogram PlotsHistogram can be created for any portion of eye diagram

Histogram across amplitude axis provide distribution around level one and zero

Histogram across timing axis provide peak to peak jitter


Page 9

Eye DelayWhy delay calculation is required

Calculated Delay

• Delay calculation is required for automated eye parameter measurements

• Binning the eye diagram makes this calculation easy


Page 10

Automated Eye Crossing Detection

• Mean value of horizontal histogram provide crossing time value

• Mean value of amplitude histogram provides crossing amplitude value


Page 11

Measurements of Eye Level One/Zero

0% 40% 60%Measurement boundaries

100%

Eye

Ampli

tude

3 σ

3 σEye

Heigh

t

1 σ

1 σ Eye Amplitude = Level One – Level ZeroEye Height = (Eye level one- 3σ)- (Eye level zero+3σ)Eye S/N= (Eye level one-Eye level zero)

1σ level one+1σ level zero


Page 12

Eye Measurements in ADS2008


Page 13

Eye Measurements in ADS2009 Fast and Easy

Eye Probe (new addition to ADS2009) How to select eye measurements

Any number of Eye probes could be used in a design


Page 14

DDR2 Simulation in ADS

Memory Module & Eye Probe

IBIS drivers and triggers


Page 15

Memory Bus Simulation using ADS

• X8 Un-buffered Memory Down Channel• 8 SDRAM Devices per signal• Signal Group : CMD/ADD


Page 16

Memory Performance at DRAM

How to improve channel performance?


Page 17

• Introduction to Optimization• Time domain Optimization and why it is difficult• Optimization of DDR2 Channel


Page 18

Optimization in ADSModify your Designs Automatically to Achieve Required Performance

Why Optimization?• Parameter sweep often doesn’t lead to an optimized designs• Parameter sweeps requires usually large number of simulation when

number of variables are large

The use of Optimizers in a design process• Automatically change design parameter to meet design goals• Categorized by their error function formulation• Coarse design stages: Random optimizer, Random Minimax optimizer and Simulated

Annealing optimizer • Fine design stages: Gradient optimizer, Gradient Minimax optimizer, Quasi-Newton optimizer

and Minimax optimizer


Page 19

Issues with Time Domain Optimization

– Time domain optimization goals are often difficult to define

– Changes in any reactive component during optimization will effect channel delay and optimization goals may no longer be applicable


Page 20

DDR2 Channel Design

X8 Un-buffered Memory Down Channel

8 SDRAM Devices

Signal Group to Optimize: CMD/ADD

Design Parameters:

Leadin Escape W leadin S Breakout Trace Spacing

Rtt L Brkout

3-5 mils 0.3-0.8in20-100 Ω8-15 mils3.5-5.5 mils0.3-0.8 in2-4 in


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Eye Diagram Optimization

• ADS2009 makes it easy to perform eye optimization

• Any eye measurement could be used as an optimization expression

• Any number of eye probes, measurements & parameters could be optimized at the same time


Page 22

Optimized Eye Diagram Performance

Eye Diagram after Channel Optimization

Optimizer Type : RandomNumber of iteration : 20Optimization time : 25 minutes


Page 23

Performance Comparison

Before After


Page 24

Sweeping Corner Case

Batch simulation is used to sweep corner cases


Page 25

Batch Mode Simulation in ADSIntroduced in ADS2008 Update 2

StringListStringList1String[1]=

String List

DataFileListDataFileList1FileName[1]=

DataFileList

BatchSimControllerBatchSim1

SweepModule=SweepModuleArgument=UseSweepModule=Analysis[1]=UseSweepPlan=Var= Start=1.0 Stop=10.0 Step=1.0 Lin=

BATCH SIMULATION

NetlistIncludeListNetlistIncludeList1NetlistName[1]=

Netlist Include List

The new palette will have four components:•the batch simulation controller•the DataFileList container•the StringList container•the NetlistIncludeList container

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Page 26

Batch Simulation Controller Dialog

•Eliminates requirement to write complex manual scripts•Uses Sweep Plan or Sweep Module•No limits on number of parameter sweep•Allow sweeping of Touchstone files, connector models, netlist etc.•Allow parameters to be defined in .csv format•Enable complex measurements such as eye diagram under parameter sweep mode.

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Simulation Results

Here only Rx corner cases was swept.

Batch mode allows simulation of any combination of Tx/Rx corner cases and IBIS models

Time Domain Optimization Discussed

• Works well even if the flight time delay is changed due to changein the reactive element value.

• Automatically calculates delay required for eye positioning

• Automatically detects eye crossing point and 40-60% region

• Optimize eye diagram performance

• Corner case simulation performance was determined

Any eye diagram parameter such as eye opening factor, eye height, peak to peak jitter, rise time … can be used as an optimization goal.

Will make your design work without running 1000’s of parameter sweep


Page 28


Page 29

DDR Mesurements

Near Term RoadmapNear Term Roadmap


Page 30


Page 31

Post ADS2009 Update 1: Memory Compliance Toolkits

vdd

DRAM_1

vdd

DRAM_0

vdd

vdd

aw

DQS_DRAM_1N

DQS_DRAM_1Pvdd

DQS_DRAM_0N

DQS_DRAM_0Pvdd

vdd

ML1CTL_Cdq_TL2_2

Layer=1W=W milLength=2.9 mmSubst="DIMMSUB"

ML1CTL_Cdq_TL2_1


RR1R=R_dq Ohm

ML1CTL_Cdq_TL1


ML1CTL_Cdq_TL0

Layer=1W=W milLength=3 mmSubst="DIMMSUB"

IBIS_IOIBIS26

UsePkg=yesDataTypeSelector=TypSetAllData=yesModelName="DQ_FULL_800"PinName="K8"ComponentName="MT47H32M16BN_CLP_3_neg25"IbisFile="u37y_800.ibs"

DigO

IO

PD

PU

E

TPCGC

IBIS_IOIBIS11

UsePkg=yesDataTypeSelector=TypSetAllData=yesModelName="DQ_FULL_800"PinName="K8"ComponentName="MT47H32M16BN_CLP_3_neg25"IbisFile="u37y_800.ibs"

DigO

IO

PD

PU

E

TPC

GC

VARVAR3W=5.0

EqnVar

VtPRBSVPRBS4

Delay=0 psecFallTime=10 psecRiseTime=10 psecBitRate=0.75 GHzEdgeShape=Linear TransitionVhigh=2 VVlow=0.0 VRegisterLength=17

- -

++

VtPRBSVPRBS3

Delay=0 psecFallTime=10 psecRiseTime=10 psecBitRate=0.75 GHzEdgeShape=Linear TransitionVhigh=2 VVlow=0.0 VRegisterLength=17

- -

++

ML1CTL_Cdq_TL0A1

Layer=1W=W milLength=3 inSubst="DIMMSUB"

V_DCSRC18Vdc=VDD/2

RR6R=R_Ref Ohm

IBIS_IOIBIS21

UsePkg=yesDataTypeSelector=TypSetAllData=yesModelName="SSTL18_I"PinName="12"ComponentName="VIRTEX-5_FF1136"IbisFile="v irtex5.ibs"

Di gO

IO

PD

PU

E

TPC

GC

IBIS_IOIBIS17

UsePkg=yesDataTypeSelector=TypSetAllData=yesModelName="SSTL18_I"PinName="12"ComponentName="VIRTEX-5_FF1136"IbisFile="v irtex5.ibs"

Di gO

IO

PD

PU

E

TPC

GC

IBIS_DIOIBIS8

UsePkg=yesDataTypeSelector=TypSetAllData=yesModelName="DQ_FULL_800"PinName="E7"ComponentName="MT47H32M16BN_CLP_3_neg25"IbisFile="u37y_800.ibs"

DigO

IO_I

PU

PD E

T

GC

PC

IO_NI

ML2CTL_Cdqs_TL0

ReuseRLGC=noRLGC_File=Layer=1S=6 milW=W milLength=3 mmSubst="DIMMSUB"

ML2CTL_Cdqs_TL1

ReuseRLGC=noRLGC_File=Layer=1S=6 milW=W milLength=3 mmSubst="DIMMSUB"

RR8R=R_dqs Ohm

RR7R=R_dqs Ohm

IBIS_DIOIBIS27

UsePkg=yesDataTypeSelector=TypSetAllData=yesModelName="DQ_FULL_800"PinName="E7"ComponentName="MT47H32M16BN_CLP_3_neg25"IbisFile="u37y_800.ibs"

DigO

IO_I

PU

PD

E

T

GCPC

IO_NI

ML2CTL_Cdqs_TL2_1

ReuseRLGC=noRLGC_File=Layer=1S=6.0 milW=W milLength=2.9 mmSubst="DIMMSUB"

ML2CTL_Cdqs_TL2_2

ReuseRLGC=noRLGC_File=Layer=1S=6.0 milW=W milLength=2.9 mmSubst="DIMMSUB"

VtPRBSVPRBS5

Delay=0 psecFallTime=10 psecRiseTime=10 psecBitRate=0.75 GHzEdgeShape=Linear TransitionVhigh=2 VVlow=0.0 VBitSequence="10101010"

- -

++

ML2CTL_Cdqs_TL0A1

ReuseRLGC=noRLGC_File=Layer=1S=6.0 milW=W milLength=3 inSubst="DIMMSUB"

IBIS_DIOIBIS24

UsePkg=yesDataTypeSelector=TypSetAllData=yesModelName="SSTL18_I"PinName="20P"ComponentName="VIRTEX-5_FF1136"IbisFile="v irtex5.ibs"

Di gO

IO_ I

PU

PD E

T

GCPC

IO_NI


Page 32

Memory Compliance Toolkits-Features

Comprehensive JEDEC measurement support


Page 33


Easy installation (ADS design kit format) and frequent updates


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• Open-source memory measurements (C/C++)• Easy to add new user-defined capability• Automatic compilation of user-defined measurements for streamlined

deployment• Built-in, free compiler requires no additional software for user-defined

functionality


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2 4 6 8 10 12 14 16 18 200 22

1.95

2.00

2.05

2.10

1.90

2.15

Index

Sle

wR

Set

upFa

ll

• Comprehensive reporting


Page 36

Conclusion

• Time Domain optimization of eye diagram in ADS provides a powerful methodology to improve high speed memory design and to extract even fraction of the psec of timing margin buried in interconnects

• Substantial reduction in time needed to design and optimize of memory platform design is made (from weeks to hours)

• Guarantee maximal channel robustness

• Minimize Over/Under design risks

Opportunities for future developmentNeed to demonstrate IBIS model optimization such as driver strength, ODT etc.

Eye Diagram

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