7222019 Extra Project hhhh

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2008

Pipelined MIPS CPU

Synthesis and On-Die

Representation

ECE472Joseph Crop

Stewart Myers

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2

983124983137983138983148983141 983151983142 983107983151983150983156983141983150983156983155

Introduction 3

Steps Taken and Simulation 3

Pitfalls 8

Simulated Delay 9

APPENDIX A ndash Synthesized Pipelined MIPS CPU 11

APPENDIX B ndash Pipelined MIPS CPU On-Die Representation 12

APPENDIX C ndash Encounter Configuration File 13

APPENDIX D ndash Synthesis Configuration Code 15

APPENDIX E ndash Pipelined MIPS CPU Verilog Code 16

7222019 Extra Project hhhh

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3

983113983150983156983154983151983140983157983139983156983145983151983150

This project involved the creation of an on-die representation of a pipelined MIPS

CPU from code acquisition to synthesis to final die layout Although we have had

experience with ModelSIM and writing Verilog from other projects during this term

many of the tools required to complete the synthesis and on-die representation were

completely new to us We will explain all the steps taken to reach the final

representation how we simulated our pipelined CPU the pitfalls we encountered and

how we overcame them and we will explain how we simulated the delay and what those

delay values were

983123983156983141983152983155 983124983137983147983141983150 983137983150983140 983123983145983149983157983148983137983156983145983151983150

1 If you havenrsquot already create a test bench for your verilog code

2 Place all of your v files in the verilog_input folder

3 Modify the dc_syn file inside of the synthesis folder to include all of your v files

read_verilog verilog_inputfile1v

read_verilog verilog_inputfile2v

4 Change both of the current_ design parameter to contain the name of your test

bench module Also make sure your test bench module has a clock input

current_design mips_pipeline_testbench

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4

5 Create a clock in the design change the create_clock command to have the

get_ports parameter to point you your clock register Ours was named ldquoclkrdquo

create_clock clk -name cpu_clock -period 5

6 Change the names of the output files to something useful

write -format verilog -hierarchy -output

synthesized_verilogpipeline_testbenchgatev

write_sdc synthesized_verilogpipeline_testbenchsdc

7 Open a terminal navigate to the synthesis folder and execute the following

command This starts the Design Vision program and creates gate-level

synthesized verilog If you donrsquot have your current design listed as your test

bench thing will go wring and you may or may not get errors

design_vision-xg -f dc_syn

8 After the Design Vision program loads choose Schematic -gt New Design

Schematic View If not already selected make sure your test bench is loaded in

the drop-down box at the top of the screen If you didnrsquot set the current_design

parameter correctly your test bench will load as a very small design instead of

your whole cpu

9 After ogling your cool design close Design Vision

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5

10 Make sure your gave-level verilog was synthesized correctly by running is in

modelsim and verifying identical operation to your original code It should be

located in

synthesized_verilog[name]gatev

11 Three reports are generated from the synthesis an area report clock report and a

delay report they are placed in the synthesisreports folder Verify the clock was

asserted correctly to you design by opening the clock report you should see

something like this

Clock Period Waveform Attrs Sources

--------------------------------------------------------------------------------

clk 500 0 25 clk

--------------------------------------------------------------------------------

If the clock report looks correct open the delay report If itrsquos wrong your

test bench or synthesis configuration file are incorrect The delay report

will tell you if your selected clock period will work for the gate simulated

gate delays from Design Vision It should look something like this

Point Incr Path

-------------------------------------------------------------------------- ---------------

clock clk (rise edge) 000 000clock network delay (ideal) 000 000

dutWB_MemtoReg_regCK (DFFTRX1MTH) 000 000 r

data required time 491

-------------------------------------------------------------------------- ---------------

data required time 491

data arrival time -490

-------------------------------------------------------------------------- ---------------slack (MET) 001

7222019 Extra Project hhhh

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6

12 Change the directory in your shell to the encounter folder

13 Edit encounterconf in the encounter folder

1

Make sure your lib and lef are pointed to correctly

set rda_Input(ui_timelib) cell_lib_filesscmetro_cms9flp-

lvt_tt_1p2v_25clib

set rda_Input(ui_leffile) cell_lib_fileslefcms9flp_8lm_2thick_techlef

cell_lib_fileslefcms9flplvt_m_macroslef

2 Make sure your test bench is your top cell

set rda_Input(ui_topcell) mips_pipeline_testbench

3 Make sure your timing and netlist files are pointed to correctly

set rda_Input(ui_netlist) synthesized_verilog[name]gatev

set rda_Input(ui_timingcon_file) synthesized_verilog[name]sdc

14 Run Cadence encounter We found it in

ldquousrlocalappscadenceSOCcurrentbinencounterrdquo

15 Navigate to Design -gt Design Import -gt Load and select your ldquoencounterconfrdquo

file and click OK You should see a black square with gray horizontal lines on the

screen

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 715

7

16 Add power rings by navigating to Power -gt Power Planning -gt Add Rings Type

VSS VDD into the Net(s) area specify metal layers and ring width (We used

TopBottom Metal5 and LeftRight Metal6) and select center in channel click

ldquoupdaterdquo to see what values it is actually going to use Click ldquoOKrdquo

17 Add horizontal power buses by navigating to Route -gt Special Route and clicking

ldquoOKrdquo (the default values are usually acceptable)

18 Navigate to Place -gt Standard Cells and click ldquoOKrdquo this will place all of the

standard blocks This step can take a while so be patient To make the cells show

up by clicking on the Physical View button in the top right corner of the screen

19 Now go to Edit -gt Pin Editor and click on your clock(s) in the list of pins and

change USE to CLOCK

20 Add filler blocks to connect the power rails between the standard cells with Place

-gt Physical Cells -gt Add Filler and click on ldquoselectrdquo Highlight all fillers and click

add Then click ldquoCloserdquo and then click ldquoOKrdquo This will add filler blocks fitting

the largest block it can into each hole

21 To route the blocks run Route -gt Nanoroute -gt Route with the default options

Sometimes unnecessarily ugly routes will be taken manually fix these to ensure a

clean signal path if you would like

22 Now run Timing -gt Optimize with ldquoPost-Routerdquo selected

7222019 Extra Project hhhh

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9

CPU and the current_design parameter serves as the entry point overview file of that

hierarchy We ran Design Vision many many times before discovering this error

After synthesizing our CPU we ran into a third major pitfall when trying to time

the synthesized CPU in Design Vision We began synthesis by using the pipelined

testbench which contained a clock but did not have a clock as input When using the

testbench Design Vision said we had no clock and we couldnrsquot time our CPU We had

to have an output Y and input A then set them equal to each other on the posedge of the

clock along with running our MIPS pipeline module and with no reset signal For

whatever reason these changes added a clock to our synthesis and we could time the

pipelined CPU

After synthesizing we were able to move on to the on-die representation phase

where we encountered only minor easily remedied issues such as forgetting to check or

uncheck a dialog box entry etc All these issues were quickly taking care of by re-

reading the online tutorial

983123983145983149983157983148983137983156983141983140 983108983141983148983137983161

Following is the report created by Design Vision on simulated delay

Report timing

-path full-delay max-max_paths 1

Design mips_pipeline_testbenchVersion X-200509-SP2Date Fri Dec 12 142903 2008

A fanout number of 1000 was used for high fanout net computations

Operating Conditions tt_1p2v_25c Library scmetro_cms9flp-lvt_tt_1p2v_25cWire Load Model Mode top

Startpoint dutWB_MemtoReg_reg(rising edge-triggered flip-flop clocked by clk)

Endpoint dutMEM_Zero_reg(rising edge-triggered flip-flop clocked by clk)

Path Group clk

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10

Path Type max

Point Incr Path--------------------------------------------------------------------------clock clk (rise edge) 000 000clock network delay (ideal) 000 000dutWB_MemtoReg_regCK (DFFTRX1MTH) 000 000 rdutWB_MemtoReg_regQ (DFFTRX1MTH) 017 017 f

U335Y (BUFX2MTH) 016 033 fU970Y (AO22X2MTH) 017 049 fU258Y (BUFX4MTH) 008 057 fU282Y (AOI22X1MTH) 007 064 rU278Y (OAI2BB1X2MTH) 004 067 fU268Y (AO22X2MTH) 015 082 fdutEX_ALUadd_145U1_2CO (ADDFX2MTH) 023 105 fdutEX_ALUadd_145U1_3CO (ADDFX2MTH) 013 118 fdutEX_ALUadd_145U1_4CO (ADDFX2MTH) 013 131 fdutEX_ALUadd_145U1_5CO (ADDFX2MTH) 013 143 fdutEX_ALUadd_145U1_6CO (ADDFX2MTH) 013 156 fdutEX_ALUadd_145U1_7CO (ADDFX2MTH) 013 168 fdutEX_ALUadd_145U1_8CO (ADDFX2MTH) 013 181 fdutEX_ALUadd_145U1_9CO (ADDFX2MTH) 013 194 fdutEX_ALUadd_145U1_10CO (ADDFX2MTH) 013 206 fdutEX_ALUadd_145U1_11CO (ADDFX2MTH) 013 219 fdutEX_ALUadd_145U1_12CO (ADDFX2MTH) 013 232 f

dutEX_ALUadd_145U1_13CO (ADDFX2MTH) 013 244 fdutEX_ALUadd_145U1_14CO (ADDFX2MTH) 013 257 fdutEX_ALUadd_145U1_15CO (ADDFX2MTH) 013 270 fdutEX_ALUadd_145U1_16CO (ADDFX2MTH) 013 282 fdutEX_ALUadd_145U1_17CO (ADDFX2MTH) 013 295 fdutEX_ALUadd_145U1_18CO (ADDFX2MTH) 013 308 fdutEX_ALUadd_145U1_19CO (ADDFX2MTH) 013 320 fdutEX_ALUadd_145U1_20CO (ADDFX2MTH) 013 333 fdutEX_ALUadd_145U1_21CO (ADDFX2MTH) 013 346 fdutEX_ALUadd_145U1_22CO (ADDFX2MTH) 013 358 fdutEX_ALUadd_145U1_23CO (ADDFX2MTH) 013 371 fdutEX_ALUadd_145U1_24CO (ADDFX2MTH) 013 384 fdutEX_ALUadd_145U1_25CO (ADDFX2MTH) 013 396 fdutEX_ALUadd_145U1_26CO (ADDFX2MTH) 013 409 fdutEX_ALUadd_145U1_27CO (ADDFX2MTH) 014 423 fU272Y (NAND2X1MTH) 004 427 rU267Y (NAND3X2MTH) 005 432 f

dutEX_ALUadd_145U1_29CO (ADDFX2MTH) 012 444 fdutEX_ALUadd_145U1_30CO (ADDFX2MTH) 012 457 fdutEX_ALUadd_145U1_31Y (XOR3X1MTH) 009 466 fU251Y (NAND2X1MTH) 004 469 rU252Y (OAI2B11X2MTH) 007 476 fU269Y (NOR2XLMTH) 006 482 rU259Y (NAND2XLMTH) 004 486 fU289Y (NOR2X1MTH) 004 490 rdutMEM_Zero_regD (DFFTRX1MTH) 000 490 rdata arrival time 490

clock clk (rise edge) 500 500clock network delay (ideal) 000 500dutMEM_Zero_regCK (DFFTRX1MTH) 000 500 rlibrary setup time -009 491data required time 491--------------------------------------------------------------------------

data required time 491data arrival time -490--------------------------------------------------------------------------slack (MET) 001

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11

983105983120983120983109983118983108983113983128 983105 991251 983123983161983150983156983144983141983155983145983162983141983140 983111983137983156983141 983116983141983158983141983148 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125

7222019 Extra Project hhhh

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12

983105983120983120983109983118983108983113983128 983106 991251 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125 983119983150983085983108983145983141 983122983141983152983154983141983155983141983150983156983137983156983145983151983150

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13

983105983120983120983109983118983108983113983128 983107 991251 983109983150983139983151983157983150983156983141983154 983107983151983150983142983145983143983157983154983137983156983145983151983150 983110983145983148983141

SOC Encounter Input configuration file

global rda_Input

set rda_Input(ui_netlist) synthesized_verilogpipeline_testbenchgatev

set rda_Input(ui_timingcon_file) synthesized_verilogpipeline_testbenchsdc

set rda_Input(ui_topcell) mips_pipeline_testbench

set rda_Input(ui_netlisttype) Verilog

set rda_Input(ui_ilmlist)

set rda_Input(ui_settop) 1

set rda_Input(ui_celllib)

set rda_Input(ui_iolib)

set rda_Input(ui_areaiolib)

set rda_Input(ui_blklib)

set rda_Input(ui_kboxlib)

set rda_Input(ui_timelib) cell_lib_filesscmetro_cms9flp-lvt_tt_1p2v_25clib

set rda_Input(ui_smodDef)

set rda_Input(ui_smodData)

set rda_Input(ui_dpath)

set rda_Input(ui_tech_file)

set rda_Input(ui_buf_footprint) BUFX2MTH

set rda_Input(ui_delay_footprint) BUFX2MTH

set rda_Input(ui_inv_footprint) INVX1MTH

set rda_Input(ui_leffile) cell_lib_fileslefcms9flp_8lm_2thick_techlef cell_lib_fileslefcms9flplvt_m_macroslef

set rda_Input(ui_core_cntl) aspect

set rda_Input(ui_aspect_ratio) 10

set rda_Input(ui_core_util) 07

set rda_Input(ui_core_height)

set rda_Input(ui_core_width)

set rda_Input(ui_core_to_left) 30

set rda_Input(ui_core_to_right) 30

set rda_Input(ui_core_to_top) 30set rda_Input(ui_core_to_bottom) 30

set rda_Input(ui_max_io_height) 0

set rda_Input(ui_row_height)

set rda_Input(ui_isHorTrackHalfPitch) 0

set rda_Input(ui_isVerTrackHalfPitch) 1

set rda_Input(ui_ioOri) R180

set rda_Input(ui_isOrigCenter) 0

set rda_Input(ui_exc_net)

set rda_Input(ui_delay_limit) 1000

set rda_Input(ui_net_delay) 10000ps

set rda_Input(ui_net_load) 05pf

set rda_Input(ui_in_tran_delay) 1200ps

set rda_Input(ui_captbl_file)

set rda_Input(ui_cap_scale) 10

set rda_Input(ui_xcap_scale) 10

set rda_Input(ui_res_scale) 10

set rda_Input(ui_shr_scale) 10set rda_Input(ui_time_unit) none

set rda_Input(ui_cap_unit)

set rda_Input(ui_sigstormlib)

set rda_Input(ui_cdb_file)

set rda_Input(ui_echo_file)

set rda_Input(ui_qxtech_file)

set rda_Input(ui_qxlib_file)

set rda_Input(ui_qxconf_file)

set rda_Input(ui_pwrnet) VDD

set rda_Input(ui_gndnet) VSS

set rda_Input(flip_first) 1

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14

set rda_Input(double_back) 1

set rda_Input(assign_buffer) 0

set rda_Input(ui_pg_connections) [list

PINVDD

PINVSS

]

set rda_Input(PINVDD) VDD

set rda_Input(PINVSS) VSS

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983105983120983120983109983118983108983113983128 983108 991251 983123983161983150983156983144983141983155983145983155 983107983151983150983142983145983143983157983154983137983156983145983151983150 983107983151983140983141

synopsys synthesis script

set hdlin_auto_save_templates true

set hdlin_check_no_latch true

set hdlin_warn_sens_list true

define_name_rules MYrules -map [ _ ] _

read_verilog verilog_inputoutv

current_design mips_pipeline_testbench

link

constraints are below

erase all attributes and constrains from the current design

reset_design

set wire loading mode to top

set_wire_load_mode top

Create clock with 5ns period

create_clock clk -name clk -period 5

change_names -rules MYrules -hierarchy

Compile with completely disolved design

compile -ungroup_all

Make sure we are at the top level

set current_design mips_pipeline_testbench

Generate area and constraints reports on the optimized design

report_area gt reportsarearpt

Generate timing report for worst case path

report_timing gt reportsdelayrpt

report_clock gt reportsclockrpt

Save the compiled design

write -format verilog -hierarchy -output synthesized_verilogpipeline_testbenchgatev

write_sdc synthesized_verilogpipeline_testbenchsdc

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2

983124983137983138983148983141 983151983142 983107983151983150983156983141983150983156983155

Introduction 3

Steps Taken and Simulation 3

Pitfalls 8

Simulated Delay 9

APPENDIX A ndash Synthesized Pipelined MIPS CPU 11

APPENDIX B ndash Pipelined MIPS CPU On-Die Representation 12

APPENDIX C ndash Encounter Configuration File 13

APPENDIX D ndash Synthesis Configuration Code 15

APPENDIX E ndash Pipelined MIPS CPU Verilog Code 16

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3

983113983150983156983154983151983140983157983139983156983145983151983150

This project involved the creation of an on-die representation of a pipelined MIPS

CPU from code acquisition to synthesis to final die layout Although we have had

experience with ModelSIM and writing Verilog from other projects during this term

many of the tools required to complete the synthesis and on-die representation were

completely new to us We will explain all the steps taken to reach the final

representation how we simulated our pipelined CPU the pitfalls we encountered and

how we overcame them and we will explain how we simulated the delay and what those

delay values were

983123983156983141983152983155 983124983137983147983141983150 983137983150983140 983123983145983149983157983148983137983156983145983151983150

1 If you havenrsquot already create a test bench for your verilog code

2 Place all of your v files in the verilog_input folder

3 Modify the dc_syn file inside of the synthesis folder to include all of your v files

read_verilog verilog_inputfile1v

read_verilog verilog_inputfile2v

4 Change both of the current_ design parameter to contain the name of your test

bench module Also make sure your test bench module has a clock input

current_design mips_pipeline_testbench

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4

5 Create a clock in the design change the create_clock command to have the

get_ports parameter to point you your clock register Ours was named ldquoclkrdquo

create_clock clk -name cpu_clock -period 5

6 Change the names of the output files to something useful

write -format verilog -hierarchy -output

synthesized_verilogpipeline_testbenchgatev

write_sdc synthesized_verilogpipeline_testbenchsdc

7 Open a terminal navigate to the synthesis folder and execute the following

command This starts the Design Vision program and creates gate-level

synthesized verilog If you donrsquot have your current design listed as your test

bench thing will go wring and you may or may not get errors

design_vision-xg -f dc_syn

8 After the Design Vision program loads choose Schematic -gt New Design

Schematic View If not already selected make sure your test bench is loaded in

the drop-down box at the top of the screen If you didnrsquot set the current_design

parameter correctly your test bench will load as a very small design instead of

your whole cpu

9 After ogling your cool design close Design Vision

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5

10 Make sure your gave-level verilog was synthesized correctly by running is in

modelsim and verifying identical operation to your original code It should be

located in

synthesized_verilog[name]gatev

11 Three reports are generated from the synthesis an area report clock report and a

delay report they are placed in the synthesisreports folder Verify the clock was

asserted correctly to you design by opening the clock report you should see

something like this

Clock Period Waveform Attrs Sources

--------------------------------------------------------------------------------

clk 500 0 25 clk

--------------------------------------------------------------------------------

If the clock report looks correct open the delay report If itrsquos wrong your

test bench or synthesis configuration file are incorrect The delay report

will tell you if your selected clock period will work for the gate simulated

gate delays from Design Vision It should look something like this

Point Incr Path

-------------------------------------------------------------------------- ---------------

clock clk (rise edge) 000 000clock network delay (ideal) 000 000

dutWB_MemtoReg_regCK (DFFTRX1MTH) 000 000 r

data required time 491

-------------------------------------------------------------------------- ---------------

data required time 491

data arrival time -490

-------------------------------------------------------------------------- ---------------slack (MET) 001

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6

12 Change the directory in your shell to the encounter folder

13 Edit encounterconf in the encounter folder

1

Make sure your lib and lef are pointed to correctly

set rda_Input(ui_timelib) cell_lib_filesscmetro_cms9flp-

lvt_tt_1p2v_25clib

set rda_Input(ui_leffile) cell_lib_fileslefcms9flp_8lm_2thick_techlef

cell_lib_fileslefcms9flplvt_m_macroslef

2 Make sure your test bench is your top cell

set rda_Input(ui_topcell) mips_pipeline_testbench

3 Make sure your timing and netlist files are pointed to correctly

set rda_Input(ui_netlist) synthesized_verilog[name]gatev

set rda_Input(ui_timingcon_file) synthesized_verilog[name]sdc

14 Run Cadence encounter We found it in

ldquousrlocalappscadenceSOCcurrentbinencounterrdquo

15 Navigate to Design -gt Design Import -gt Load and select your ldquoencounterconfrdquo

file and click OK You should see a black square with gray horizontal lines on the

screen

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 715

7

16 Add power rings by navigating to Power -gt Power Planning -gt Add Rings Type

VSS VDD into the Net(s) area specify metal layers and ring width (We used

TopBottom Metal5 and LeftRight Metal6) and select center in channel click

ldquoupdaterdquo to see what values it is actually going to use Click ldquoOKrdquo

17 Add horizontal power buses by navigating to Route -gt Special Route and clicking

ldquoOKrdquo (the default values are usually acceptable)

18 Navigate to Place -gt Standard Cells and click ldquoOKrdquo this will place all of the

standard blocks This step can take a while so be patient To make the cells show

up by clicking on the Physical View button in the top right corner of the screen

19 Now go to Edit -gt Pin Editor and click on your clock(s) in the list of pins and

change USE to CLOCK

20 Add filler blocks to connect the power rails between the standard cells with Place

-gt Physical Cells -gt Add Filler and click on ldquoselectrdquo Highlight all fillers and click

add Then click ldquoCloserdquo and then click ldquoOKrdquo This will add filler blocks fitting

the largest block it can into each hole

21 To route the blocks run Route -gt Nanoroute -gt Route with the default options

Sometimes unnecessarily ugly routes will be taken manually fix these to ensure a

clean signal path if you would like

22 Now run Timing -gt Optimize with ldquoPost-Routerdquo selected

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 815

7222019 Extra Project hhhh

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9

CPU and the current_design parameter serves as the entry point overview file of that

hierarchy We ran Design Vision many many times before discovering this error

After synthesizing our CPU we ran into a third major pitfall when trying to time

the synthesized CPU in Design Vision We began synthesis by using the pipelined

testbench which contained a clock but did not have a clock as input When using the

testbench Design Vision said we had no clock and we couldnrsquot time our CPU We had

to have an output Y and input A then set them equal to each other on the posedge of the

clock along with running our MIPS pipeline module and with no reset signal For

whatever reason these changes added a clock to our synthesis and we could time the

pipelined CPU

After synthesizing we were able to move on to the on-die representation phase

where we encountered only minor easily remedied issues such as forgetting to check or

uncheck a dialog box entry etc All these issues were quickly taking care of by re-

reading the online tutorial

983123983145983149983157983148983137983156983141983140 983108983141983148983137983161

Following is the report created by Design Vision on simulated delay

Report timing

-path full-delay max-max_paths 1

Design mips_pipeline_testbenchVersion X-200509-SP2Date Fri Dec 12 142903 2008

A fanout number of 1000 was used for high fanout net computations

Operating Conditions tt_1p2v_25c Library scmetro_cms9flp-lvt_tt_1p2v_25cWire Load Model Mode top

Startpoint dutWB_MemtoReg_reg(rising edge-triggered flip-flop clocked by clk)

Endpoint dutMEM_Zero_reg(rising edge-triggered flip-flop clocked by clk)

Path Group clk

7222019 Extra Project hhhh

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10

Path Type max

Point Incr Path--------------------------------------------------------------------------clock clk (rise edge) 000 000clock network delay (ideal) 000 000dutWB_MemtoReg_regCK (DFFTRX1MTH) 000 000 rdutWB_MemtoReg_regQ (DFFTRX1MTH) 017 017 f

U335Y (BUFX2MTH) 016 033 fU970Y (AO22X2MTH) 017 049 fU258Y (BUFX4MTH) 008 057 fU282Y (AOI22X1MTH) 007 064 rU278Y (OAI2BB1X2MTH) 004 067 fU268Y (AO22X2MTH) 015 082 fdutEX_ALUadd_145U1_2CO (ADDFX2MTH) 023 105 fdutEX_ALUadd_145U1_3CO (ADDFX2MTH) 013 118 fdutEX_ALUadd_145U1_4CO (ADDFX2MTH) 013 131 fdutEX_ALUadd_145U1_5CO (ADDFX2MTH) 013 143 fdutEX_ALUadd_145U1_6CO (ADDFX2MTH) 013 156 fdutEX_ALUadd_145U1_7CO (ADDFX2MTH) 013 168 fdutEX_ALUadd_145U1_8CO (ADDFX2MTH) 013 181 fdutEX_ALUadd_145U1_9CO (ADDFX2MTH) 013 194 fdutEX_ALUadd_145U1_10CO (ADDFX2MTH) 013 206 fdutEX_ALUadd_145U1_11CO (ADDFX2MTH) 013 219 fdutEX_ALUadd_145U1_12CO (ADDFX2MTH) 013 232 f

dutEX_ALUadd_145U1_13CO (ADDFX2MTH) 013 244 fdutEX_ALUadd_145U1_14CO (ADDFX2MTH) 013 257 fdutEX_ALUadd_145U1_15CO (ADDFX2MTH) 013 270 fdutEX_ALUadd_145U1_16CO (ADDFX2MTH) 013 282 fdutEX_ALUadd_145U1_17CO (ADDFX2MTH) 013 295 fdutEX_ALUadd_145U1_18CO (ADDFX2MTH) 013 308 fdutEX_ALUadd_145U1_19CO (ADDFX2MTH) 013 320 fdutEX_ALUadd_145U1_20CO (ADDFX2MTH) 013 333 fdutEX_ALUadd_145U1_21CO (ADDFX2MTH) 013 346 fdutEX_ALUadd_145U1_22CO (ADDFX2MTH) 013 358 fdutEX_ALUadd_145U1_23CO (ADDFX2MTH) 013 371 fdutEX_ALUadd_145U1_24CO (ADDFX2MTH) 013 384 fdutEX_ALUadd_145U1_25CO (ADDFX2MTH) 013 396 fdutEX_ALUadd_145U1_26CO (ADDFX2MTH) 013 409 fdutEX_ALUadd_145U1_27CO (ADDFX2MTH) 014 423 fU272Y (NAND2X1MTH) 004 427 rU267Y (NAND3X2MTH) 005 432 f

dutEX_ALUadd_145U1_29CO (ADDFX2MTH) 012 444 fdutEX_ALUadd_145U1_30CO (ADDFX2MTH) 012 457 fdutEX_ALUadd_145U1_31Y (XOR3X1MTH) 009 466 fU251Y (NAND2X1MTH) 004 469 rU252Y (OAI2B11X2MTH) 007 476 fU269Y (NOR2XLMTH) 006 482 rU259Y (NAND2XLMTH) 004 486 fU289Y (NOR2X1MTH) 004 490 rdutMEM_Zero_regD (DFFTRX1MTH) 000 490 rdata arrival time 490

clock clk (rise edge) 500 500clock network delay (ideal) 000 500dutMEM_Zero_regCK (DFFTRX1MTH) 000 500 rlibrary setup time -009 491data required time 491--------------------------------------------------------------------------

data required time 491data arrival time -490--------------------------------------------------------------------------slack (MET) 001

7222019 Extra Project hhhh

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11

983105983120983120983109983118983108983113983128 983105 991251 983123983161983150983156983144983141983155983145983162983141983140 983111983137983156983141 983116983141983158983141983148 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125

7222019 Extra Project hhhh

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12

983105983120983120983109983118983108983113983128 983106 991251 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125 983119983150983085983108983145983141 983122983141983152983154983141983155983141983150983156983137983156983145983151983150

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 1315

13

983105983120983120983109983118983108983113983128 983107 991251 983109983150983139983151983157983150983156983141983154 983107983151983150983142983145983143983157983154983137983156983145983151983150 983110983145983148983141

SOC Encounter Input configuration file

global rda_Input

set rda_Input(ui_netlist) synthesized_verilogpipeline_testbenchgatev

set rda_Input(ui_timingcon_file) synthesized_verilogpipeline_testbenchsdc

set rda_Input(ui_topcell) mips_pipeline_testbench

set rda_Input(ui_netlisttype) Verilog

set rda_Input(ui_ilmlist)

set rda_Input(ui_settop) 1

set rda_Input(ui_celllib)

set rda_Input(ui_iolib)

set rda_Input(ui_areaiolib)

set rda_Input(ui_blklib)

set rda_Input(ui_kboxlib)

set rda_Input(ui_timelib) cell_lib_filesscmetro_cms9flp-lvt_tt_1p2v_25clib

set rda_Input(ui_smodDef)

set rda_Input(ui_smodData)

set rda_Input(ui_dpath)

set rda_Input(ui_tech_file)

set rda_Input(ui_buf_footprint) BUFX2MTH

set rda_Input(ui_delay_footprint) BUFX2MTH

set rda_Input(ui_inv_footprint) INVX1MTH

set rda_Input(ui_leffile) cell_lib_fileslefcms9flp_8lm_2thick_techlef cell_lib_fileslefcms9flplvt_m_macroslef

set rda_Input(ui_core_cntl) aspect

set rda_Input(ui_aspect_ratio) 10

set rda_Input(ui_core_util) 07

set rda_Input(ui_core_height)

set rda_Input(ui_core_width)

set rda_Input(ui_core_to_left) 30

set rda_Input(ui_core_to_right) 30

set rda_Input(ui_core_to_top) 30set rda_Input(ui_core_to_bottom) 30

set rda_Input(ui_max_io_height) 0

set rda_Input(ui_row_height)

set rda_Input(ui_isHorTrackHalfPitch) 0

set rda_Input(ui_isVerTrackHalfPitch) 1

set rda_Input(ui_ioOri) R180

set rda_Input(ui_isOrigCenter) 0

set rda_Input(ui_exc_net)

set rda_Input(ui_delay_limit) 1000

set rda_Input(ui_net_delay) 10000ps

set rda_Input(ui_net_load) 05pf

set rda_Input(ui_in_tran_delay) 1200ps

set rda_Input(ui_captbl_file)

set rda_Input(ui_cap_scale) 10

set rda_Input(ui_xcap_scale) 10

set rda_Input(ui_res_scale) 10

set rda_Input(ui_shr_scale) 10set rda_Input(ui_time_unit) none

set rda_Input(ui_cap_unit)

set rda_Input(ui_sigstormlib)

set rda_Input(ui_cdb_file)

set rda_Input(ui_echo_file)

set rda_Input(ui_qxtech_file)

set rda_Input(ui_qxlib_file)

set rda_Input(ui_qxconf_file)

set rda_Input(ui_pwrnet) VDD

set rda_Input(ui_gndnet) VSS

set rda_Input(flip_first) 1

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14

set rda_Input(double_back) 1

set rda_Input(assign_buffer) 0

set rda_Input(ui_pg_connections) [list

PINVDD

PINVSS

]

set rda_Input(PINVDD) VDD

set rda_Input(PINVSS) VSS

7222019 Extra Project hhhh

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983105983120983120983109983118983108983113983128 983108 991251 983123983161983150983156983144983141983155983145983155 983107983151983150983142983145983143983157983154983137983156983145983151983150 983107983151983140983141

synopsys synthesis script

set hdlin_auto_save_templates true

set hdlin_check_no_latch true

set hdlin_warn_sens_list true

define_name_rules MYrules -map [ _ ] _

read_verilog verilog_inputoutv

current_design mips_pipeline_testbench

link

constraints are below

erase all attributes and constrains from the current design

reset_design

set wire loading mode to top

set_wire_load_mode top

Create clock with 5ns period

create_clock clk -name clk -period 5

change_names -rules MYrules -hierarchy

Compile with completely disolved design

compile -ungroup_all

Make sure we are at the top level

set current_design mips_pipeline_testbench

Generate area and constraints reports on the optimized design

report_area gt reportsarearpt

Generate timing report for worst case path

report_timing gt reportsdelayrpt

report_clock gt reportsclockrpt

Save the compiled design

write -format verilog -hierarchy -output synthesized_verilogpipeline_testbenchgatev

write_sdc synthesized_verilogpipeline_testbenchsdc

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3

983113983150983156983154983151983140983157983139983156983145983151983150

This project involved the creation of an on-die representation of a pipelined MIPS

CPU from code acquisition to synthesis to final die layout Although we have had

experience with ModelSIM and writing Verilog from other projects during this term

many of the tools required to complete the synthesis and on-die representation were

completely new to us We will explain all the steps taken to reach the final

representation how we simulated our pipelined CPU the pitfalls we encountered and

how we overcame them and we will explain how we simulated the delay and what those

delay values were

983123983156983141983152983155 983124983137983147983141983150 983137983150983140 983123983145983149983157983148983137983156983145983151983150

1 If you havenrsquot already create a test bench for your verilog code

2 Place all of your v files in the verilog_input folder

3 Modify the dc_syn file inside of the synthesis folder to include all of your v files

read_verilog verilog_inputfile1v

read_verilog verilog_inputfile2v

4 Change both of the current_ design parameter to contain the name of your test

bench module Also make sure your test bench module has a clock input

current_design mips_pipeline_testbench

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4

5 Create a clock in the design change the create_clock command to have the

get_ports parameter to point you your clock register Ours was named ldquoclkrdquo

create_clock clk -name cpu_clock -period 5

6 Change the names of the output files to something useful

write -format verilog -hierarchy -output

synthesized_verilogpipeline_testbenchgatev

write_sdc synthesized_verilogpipeline_testbenchsdc

7 Open a terminal navigate to the synthesis folder and execute the following

command This starts the Design Vision program and creates gate-level

synthesized verilog If you donrsquot have your current design listed as your test

bench thing will go wring and you may or may not get errors

design_vision-xg -f dc_syn

8 After the Design Vision program loads choose Schematic -gt New Design

Schematic View If not already selected make sure your test bench is loaded in

the drop-down box at the top of the screen If you didnrsquot set the current_design

parameter correctly your test bench will load as a very small design instead of

your whole cpu

9 After ogling your cool design close Design Vision

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5

10 Make sure your gave-level verilog was synthesized correctly by running is in

modelsim and verifying identical operation to your original code It should be

located in

synthesized_verilog[name]gatev

11 Three reports are generated from the synthesis an area report clock report and a

delay report they are placed in the synthesisreports folder Verify the clock was

asserted correctly to you design by opening the clock report you should see

something like this

Clock Period Waveform Attrs Sources

--------------------------------------------------------------------------------

clk 500 0 25 clk

--------------------------------------------------------------------------------

If the clock report looks correct open the delay report If itrsquos wrong your

test bench or synthesis configuration file are incorrect The delay report

will tell you if your selected clock period will work for the gate simulated

gate delays from Design Vision It should look something like this

Point Incr Path

-------------------------------------------------------------------------- ---------------

clock clk (rise edge) 000 000clock network delay (ideal) 000 000

dutWB_MemtoReg_regCK (DFFTRX1MTH) 000 000 r

data required time 491

-------------------------------------------------------------------------- ---------------

data required time 491

data arrival time -490

-------------------------------------------------------------------------- ---------------slack (MET) 001

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6

12 Change the directory in your shell to the encounter folder

13 Edit encounterconf in the encounter folder

1

Make sure your lib and lef are pointed to correctly

set rda_Input(ui_timelib) cell_lib_filesscmetro_cms9flp-

lvt_tt_1p2v_25clib

set rda_Input(ui_leffile) cell_lib_fileslefcms9flp_8lm_2thick_techlef

cell_lib_fileslefcms9flplvt_m_macroslef

2 Make sure your test bench is your top cell

set rda_Input(ui_topcell) mips_pipeline_testbench

3 Make sure your timing and netlist files are pointed to correctly

set rda_Input(ui_netlist) synthesized_verilog[name]gatev

set rda_Input(ui_timingcon_file) synthesized_verilog[name]sdc

14 Run Cadence encounter We found it in

ldquousrlocalappscadenceSOCcurrentbinencounterrdquo

15 Navigate to Design -gt Design Import -gt Load and select your ldquoencounterconfrdquo

file and click OK You should see a black square with gray horizontal lines on the

screen

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7

16 Add power rings by navigating to Power -gt Power Planning -gt Add Rings Type

VSS VDD into the Net(s) area specify metal layers and ring width (We used

TopBottom Metal5 and LeftRight Metal6) and select center in channel click

ldquoupdaterdquo to see what values it is actually going to use Click ldquoOKrdquo

17 Add horizontal power buses by navigating to Route -gt Special Route and clicking

ldquoOKrdquo (the default values are usually acceptable)

18 Navigate to Place -gt Standard Cells and click ldquoOKrdquo this will place all of the

standard blocks This step can take a while so be patient To make the cells show

up by clicking on the Physical View button in the top right corner of the screen

19 Now go to Edit -gt Pin Editor and click on your clock(s) in the list of pins and

change USE to CLOCK

20 Add filler blocks to connect the power rails between the standard cells with Place

-gt Physical Cells -gt Add Filler and click on ldquoselectrdquo Highlight all fillers and click

add Then click ldquoCloserdquo and then click ldquoOKrdquo This will add filler blocks fitting

the largest block it can into each hole

21 To route the blocks run Route -gt Nanoroute -gt Route with the default options

Sometimes unnecessarily ugly routes will be taken manually fix these to ensure a

clean signal path if you would like

22 Now run Timing -gt Optimize with ldquoPost-Routerdquo selected

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9

CPU and the current_design parameter serves as the entry point overview file of that

hierarchy We ran Design Vision many many times before discovering this error

After synthesizing our CPU we ran into a third major pitfall when trying to time

the synthesized CPU in Design Vision We began synthesis by using the pipelined

testbench which contained a clock but did not have a clock as input When using the

testbench Design Vision said we had no clock and we couldnrsquot time our CPU We had

to have an output Y and input A then set them equal to each other on the posedge of the

clock along with running our MIPS pipeline module and with no reset signal For

whatever reason these changes added a clock to our synthesis and we could time the

pipelined CPU

After synthesizing we were able to move on to the on-die representation phase

where we encountered only minor easily remedied issues such as forgetting to check or

uncheck a dialog box entry etc All these issues were quickly taking care of by re-

reading the online tutorial

983123983145983149983157983148983137983156983141983140 983108983141983148983137983161

Following is the report created by Design Vision on simulated delay

Report timing

-path full-delay max-max_paths 1

Design mips_pipeline_testbenchVersion X-200509-SP2Date Fri Dec 12 142903 2008

A fanout number of 1000 was used for high fanout net computations

Operating Conditions tt_1p2v_25c Library scmetro_cms9flp-lvt_tt_1p2v_25cWire Load Model Mode top

Startpoint dutWB_MemtoReg_reg(rising edge-triggered flip-flop clocked by clk)

Endpoint dutMEM_Zero_reg(rising edge-triggered flip-flop clocked by clk)

Path Group clk

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Path Type max

Point Incr Path--------------------------------------------------------------------------clock clk (rise edge) 000 000clock network delay (ideal) 000 000dutWB_MemtoReg_regCK (DFFTRX1MTH) 000 000 rdutWB_MemtoReg_regQ (DFFTRX1MTH) 017 017 f

U335Y (BUFX2MTH) 016 033 fU970Y (AO22X2MTH) 017 049 fU258Y (BUFX4MTH) 008 057 fU282Y (AOI22X1MTH) 007 064 rU278Y (OAI2BB1X2MTH) 004 067 fU268Y (AO22X2MTH) 015 082 fdutEX_ALUadd_145U1_2CO (ADDFX2MTH) 023 105 fdutEX_ALUadd_145U1_3CO (ADDFX2MTH) 013 118 fdutEX_ALUadd_145U1_4CO (ADDFX2MTH) 013 131 fdutEX_ALUadd_145U1_5CO (ADDFX2MTH) 013 143 fdutEX_ALUadd_145U1_6CO (ADDFX2MTH) 013 156 fdutEX_ALUadd_145U1_7CO (ADDFX2MTH) 013 168 fdutEX_ALUadd_145U1_8CO (ADDFX2MTH) 013 181 fdutEX_ALUadd_145U1_9CO (ADDFX2MTH) 013 194 fdutEX_ALUadd_145U1_10CO (ADDFX2MTH) 013 206 fdutEX_ALUadd_145U1_11CO (ADDFX2MTH) 013 219 fdutEX_ALUadd_145U1_12CO (ADDFX2MTH) 013 232 f

dutEX_ALUadd_145U1_13CO (ADDFX2MTH) 013 244 fdutEX_ALUadd_145U1_14CO (ADDFX2MTH) 013 257 fdutEX_ALUadd_145U1_15CO (ADDFX2MTH) 013 270 fdutEX_ALUadd_145U1_16CO (ADDFX2MTH) 013 282 fdutEX_ALUadd_145U1_17CO (ADDFX2MTH) 013 295 fdutEX_ALUadd_145U1_18CO (ADDFX2MTH) 013 308 fdutEX_ALUadd_145U1_19CO (ADDFX2MTH) 013 320 fdutEX_ALUadd_145U1_20CO (ADDFX2MTH) 013 333 fdutEX_ALUadd_145U1_21CO (ADDFX2MTH) 013 346 fdutEX_ALUadd_145U1_22CO (ADDFX2MTH) 013 358 fdutEX_ALUadd_145U1_23CO (ADDFX2MTH) 013 371 fdutEX_ALUadd_145U1_24CO (ADDFX2MTH) 013 384 fdutEX_ALUadd_145U1_25CO (ADDFX2MTH) 013 396 fdutEX_ALUadd_145U1_26CO (ADDFX2MTH) 013 409 fdutEX_ALUadd_145U1_27CO (ADDFX2MTH) 014 423 fU272Y (NAND2X1MTH) 004 427 rU267Y (NAND3X2MTH) 005 432 f

dutEX_ALUadd_145U1_29CO (ADDFX2MTH) 012 444 fdutEX_ALUadd_145U1_30CO (ADDFX2MTH) 012 457 fdutEX_ALUadd_145U1_31Y (XOR3X1MTH) 009 466 fU251Y (NAND2X1MTH) 004 469 rU252Y (OAI2B11X2MTH) 007 476 fU269Y (NOR2XLMTH) 006 482 rU259Y (NAND2XLMTH) 004 486 fU289Y (NOR2X1MTH) 004 490 rdutMEM_Zero_regD (DFFTRX1MTH) 000 490 rdata arrival time 490

clock clk (rise edge) 500 500clock network delay (ideal) 000 500dutMEM_Zero_regCK (DFFTRX1MTH) 000 500 rlibrary setup time -009 491data required time 491--------------------------------------------------------------------------

data required time 491data arrival time -490--------------------------------------------------------------------------slack (MET) 001

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11

983105983120983120983109983118983108983113983128 983105 991251 983123983161983150983156983144983141983155983145983162983141983140 983111983137983156983141 983116983141983158983141983148 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125

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983105983120983120983109983118983108983113983128 983106 991251 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125 983119983150983085983108983145983141 983122983141983152983154983141983155983141983150983156983137983156983145983151983150

7222019 Extra Project hhhh

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983105983120983120983109983118983108983113983128 983107 991251 983109983150983139983151983157983150983156983141983154 983107983151983150983142983145983143983157983154983137983156983145983151983150 983110983145983148983141

SOC Encounter Input configuration file

global rda_Input

set rda_Input(ui_netlist) synthesized_verilogpipeline_testbenchgatev

set rda_Input(ui_timingcon_file) synthesized_verilogpipeline_testbenchsdc

set rda_Input(ui_topcell) mips_pipeline_testbench

set rda_Input(ui_netlisttype) Verilog

set rda_Input(ui_ilmlist)

set rda_Input(ui_settop) 1

set rda_Input(ui_celllib)

set rda_Input(ui_iolib)

set rda_Input(ui_areaiolib)

set rda_Input(ui_blklib)

set rda_Input(ui_kboxlib)

set rda_Input(ui_timelib) cell_lib_filesscmetro_cms9flp-lvt_tt_1p2v_25clib

set rda_Input(ui_smodDef)

set rda_Input(ui_smodData)

set rda_Input(ui_dpath)

set rda_Input(ui_tech_file)

set rda_Input(ui_buf_footprint) BUFX2MTH

set rda_Input(ui_delay_footprint) BUFX2MTH

set rda_Input(ui_inv_footprint) INVX1MTH

set rda_Input(ui_leffile) cell_lib_fileslefcms9flp_8lm_2thick_techlef cell_lib_fileslefcms9flplvt_m_macroslef

set rda_Input(ui_core_cntl) aspect

set rda_Input(ui_aspect_ratio) 10

set rda_Input(ui_core_util) 07

set rda_Input(ui_core_height)

set rda_Input(ui_core_width)

set rda_Input(ui_core_to_left) 30

set rda_Input(ui_core_to_right) 30

set rda_Input(ui_core_to_top) 30set rda_Input(ui_core_to_bottom) 30

set rda_Input(ui_max_io_height) 0

set rda_Input(ui_row_height)

set rda_Input(ui_isHorTrackHalfPitch) 0

set rda_Input(ui_isVerTrackHalfPitch) 1

set rda_Input(ui_ioOri) R180

set rda_Input(ui_isOrigCenter) 0

set rda_Input(ui_exc_net)

set rda_Input(ui_delay_limit) 1000

set rda_Input(ui_net_delay) 10000ps

set rda_Input(ui_net_load) 05pf

set rda_Input(ui_in_tran_delay) 1200ps

set rda_Input(ui_captbl_file)

set rda_Input(ui_cap_scale) 10

set rda_Input(ui_xcap_scale) 10

set rda_Input(ui_res_scale) 10

set rda_Input(ui_shr_scale) 10set rda_Input(ui_time_unit) none

set rda_Input(ui_cap_unit)

set rda_Input(ui_sigstormlib)

set rda_Input(ui_cdb_file)

set rda_Input(ui_echo_file)

set rda_Input(ui_qxtech_file)

set rda_Input(ui_qxlib_file)

set rda_Input(ui_qxconf_file)

set rda_Input(ui_pwrnet) VDD

set rda_Input(ui_gndnet) VSS

set rda_Input(flip_first) 1

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14

set rda_Input(double_back) 1

set rda_Input(assign_buffer) 0

set rda_Input(ui_pg_connections) [list

PINVDD

PINVSS

]

set rda_Input(PINVDD) VDD

set rda_Input(PINVSS) VSS

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983105983120983120983109983118983108983113983128 983108 991251 983123983161983150983156983144983141983155983145983155 983107983151983150983142983145983143983157983154983137983156983145983151983150 983107983151983140983141

synopsys synthesis script

set hdlin_auto_save_templates true

set hdlin_check_no_latch true

set hdlin_warn_sens_list true

define_name_rules MYrules -map [ _ ] _

read_verilog verilog_inputoutv

current_design mips_pipeline_testbench

link

constraints are below

erase all attributes and constrains from the current design

reset_design

set wire loading mode to top

set_wire_load_mode top

Create clock with 5ns period

create_clock clk -name clk -period 5

change_names -rules MYrules -hierarchy

Compile with completely disolved design

compile -ungroup_all

Make sure we are at the top level

set current_design mips_pipeline_testbench

Generate area and constraints reports on the optimized design

report_area gt reportsarearpt

Generate timing report for worst case path

report_timing gt reportsdelayrpt

report_clock gt reportsclockrpt

Save the compiled design

write -format verilog -hierarchy -output synthesized_verilogpipeline_testbenchgatev

write_sdc synthesized_verilogpipeline_testbenchsdc

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 415

4

5 Create a clock in the design change the create_clock command to have the

get_ports parameter to point you your clock register Ours was named ldquoclkrdquo

create_clock clk -name cpu_clock -period 5

6 Change the names of the output files to something useful

write -format verilog -hierarchy -output

synthesized_verilogpipeline_testbenchgatev

write_sdc synthesized_verilogpipeline_testbenchsdc

7 Open a terminal navigate to the synthesis folder and execute the following

command This starts the Design Vision program and creates gate-level

synthesized verilog If you donrsquot have your current design listed as your test

bench thing will go wring and you may or may not get errors

design_vision-xg -f dc_syn

8 After the Design Vision program loads choose Schematic -gt New Design

Schematic View If not already selected make sure your test bench is loaded in

the drop-down box at the top of the screen If you didnrsquot set the current_design

parameter correctly your test bench will load as a very small design instead of

your whole cpu

9 After ogling your cool design close Design Vision

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 515

5

10 Make sure your gave-level verilog was synthesized correctly by running is in

modelsim and verifying identical operation to your original code It should be

located in

synthesized_verilog[name]gatev

11 Three reports are generated from the synthesis an area report clock report and a

delay report they are placed in the synthesisreports folder Verify the clock was

asserted correctly to you design by opening the clock report you should see

something like this

Clock Period Waveform Attrs Sources

--------------------------------------------------------------------------------

clk 500 0 25 clk

--------------------------------------------------------------------------------

If the clock report looks correct open the delay report If itrsquos wrong your

test bench or synthesis configuration file are incorrect The delay report

will tell you if your selected clock period will work for the gate simulated

gate delays from Design Vision It should look something like this

Point Incr Path

-------------------------------------------------------------------------- ---------------

clock clk (rise edge) 000 000clock network delay (ideal) 000 000

dutWB_MemtoReg_regCK (DFFTRX1MTH) 000 000 r

data required time 491

-------------------------------------------------------------------------- ---------------

data required time 491

data arrival time -490

-------------------------------------------------------------------------- ---------------slack (MET) 001

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 615

6

12 Change the directory in your shell to the encounter folder

13 Edit encounterconf in the encounter folder

1

Make sure your lib and lef are pointed to correctly

set rda_Input(ui_timelib) cell_lib_filesscmetro_cms9flp-

lvt_tt_1p2v_25clib

set rda_Input(ui_leffile) cell_lib_fileslefcms9flp_8lm_2thick_techlef

cell_lib_fileslefcms9flplvt_m_macroslef

2 Make sure your test bench is your top cell

set rda_Input(ui_topcell) mips_pipeline_testbench

3 Make sure your timing and netlist files are pointed to correctly

set rda_Input(ui_netlist) synthesized_verilog[name]gatev

set rda_Input(ui_timingcon_file) synthesized_verilog[name]sdc

14 Run Cadence encounter We found it in

ldquousrlocalappscadenceSOCcurrentbinencounterrdquo

15 Navigate to Design -gt Design Import -gt Load and select your ldquoencounterconfrdquo

file and click OK You should see a black square with gray horizontal lines on the

screen

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 715

7

16 Add power rings by navigating to Power -gt Power Planning -gt Add Rings Type

VSS VDD into the Net(s) area specify metal layers and ring width (We used

TopBottom Metal5 and LeftRight Metal6) and select center in channel click

ldquoupdaterdquo to see what values it is actually going to use Click ldquoOKrdquo

17 Add horizontal power buses by navigating to Route -gt Special Route and clicking

ldquoOKrdquo (the default values are usually acceptable)

18 Navigate to Place -gt Standard Cells and click ldquoOKrdquo this will place all of the

standard blocks This step can take a while so be patient To make the cells show

up by clicking on the Physical View button in the top right corner of the screen

19 Now go to Edit -gt Pin Editor and click on your clock(s) in the list of pins and

change USE to CLOCK

20 Add filler blocks to connect the power rails between the standard cells with Place

-gt Physical Cells -gt Add Filler and click on ldquoselectrdquo Highlight all fillers and click

add Then click ldquoCloserdquo and then click ldquoOKrdquo This will add filler blocks fitting

the largest block it can into each hole

21 To route the blocks run Route -gt Nanoroute -gt Route with the default options

Sometimes unnecessarily ugly routes will be taken manually fix these to ensure a

clean signal path if you would like

22 Now run Timing -gt Optimize with ldquoPost-Routerdquo selected

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 815

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 915

9

CPU and the current_design parameter serves as the entry point overview file of that

hierarchy We ran Design Vision many many times before discovering this error

After synthesizing our CPU we ran into a third major pitfall when trying to time

the synthesized CPU in Design Vision We began synthesis by using the pipelined

testbench which contained a clock but did not have a clock as input When using the

testbench Design Vision said we had no clock and we couldnrsquot time our CPU We had

to have an output Y and input A then set them equal to each other on the posedge of the

clock along with running our MIPS pipeline module and with no reset signal For

whatever reason these changes added a clock to our synthesis and we could time the

pipelined CPU

After synthesizing we were able to move on to the on-die representation phase

where we encountered only minor easily remedied issues such as forgetting to check or

uncheck a dialog box entry etc All these issues were quickly taking care of by re-

reading the online tutorial

983123983145983149983157983148983137983156983141983140 983108983141983148983137983161

Following is the report created by Design Vision on simulated delay

Report timing

-path full-delay max-max_paths 1

Design mips_pipeline_testbenchVersion X-200509-SP2Date Fri Dec 12 142903 2008

A fanout number of 1000 was used for high fanout net computations

Operating Conditions tt_1p2v_25c Library scmetro_cms9flp-lvt_tt_1p2v_25cWire Load Model Mode top

Startpoint dutWB_MemtoReg_reg(rising edge-triggered flip-flop clocked by clk)

Endpoint dutMEM_Zero_reg(rising edge-triggered flip-flop clocked by clk)

Path Group clk

7222019 Extra Project hhhh

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10

Path Type max

Point Incr Path--------------------------------------------------------------------------clock clk (rise edge) 000 000clock network delay (ideal) 000 000dutWB_MemtoReg_regCK (DFFTRX1MTH) 000 000 rdutWB_MemtoReg_regQ (DFFTRX1MTH) 017 017 f

U335Y (BUFX2MTH) 016 033 fU970Y (AO22X2MTH) 017 049 fU258Y (BUFX4MTH) 008 057 fU282Y (AOI22X1MTH) 007 064 rU278Y (OAI2BB1X2MTH) 004 067 fU268Y (AO22X2MTH) 015 082 fdutEX_ALUadd_145U1_2CO (ADDFX2MTH) 023 105 fdutEX_ALUadd_145U1_3CO (ADDFX2MTH) 013 118 fdutEX_ALUadd_145U1_4CO (ADDFX2MTH) 013 131 fdutEX_ALUadd_145U1_5CO (ADDFX2MTH) 013 143 fdutEX_ALUadd_145U1_6CO (ADDFX2MTH) 013 156 fdutEX_ALUadd_145U1_7CO (ADDFX2MTH) 013 168 fdutEX_ALUadd_145U1_8CO (ADDFX2MTH) 013 181 fdutEX_ALUadd_145U1_9CO (ADDFX2MTH) 013 194 fdutEX_ALUadd_145U1_10CO (ADDFX2MTH) 013 206 fdutEX_ALUadd_145U1_11CO (ADDFX2MTH) 013 219 fdutEX_ALUadd_145U1_12CO (ADDFX2MTH) 013 232 f

dutEX_ALUadd_145U1_13CO (ADDFX2MTH) 013 244 fdutEX_ALUadd_145U1_14CO (ADDFX2MTH) 013 257 fdutEX_ALUadd_145U1_15CO (ADDFX2MTH) 013 270 fdutEX_ALUadd_145U1_16CO (ADDFX2MTH) 013 282 fdutEX_ALUadd_145U1_17CO (ADDFX2MTH) 013 295 fdutEX_ALUadd_145U1_18CO (ADDFX2MTH) 013 308 fdutEX_ALUadd_145U1_19CO (ADDFX2MTH) 013 320 fdutEX_ALUadd_145U1_20CO (ADDFX2MTH) 013 333 fdutEX_ALUadd_145U1_21CO (ADDFX2MTH) 013 346 fdutEX_ALUadd_145U1_22CO (ADDFX2MTH) 013 358 fdutEX_ALUadd_145U1_23CO (ADDFX2MTH) 013 371 fdutEX_ALUadd_145U1_24CO (ADDFX2MTH) 013 384 fdutEX_ALUadd_145U1_25CO (ADDFX2MTH) 013 396 fdutEX_ALUadd_145U1_26CO (ADDFX2MTH) 013 409 fdutEX_ALUadd_145U1_27CO (ADDFX2MTH) 014 423 fU272Y (NAND2X1MTH) 004 427 rU267Y (NAND3X2MTH) 005 432 f

dutEX_ALUadd_145U1_29CO (ADDFX2MTH) 012 444 fdutEX_ALUadd_145U1_30CO (ADDFX2MTH) 012 457 fdutEX_ALUadd_145U1_31Y (XOR3X1MTH) 009 466 fU251Y (NAND2X1MTH) 004 469 rU252Y (OAI2B11X2MTH) 007 476 fU269Y (NOR2XLMTH) 006 482 rU259Y (NAND2XLMTH) 004 486 fU289Y (NOR2X1MTH) 004 490 rdutMEM_Zero_regD (DFFTRX1MTH) 000 490 rdata arrival time 490

clock clk (rise edge) 500 500clock network delay (ideal) 000 500dutMEM_Zero_regCK (DFFTRX1MTH) 000 500 rlibrary setup time -009 491data required time 491--------------------------------------------------------------------------

data required time 491data arrival time -490--------------------------------------------------------------------------slack (MET) 001

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 1115

11

983105983120983120983109983118983108983113983128 983105 991251 983123983161983150983156983144983141983155983145983162983141983140 983111983137983156983141 983116983141983158983141983148 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 1215

12

983105983120983120983109983118983108983113983128 983106 991251 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125 983119983150983085983108983145983141 983122983141983152983154983141983155983141983150983156983137983156983145983151983150

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 1315

13

983105983120983120983109983118983108983113983128 983107 991251 983109983150983139983151983157983150983156983141983154 983107983151983150983142983145983143983157983154983137983156983145983151983150 983110983145983148983141

SOC Encounter Input configuration file

global rda_Input

set rda_Input(ui_netlist) synthesized_verilogpipeline_testbenchgatev

set rda_Input(ui_timingcon_file) synthesized_verilogpipeline_testbenchsdc

set rda_Input(ui_topcell) mips_pipeline_testbench

set rda_Input(ui_netlisttype) Verilog

set rda_Input(ui_ilmlist)

set rda_Input(ui_settop) 1

set rda_Input(ui_celllib)

set rda_Input(ui_iolib)

set rda_Input(ui_areaiolib)

set rda_Input(ui_blklib)

set rda_Input(ui_kboxlib)

set rda_Input(ui_timelib) cell_lib_filesscmetro_cms9flp-lvt_tt_1p2v_25clib

set rda_Input(ui_smodDef)

set rda_Input(ui_smodData)

set rda_Input(ui_dpath)

set rda_Input(ui_tech_file)

set rda_Input(ui_buf_footprint) BUFX2MTH

set rda_Input(ui_delay_footprint) BUFX2MTH

set rda_Input(ui_inv_footprint) INVX1MTH

set rda_Input(ui_leffile) cell_lib_fileslefcms9flp_8lm_2thick_techlef cell_lib_fileslefcms9flplvt_m_macroslef

set rda_Input(ui_core_cntl) aspect

set rda_Input(ui_aspect_ratio) 10

set rda_Input(ui_core_util) 07

set rda_Input(ui_core_height)

set rda_Input(ui_core_width)

set rda_Input(ui_core_to_left) 30

set rda_Input(ui_core_to_right) 30

set rda_Input(ui_core_to_top) 30set rda_Input(ui_core_to_bottom) 30

set rda_Input(ui_max_io_height) 0

set rda_Input(ui_row_height)

set rda_Input(ui_isHorTrackHalfPitch) 0

set rda_Input(ui_isVerTrackHalfPitch) 1

set rda_Input(ui_ioOri) R180

set rda_Input(ui_isOrigCenter) 0

set rda_Input(ui_exc_net)

set rda_Input(ui_delay_limit) 1000

set rda_Input(ui_net_delay) 10000ps

set rda_Input(ui_net_load) 05pf

set rda_Input(ui_in_tran_delay) 1200ps

set rda_Input(ui_captbl_file)

set rda_Input(ui_cap_scale) 10

set rda_Input(ui_xcap_scale) 10

set rda_Input(ui_res_scale) 10

set rda_Input(ui_shr_scale) 10set rda_Input(ui_time_unit) none

set rda_Input(ui_cap_unit)

set rda_Input(ui_sigstormlib)

set rda_Input(ui_cdb_file)

set rda_Input(ui_echo_file)

set rda_Input(ui_qxtech_file)

set rda_Input(ui_qxlib_file)

set rda_Input(ui_qxconf_file)

set rda_Input(ui_pwrnet) VDD

set rda_Input(ui_gndnet) VSS

set rda_Input(flip_first) 1

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14

set rda_Input(double_back) 1

set rda_Input(assign_buffer) 0

set rda_Input(ui_pg_connections) [list

PINVDD

PINVSS

]

set rda_Input(PINVDD) VDD

set rda_Input(PINVSS) VSS

7222019 Extra Project hhhh

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983105983120983120983109983118983108983113983128 983108 991251 983123983161983150983156983144983141983155983145983155 983107983151983150983142983145983143983157983154983137983156983145983151983150 983107983151983140983141

synopsys synthesis script

set hdlin_auto_save_templates true

set hdlin_check_no_latch true

set hdlin_warn_sens_list true

define_name_rules MYrules -map [ _ ] _

read_verilog verilog_inputoutv

current_design mips_pipeline_testbench

link

constraints are below

erase all attributes and constrains from the current design

reset_design

set wire loading mode to top

set_wire_load_mode top

Create clock with 5ns period

create_clock clk -name clk -period 5

change_names -rules MYrules -hierarchy

Compile with completely disolved design

compile -ungroup_all

Make sure we are at the top level

set current_design mips_pipeline_testbench

Generate area and constraints reports on the optimized design

report_area gt reportsarearpt

Generate timing report for worst case path

report_timing gt reportsdelayrpt

report_clock gt reportsclockrpt

Save the compiled design

write -format verilog -hierarchy -output synthesized_verilogpipeline_testbenchgatev

write_sdc synthesized_verilogpipeline_testbenchsdc

7222019 Extra Project hhhh

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5

10 Make sure your gave-level verilog was synthesized correctly by running is in

modelsim and verifying identical operation to your original code It should be

located in

synthesized_verilog[name]gatev

11 Three reports are generated from the synthesis an area report clock report and a

delay report they are placed in the synthesisreports folder Verify the clock was

asserted correctly to you design by opening the clock report you should see

something like this

Clock Period Waveform Attrs Sources

--------------------------------------------------------------------------------

clk 500 0 25 clk

--------------------------------------------------------------------------------

If the clock report looks correct open the delay report If itrsquos wrong your

test bench or synthesis configuration file are incorrect The delay report

will tell you if your selected clock period will work for the gate simulated

gate delays from Design Vision It should look something like this

Point Incr Path

-------------------------------------------------------------------------- ---------------

clock clk (rise edge) 000 000clock network delay (ideal) 000 000

dutWB_MemtoReg_regCK (DFFTRX1MTH) 000 000 r

data required time 491

-------------------------------------------------------------------------- ---------------

data required time 491

data arrival time -490

-------------------------------------------------------------------------- ---------------slack (MET) 001

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 615

6

12 Change the directory in your shell to the encounter folder

13 Edit encounterconf in the encounter folder

1

Make sure your lib and lef are pointed to correctly

set rda_Input(ui_timelib) cell_lib_filesscmetro_cms9flp-

lvt_tt_1p2v_25clib

set rda_Input(ui_leffile) cell_lib_fileslefcms9flp_8lm_2thick_techlef

cell_lib_fileslefcms9flplvt_m_macroslef

2 Make sure your test bench is your top cell

set rda_Input(ui_topcell) mips_pipeline_testbench

3 Make sure your timing and netlist files are pointed to correctly

set rda_Input(ui_netlist) synthesized_verilog[name]gatev

set rda_Input(ui_timingcon_file) synthesized_verilog[name]sdc

14 Run Cadence encounter We found it in

ldquousrlocalappscadenceSOCcurrentbinencounterrdquo

15 Navigate to Design -gt Design Import -gt Load and select your ldquoencounterconfrdquo

file and click OK You should see a black square with gray horizontal lines on the

screen

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 715

7

16 Add power rings by navigating to Power -gt Power Planning -gt Add Rings Type

VSS VDD into the Net(s) area specify metal layers and ring width (We used

TopBottom Metal5 and LeftRight Metal6) and select center in channel click

ldquoupdaterdquo to see what values it is actually going to use Click ldquoOKrdquo

17 Add horizontal power buses by navigating to Route -gt Special Route and clicking

ldquoOKrdquo (the default values are usually acceptable)

18 Navigate to Place -gt Standard Cells and click ldquoOKrdquo this will place all of the

standard blocks This step can take a while so be patient To make the cells show

up by clicking on the Physical View button in the top right corner of the screen

19 Now go to Edit -gt Pin Editor and click on your clock(s) in the list of pins and

change USE to CLOCK

20 Add filler blocks to connect the power rails between the standard cells with Place

-gt Physical Cells -gt Add Filler and click on ldquoselectrdquo Highlight all fillers and click

add Then click ldquoCloserdquo and then click ldquoOKrdquo This will add filler blocks fitting

the largest block it can into each hole

21 To route the blocks run Route -gt Nanoroute -gt Route with the default options

Sometimes unnecessarily ugly routes will be taken manually fix these to ensure a

clean signal path if you would like

22 Now run Timing -gt Optimize with ldquoPost-Routerdquo selected

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 815

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 915

9

CPU and the current_design parameter serves as the entry point overview file of that

hierarchy We ran Design Vision many many times before discovering this error

After synthesizing our CPU we ran into a third major pitfall when trying to time

the synthesized CPU in Design Vision We began synthesis by using the pipelined

testbench which contained a clock but did not have a clock as input When using the

testbench Design Vision said we had no clock and we couldnrsquot time our CPU We had

to have an output Y and input A then set them equal to each other on the posedge of the

clock along with running our MIPS pipeline module and with no reset signal For

whatever reason these changes added a clock to our synthesis and we could time the

pipelined CPU

After synthesizing we were able to move on to the on-die representation phase

where we encountered only minor easily remedied issues such as forgetting to check or

uncheck a dialog box entry etc All these issues were quickly taking care of by re-

reading the online tutorial

983123983145983149983157983148983137983156983141983140 983108983141983148983137983161

Following is the report created by Design Vision on simulated delay

Report timing

-path full-delay max-max_paths 1

Design mips_pipeline_testbenchVersion X-200509-SP2Date Fri Dec 12 142903 2008

A fanout number of 1000 was used for high fanout net computations

Operating Conditions tt_1p2v_25c Library scmetro_cms9flp-lvt_tt_1p2v_25cWire Load Model Mode top

Startpoint dutWB_MemtoReg_reg(rising edge-triggered flip-flop clocked by clk)

Endpoint dutMEM_Zero_reg(rising edge-triggered flip-flop clocked by clk)

Path Group clk

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 1015

10

Path Type max

Point Incr Path--------------------------------------------------------------------------clock clk (rise edge) 000 000clock network delay (ideal) 000 000dutWB_MemtoReg_regCK (DFFTRX1MTH) 000 000 rdutWB_MemtoReg_regQ (DFFTRX1MTH) 017 017 f

U335Y (BUFX2MTH) 016 033 fU970Y (AO22X2MTH) 017 049 fU258Y (BUFX4MTH) 008 057 fU282Y (AOI22X1MTH) 007 064 rU278Y (OAI2BB1X2MTH) 004 067 fU268Y (AO22X2MTH) 015 082 fdutEX_ALUadd_145U1_2CO (ADDFX2MTH) 023 105 fdutEX_ALUadd_145U1_3CO (ADDFX2MTH) 013 118 fdutEX_ALUadd_145U1_4CO (ADDFX2MTH) 013 131 fdutEX_ALUadd_145U1_5CO (ADDFX2MTH) 013 143 fdutEX_ALUadd_145U1_6CO (ADDFX2MTH) 013 156 fdutEX_ALUadd_145U1_7CO (ADDFX2MTH) 013 168 fdutEX_ALUadd_145U1_8CO (ADDFX2MTH) 013 181 fdutEX_ALUadd_145U1_9CO (ADDFX2MTH) 013 194 fdutEX_ALUadd_145U1_10CO (ADDFX2MTH) 013 206 fdutEX_ALUadd_145U1_11CO (ADDFX2MTH) 013 219 fdutEX_ALUadd_145U1_12CO (ADDFX2MTH) 013 232 f

dutEX_ALUadd_145U1_13CO (ADDFX2MTH) 013 244 fdutEX_ALUadd_145U1_14CO (ADDFX2MTH) 013 257 fdutEX_ALUadd_145U1_15CO (ADDFX2MTH) 013 270 fdutEX_ALUadd_145U1_16CO (ADDFX2MTH) 013 282 fdutEX_ALUadd_145U1_17CO (ADDFX2MTH) 013 295 fdutEX_ALUadd_145U1_18CO (ADDFX2MTH) 013 308 fdutEX_ALUadd_145U1_19CO (ADDFX2MTH) 013 320 fdutEX_ALUadd_145U1_20CO (ADDFX2MTH) 013 333 fdutEX_ALUadd_145U1_21CO (ADDFX2MTH) 013 346 fdutEX_ALUadd_145U1_22CO (ADDFX2MTH) 013 358 fdutEX_ALUadd_145U1_23CO (ADDFX2MTH) 013 371 fdutEX_ALUadd_145U1_24CO (ADDFX2MTH) 013 384 fdutEX_ALUadd_145U1_25CO (ADDFX2MTH) 013 396 fdutEX_ALUadd_145U1_26CO (ADDFX2MTH) 013 409 fdutEX_ALUadd_145U1_27CO (ADDFX2MTH) 014 423 fU272Y (NAND2X1MTH) 004 427 rU267Y (NAND3X2MTH) 005 432 f

dutEX_ALUadd_145U1_29CO (ADDFX2MTH) 012 444 fdutEX_ALUadd_145U1_30CO (ADDFX2MTH) 012 457 fdutEX_ALUadd_145U1_31Y (XOR3X1MTH) 009 466 fU251Y (NAND2X1MTH) 004 469 rU252Y (OAI2B11X2MTH) 007 476 fU269Y (NOR2XLMTH) 006 482 rU259Y (NAND2XLMTH) 004 486 fU289Y (NOR2X1MTH) 004 490 rdutMEM_Zero_regD (DFFTRX1MTH) 000 490 rdata arrival time 490

clock clk (rise edge) 500 500clock network delay (ideal) 000 500dutMEM_Zero_regCK (DFFTRX1MTH) 000 500 rlibrary setup time -009 491data required time 491--------------------------------------------------------------------------

data required time 491data arrival time -490--------------------------------------------------------------------------slack (MET) 001

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 1115

11

983105983120983120983109983118983108983113983128 983105 991251 983123983161983150983156983144983141983155983145983162983141983140 983111983137983156983141 983116983141983158983141983148 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 1215

12

983105983120983120983109983118983108983113983128 983106 991251 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125 983119983150983085983108983145983141 983122983141983152983154983141983155983141983150983156983137983156983145983151983150

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 1315

13

983105983120983120983109983118983108983113983128 983107 991251 983109983150983139983151983157983150983156983141983154 983107983151983150983142983145983143983157983154983137983156983145983151983150 983110983145983148983141

SOC Encounter Input configuration file

global rda_Input

set rda_Input(ui_netlist) synthesized_verilogpipeline_testbenchgatev

set rda_Input(ui_timingcon_file) synthesized_verilogpipeline_testbenchsdc

set rda_Input(ui_topcell) mips_pipeline_testbench

set rda_Input(ui_netlisttype) Verilog

set rda_Input(ui_ilmlist)

set rda_Input(ui_settop) 1

set rda_Input(ui_celllib)

set rda_Input(ui_iolib)

set rda_Input(ui_areaiolib)

set rda_Input(ui_blklib)

set rda_Input(ui_kboxlib)

set rda_Input(ui_timelib) cell_lib_filesscmetro_cms9flp-lvt_tt_1p2v_25clib

set rda_Input(ui_smodDef)

set rda_Input(ui_smodData)

set rda_Input(ui_dpath)

set rda_Input(ui_tech_file)

set rda_Input(ui_buf_footprint) BUFX2MTH

set rda_Input(ui_delay_footprint) BUFX2MTH

set rda_Input(ui_inv_footprint) INVX1MTH

set rda_Input(ui_leffile) cell_lib_fileslefcms9flp_8lm_2thick_techlef cell_lib_fileslefcms9flplvt_m_macroslef

set rda_Input(ui_core_cntl) aspect

set rda_Input(ui_aspect_ratio) 10

set rda_Input(ui_core_util) 07

set rda_Input(ui_core_height)

set rda_Input(ui_core_width)

set rda_Input(ui_core_to_left) 30

set rda_Input(ui_core_to_right) 30

set rda_Input(ui_core_to_top) 30set rda_Input(ui_core_to_bottom) 30

set rda_Input(ui_max_io_height) 0

set rda_Input(ui_row_height)

set rda_Input(ui_isHorTrackHalfPitch) 0

set rda_Input(ui_isVerTrackHalfPitch) 1

set rda_Input(ui_ioOri) R180

set rda_Input(ui_isOrigCenter) 0

set rda_Input(ui_exc_net)

set rda_Input(ui_delay_limit) 1000

set rda_Input(ui_net_delay) 10000ps

set rda_Input(ui_net_load) 05pf

set rda_Input(ui_in_tran_delay) 1200ps

set rda_Input(ui_captbl_file)

set rda_Input(ui_cap_scale) 10

set rda_Input(ui_xcap_scale) 10

set rda_Input(ui_res_scale) 10

set rda_Input(ui_shr_scale) 10set rda_Input(ui_time_unit) none

set rda_Input(ui_cap_unit)

set rda_Input(ui_sigstormlib)

set rda_Input(ui_cdb_file)

set rda_Input(ui_echo_file)

set rda_Input(ui_qxtech_file)

set rda_Input(ui_qxlib_file)

set rda_Input(ui_qxconf_file)

set rda_Input(ui_pwrnet) VDD

set rda_Input(ui_gndnet) VSS

set rda_Input(flip_first) 1

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 1415

14

set rda_Input(double_back) 1

set rda_Input(assign_buffer) 0

set rda_Input(ui_pg_connections) [list

PINVDD

PINVSS

]

set rda_Input(PINVDD) VDD

set rda_Input(PINVSS) VSS

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 1515

983105983120983120983109983118983108983113983128 983108 991251 983123983161983150983156983144983141983155983145983155 983107983151983150983142983145983143983157983154983137983156983145983151983150 983107983151983140983141

synopsys synthesis script

set hdlin_auto_save_templates true

set hdlin_check_no_latch true

set hdlin_warn_sens_list true

define_name_rules MYrules -map [ _ ] _

read_verilog verilog_inputoutv

current_design mips_pipeline_testbench

link

constraints are below

erase all attributes and constrains from the current design

reset_design

set wire loading mode to top

set_wire_load_mode top

Create clock with 5ns period

create_clock clk -name clk -period 5

change_names -rules MYrules -hierarchy

Compile with completely disolved design

compile -ungroup_all

Make sure we are at the top level

set current_design mips_pipeline_testbench

Generate area and constraints reports on the optimized design

report_area gt reportsarearpt

Generate timing report for worst case path

report_timing gt reportsdelayrpt

report_clock gt reportsclockrpt

Save the compiled design

write -format verilog -hierarchy -output synthesized_verilogpipeline_testbenchgatev

write_sdc synthesized_verilogpipeline_testbenchsdc

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 615

6

12 Change the directory in your shell to the encounter folder

13 Edit encounterconf in the encounter folder

1

Make sure your lib and lef are pointed to correctly

set rda_Input(ui_timelib) cell_lib_filesscmetro_cms9flp-

lvt_tt_1p2v_25clib

set rda_Input(ui_leffile) cell_lib_fileslefcms9flp_8lm_2thick_techlef

cell_lib_fileslefcms9flplvt_m_macroslef

2 Make sure your test bench is your top cell

set rda_Input(ui_topcell) mips_pipeline_testbench

3 Make sure your timing and netlist files are pointed to correctly

set rda_Input(ui_netlist) synthesized_verilog[name]gatev

set rda_Input(ui_timingcon_file) synthesized_verilog[name]sdc

14 Run Cadence encounter We found it in

ldquousrlocalappscadenceSOCcurrentbinencounterrdquo

15 Navigate to Design -gt Design Import -gt Load and select your ldquoencounterconfrdquo

file and click OK You should see a black square with gray horizontal lines on the

screen

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 715

7

16 Add power rings by navigating to Power -gt Power Planning -gt Add Rings Type

VSS VDD into the Net(s) area specify metal layers and ring width (We used

TopBottom Metal5 and LeftRight Metal6) and select center in channel click

ldquoupdaterdquo to see what values it is actually going to use Click ldquoOKrdquo

17 Add horizontal power buses by navigating to Route -gt Special Route and clicking

ldquoOKrdquo (the default values are usually acceptable)

18 Navigate to Place -gt Standard Cells and click ldquoOKrdquo this will place all of the

standard blocks This step can take a while so be patient To make the cells show

up by clicking on the Physical View button in the top right corner of the screen

19 Now go to Edit -gt Pin Editor and click on your clock(s) in the list of pins and

change USE to CLOCK

20 Add filler blocks to connect the power rails between the standard cells with Place

-gt Physical Cells -gt Add Filler and click on ldquoselectrdquo Highlight all fillers and click

add Then click ldquoCloserdquo and then click ldquoOKrdquo This will add filler blocks fitting

the largest block it can into each hole

21 To route the blocks run Route -gt Nanoroute -gt Route with the default options

Sometimes unnecessarily ugly routes will be taken manually fix these to ensure a

clean signal path if you would like

22 Now run Timing -gt Optimize with ldquoPost-Routerdquo selected

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 815

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 915

9

CPU and the current_design parameter serves as the entry point overview file of that

hierarchy We ran Design Vision many many times before discovering this error

After synthesizing our CPU we ran into a third major pitfall when trying to time

the synthesized CPU in Design Vision We began synthesis by using the pipelined

testbench which contained a clock but did not have a clock as input When using the

testbench Design Vision said we had no clock and we couldnrsquot time our CPU We had

to have an output Y and input A then set them equal to each other on the posedge of the

clock along with running our MIPS pipeline module and with no reset signal For

whatever reason these changes added a clock to our synthesis and we could time the

pipelined CPU

After synthesizing we were able to move on to the on-die representation phase

where we encountered only minor easily remedied issues such as forgetting to check or

uncheck a dialog box entry etc All these issues were quickly taking care of by re-

reading the online tutorial

983123983145983149983157983148983137983156983141983140 983108983141983148983137983161

Following is the report created by Design Vision on simulated delay

Report timing

-path full-delay max-max_paths 1

Design mips_pipeline_testbenchVersion X-200509-SP2Date Fri Dec 12 142903 2008

A fanout number of 1000 was used for high fanout net computations

Operating Conditions tt_1p2v_25c Library scmetro_cms9flp-lvt_tt_1p2v_25cWire Load Model Mode top

Startpoint dutWB_MemtoReg_reg(rising edge-triggered flip-flop clocked by clk)

Endpoint dutMEM_Zero_reg(rising edge-triggered flip-flop clocked by clk)

Path Group clk

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10

Path Type max

Point Incr Path--------------------------------------------------------------------------clock clk (rise edge) 000 000clock network delay (ideal) 000 000dutWB_MemtoReg_regCK (DFFTRX1MTH) 000 000 rdutWB_MemtoReg_regQ (DFFTRX1MTH) 017 017 f

U335Y (BUFX2MTH) 016 033 fU970Y (AO22X2MTH) 017 049 fU258Y (BUFX4MTH) 008 057 fU282Y (AOI22X1MTH) 007 064 rU278Y (OAI2BB1X2MTH) 004 067 fU268Y (AO22X2MTH) 015 082 fdutEX_ALUadd_145U1_2CO (ADDFX2MTH) 023 105 fdutEX_ALUadd_145U1_3CO (ADDFX2MTH) 013 118 fdutEX_ALUadd_145U1_4CO (ADDFX2MTH) 013 131 fdutEX_ALUadd_145U1_5CO (ADDFX2MTH) 013 143 fdutEX_ALUadd_145U1_6CO (ADDFX2MTH) 013 156 fdutEX_ALUadd_145U1_7CO (ADDFX2MTH) 013 168 fdutEX_ALUadd_145U1_8CO (ADDFX2MTH) 013 181 fdutEX_ALUadd_145U1_9CO (ADDFX2MTH) 013 194 fdutEX_ALUadd_145U1_10CO (ADDFX2MTH) 013 206 fdutEX_ALUadd_145U1_11CO (ADDFX2MTH) 013 219 fdutEX_ALUadd_145U1_12CO (ADDFX2MTH) 013 232 f

dutEX_ALUadd_145U1_13CO (ADDFX2MTH) 013 244 fdutEX_ALUadd_145U1_14CO (ADDFX2MTH) 013 257 fdutEX_ALUadd_145U1_15CO (ADDFX2MTH) 013 270 fdutEX_ALUadd_145U1_16CO (ADDFX2MTH) 013 282 fdutEX_ALUadd_145U1_17CO (ADDFX2MTH) 013 295 fdutEX_ALUadd_145U1_18CO (ADDFX2MTH) 013 308 fdutEX_ALUadd_145U1_19CO (ADDFX2MTH) 013 320 fdutEX_ALUadd_145U1_20CO (ADDFX2MTH) 013 333 fdutEX_ALUadd_145U1_21CO (ADDFX2MTH) 013 346 fdutEX_ALUadd_145U1_22CO (ADDFX2MTH) 013 358 fdutEX_ALUadd_145U1_23CO (ADDFX2MTH) 013 371 fdutEX_ALUadd_145U1_24CO (ADDFX2MTH) 013 384 fdutEX_ALUadd_145U1_25CO (ADDFX2MTH) 013 396 fdutEX_ALUadd_145U1_26CO (ADDFX2MTH) 013 409 fdutEX_ALUadd_145U1_27CO (ADDFX2MTH) 014 423 fU272Y (NAND2X1MTH) 004 427 rU267Y (NAND3X2MTH) 005 432 f

dutEX_ALUadd_145U1_29CO (ADDFX2MTH) 012 444 fdutEX_ALUadd_145U1_30CO (ADDFX2MTH) 012 457 fdutEX_ALUadd_145U1_31Y (XOR3X1MTH) 009 466 fU251Y (NAND2X1MTH) 004 469 rU252Y (OAI2B11X2MTH) 007 476 fU269Y (NOR2XLMTH) 006 482 rU259Y (NAND2XLMTH) 004 486 fU289Y (NOR2X1MTH) 004 490 rdutMEM_Zero_regD (DFFTRX1MTH) 000 490 rdata arrival time 490

clock clk (rise edge) 500 500clock network delay (ideal) 000 500dutMEM_Zero_regCK (DFFTRX1MTH) 000 500 rlibrary setup time -009 491data required time 491--------------------------------------------------------------------------

data required time 491data arrival time -490--------------------------------------------------------------------------slack (MET) 001

7222019 Extra Project hhhh

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11

983105983120983120983109983118983108983113983128 983105 991251 983123983161983150983156983144983141983155983145983162983141983140 983111983137983156983141 983116983141983158983141983148 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 1215

12

983105983120983120983109983118983108983113983128 983106 991251 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125 983119983150983085983108983145983141 983122983141983152983154983141983155983141983150983156983137983156983145983151983150

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 1315

13

983105983120983120983109983118983108983113983128 983107 991251 983109983150983139983151983157983150983156983141983154 983107983151983150983142983145983143983157983154983137983156983145983151983150 983110983145983148983141

SOC Encounter Input configuration file

global rda_Input

set rda_Input(ui_netlist) synthesized_verilogpipeline_testbenchgatev

set rda_Input(ui_timingcon_file) synthesized_verilogpipeline_testbenchsdc

set rda_Input(ui_topcell) mips_pipeline_testbench

set rda_Input(ui_netlisttype) Verilog

set rda_Input(ui_ilmlist)

set rda_Input(ui_settop) 1

set rda_Input(ui_celllib)

set rda_Input(ui_iolib)

set rda_Input(ui_areaiolib)

set rda_Input(ui_blklib)

set rda_Input(ui_kboxlib)

set rda_Input(ui_timelib) cell_lib_filesscmetro_cms9flp-lvt_tt_1p2v_25clib

set rda_Input(ui_smodDef)

set rda_Input(ui_smodData)

set rda_Input(ui_dpath)

set rda_Input(ui_tech_file)

set rda_Input(ui_buf_footprint) BUFX2MTH

set rda_Input(ui_delay_footprint) BUFX2MTH

set rda_Input(ui_inv_footprint) INVX1MTH

set rda_Input(ui_leffile) cell_lib_fileslefcms9flp_8lm_2thick_techlef cell_lib_fileslefcms9flplvt_m_macroslef

set rda_Input(ui_core_cntl) aspect

set rda_Input(ui_aspect_ratio) 10

set rda_Input(ui_core_util) 07

set rda_Input(ui_core_height)

set rda_Input(ui_core_width)

set rda_Input(ui_core_to_left) 30

set rda_Input(ui_core_to_right) 30

set rda_Input(ui_core_to_top) 30set rda_Input(ui_core_to_bottom) 30

set rda_Input(ui_max_io_height) 0

set rda_Input(ui_row_height)

set rda_Input(ui_isHorTrackHalfPitch) 0

set rda_Input(ui_isVerTrackHalfPitch) 1

set rda_Input(ui_ioOri) R180

set rda_Input(ui_isOrigCenter) 0

set rda_Input(ui_exc_net)

set rda_Input(ui_delay_limit) 1000

set rda_Input(ui_net_delay) 10000ps

set rda_Input(ui_net_load) 05pf

set rda_Input(ui_in_tran_delay) 1200ps

set rda_Input(ui_captbl_file)

set rda_Input(ui_cap_scale) 10

set rda_Input(ui_xcap_scale) 10

set rda_Input(ui_res_scale) 10

set rda_Input(ui_shr_scale) 10set rda_Input(ui_time_unit) none

set rda_Input(ui_cap_unit)

set rda_Input(ui_sigstormlib)

set rda_Input(ui_cdb_file)

set rda_Input(ui_echo_file)

set rda_Input(ui_qxtech_file)

set rda_Input(ui_qxlib_file)

set rda_Input(ui_qxconf_file)

set rda_Input(ui_pwrnet) VDD

set rda_Input(ui_gndnet) VSS

set rda_Input(flip_first) 1

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14

set rda_Input(double_back) 1

set rda_Input(assign_buffer) 0

set rda_Input(ui_pg_connections) [list

PINVDD

PINVSS

]

set rda_Input(PINVDD) VDD

set rda_Input(PINVSS) VSS

7222019 Extra Project hhhh

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983105983120983120983109983118983108983113983128 983108 991251 983123983161983150983156983144983141983155983145983155 983107983151983150983142983145983143983157983154983137983156983145983151983150 983107983151983140983141

synopsys synthesis script

set hdlin_auto_save_templates true

set hdlin_check_no_latch true

set hdlin_warn_sens_list true

define_name_rules MYrules -map [ _ ] _

read_verilog verilog_inputoutv

current_design mips_pipeline_testbench

link

constraints are below

erase all attributes and constrains from the current design

reset_design

set wire loading mode to top

set_wire_load_mode top

Create clock with 5ns period

create_clock clk -name clk -period 5

change_names -rules MYrules -hierarchy

Compile with completely disolved design

compile -ungroup_all

Make sure we are at the top level

set current_design mips_pipeline_testbench

Generate area and constraints reports on the optimized design

report_area gt reportsarearpt

Generate timing report for worst case path

report_timing gt reportsdelayrpt

report_clock gt reportsclockrpt

Save the compiled design

write -format verilog -hierarchy -output synthesized_verilogpipeline_testbenchgatev

write_sdc synthesized_verilogpipeline_testbenchsdc

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 715

7

16 Add power rings by navigating to Power -gt Power Planning -gt Add Rings Type

VSS VDD into the Net(s) area specify metal layers and ring width (We used

TopBottom Metal5 and LeftRight Metal6) and select center in channel click

ldquoupdaterdquo to see what values it is actually going to use Click ldquoOKrdquo

17 Add horizontal power buses by navigating to Route -gt Special Route and clicking

ldquoOKrdquo (the default values are usually acceptable)

18 Navigate to Place -gt Standard Cells and click ldquoOKrdquo this will place all of the

standard blocks This step can take a while so be patient To make the cells show

up by clicking on the Physical View button in the top right corner of the screen

19 Now go to Edit -gt Pin Editor and click on your clock(s) in the list of pins and

change USE to CLOCK

20 Add filler blocks to connect the power rails between the standard cells with Place

-gt Physical Cells -gt Add Filler and click on ldquoselectrdquo Highlight all fillers and click

add Then click ldquoCloserdquo and then click ldquoOKrdquo This will add filler blocks fitting

the largest block it can into each hole

21 To route the blocks run Route -gt Nanoroute -gt Route with the default options

Sometimes unnecessarily ugly routes will be taken manually fix these to ensure a

clean signal path if you would like

22 Now run Timing -gt Optimize with ldquoPost-Routerdquo selected

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 815

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 915

9

CPU and the current_design parameter serves as the entry point overview file of that

hierarchy We ran Design Vision many many times before discovering this error

After synthesizing our CPU we ran into a third major pitfall when trying to time

the synthesized CPU in Design Vision We began synthesis by using the pipelined

testbench which contained a clock but did not have a clock as input When using the

testbench Design Vision said we had no clock and we couldnrsquot time our CPU We had

to have an output Y and input A then set them equal to each other on the posedge of the

clock along with running our MIPS pipeline module and with no reset signal For

whatever reason these changes added a clock to our synthesis and we could time the

pipelined CPU

After synthesizing we were able to move on to the on-die representation phase

where we encountered only minor easily remedied issues such as forgetting to check or

uncheck a dialog box entry etc All these issues were quickly taking care of by re-

reading the online tutorial

983123983145983149983157983148983137983156983141983140 983108983141983148983137983161

Following is the report created by Design Vision on simulated delay

Report timing

-path full-delay max-max_paths 1

Design mips_pipeline_testbenchVersion X-200509-SP2Date Fri Dec 12 142903 2008

A fanout number of 1000 was used for high fanout net computations

Operating Conditions tt_1p2v_25c Library scmetro_cms9flp-lvt_tt_1p2v_25cWire Load Model Mode top

Startpoint dutWB_MemtoReg_reg(rising edge-triggered flip-flop clocked by clk)

Endpoint dutMEM_Zero_reg(rising edge-triggered flip-flop clocked by clk)

Path Group clk

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 1015

10

Path Type max

Point Incr Path--------------------------------------------------------------------------clock clk (rise edge) 000 000clock network delay (ideal) 000 000dutWB_MemtoReg_regCK (DFFTRX1MTH) 000 000 rdutWB_MemtoReg_regQ (DFFTRX1MTH) 017 017 f

U335Y (BUFX2MTH) 016 033 fU970Y (AO22X2MTH) 017 049 fU258Y (BUFX4MTH) 008 057 fU282Y (AOI22X1MTH) 007 064 rU278Y (OAI2BB1X2MTH) 004 067 fU268Y (AO22X2MTH) 015 082 fdutEX_ALUadd_145U1_2CO (ADDFX2MTH) 023 105 fdutEX_ALUadd_145U1_3CO (ADDFX2MTH) 013 118 fdutEX_ALUadd_145U1_4CO (ADDFX2MTH) 013 131 fdutEX_ALUadd_145U1_5CO (ADDFX2MTH) 013 143 fdutEX_ALUadd_145U1_6CO (ADDFX2MTH) 013 156 fdutEX_ALUadd_145U1_7CO (ADDFX2MTH) 013 168 fdutEX_ALUadd_145U1_8CO (ADDFX2MTH) 013 181 fdutEX_ALUadd_145U1_9CO (ADDFX2MTH) 013 194 fdutEX_ALUadd_145U1_10CO (ADDFX2MTH) 013 206 fdutEX_ALUadd_145U1_11CO (ADDFX2MTH) 013 219 fdutEX_ALUadd_145U1_12CO (ADDFX2MTH) 013 232 f

dutEX_ALUadd_145U1_13CO (ADDFX2MTH) 013 244 fdutEX_ALUadd_145U1_14CO (ADDFX2MTH) 013 257 fdutEX_ALUadd_145U1_15CO (ADDFX2MTH) 013 270 fdutEX_ALUadd_145U1_16CO (ADDFX2MTH) 013 282 fdutEX_ALUadd_145U1_17CO (ADDFX2MTH) 013 295 fdutEX_ALUadd_145U1_18CO (ADDFX2MTH) 013 308 fdutEX_ALUadd_145U1_19CO (ADDFX2MTH) 013 320 fdutEX_ALUadd_145U1_20CO (ADDFX2MTH) 013 333 fdutEX_ALUadd_145U1_21CO (ADDFX2MTH) 013 346 fdutEX_ALUadd_145U1_22CO (ADDFX2MTH) 013 358 fdutEX_ALUadd_145U1_23CO (ADDFX2MTH) 013 371 fdutEX_ALUadd_145U1_24CO (ADDFX2MTH) 013 384 fdutEX_ALUadd_145U1_25CO (ADDFX2MTH) 013 396 fdutEX_ALUadd_145U1_26CO (ADDFX2MTH) 013 409 fdutEX_ALUadd_145U1_27CO (ADDFX2MTH) 014 423 fU272Y (NAND2X1MTH) 004 427 rU267Y (NAND3X2MTH) 005 432 f

dutEX_ALUadd_145U1_29CO (ADDFX2MTH) 012 444 fdutEX_ALUadd_145U1_30CO (ADDFX2MTH) 012 457 fdutEX_ALUadd_145U1_31Y (XOR3X1MTH) 009 466 fU251Y (NAND2X1MTH) 004 469 rU252Y (OAI2B11X2MTH) 007 476 fU269Y (NOR2XLMTH) 006 482 rU259Y (NAND2XLMTH) 004 486 fU289Y (NOR2X1MTH) 004 490 rdutMEM_Zero_regD (DFFTRX1MTH) 000 490 rdata arrival time 490

clock clk (rise edge) 500 500clock network delay (ideal) 000 500dutMEM_Zero_regCK (DFFTRX1MTH) 000 500 rlibrary setup time -009 491data required time 491--------------------------------------------------------------------------

data required time 491data arrival time -490--------------------------------------------------------------------------slack (MET) 001

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983105983120983120983109983118983108983113983128 983105 991251 983123983161983150983156983144983141983155983145983162983141983140 983111983137983156983141 983116983141983158983141983148 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125

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983105983120983120983109983118983108983113983128 983106 991251 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125 983119983150983085983108983145983141 983122983141983152983154983141983155983141983150983156983137983156983145983151983150

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983105983120983120983109983118983108983113983128 983107 991251 983109983150983139983151983157983150983156983141983154 983107983151983150983142983145983143983157983154983137983156983145983151983150 983110983145983148983141

SOC Encounter Input configuration file

global rda_Input

set rda_Input(ui_netlist) synthesized_verilogpipeline_testbenchgatev

set rda_Input(ui_timingcon_file) synthesized_verilogpipeline_testbenchsdc

set rda_Input(ui_topcell) mips_pipeline_testbench

set rda_Input(ui_netlisttype) Verilog

set rda_Input(ui_ilmlist)

set rda_Input(ui_settop) 1

set rda_Input(ui_celllib)

set rda_Input(ui_iolib)

set rda_Input(ui_areaiolib)

set rda_Input(ui_blklib)

set rda_Input(ui_kboxlib)

set rda_Input(ui_timelib) cell_lib_filesscmetro_cms9flp-lvt_tt_1p2v_25clib

set rda_Input(ui_smodDef)

set rda_Input(ui_smodData)

set rda_Input(ui_dpath)

set rda_Input(ui_tech_file)

set rda_Input(ui_buf_footprint) BUFX2MTH

set rda_Input(ui_delay_footprint) BUFX2MTH

set rda_Input(ui_inv_footprint) INVX1MTH

set rda_Input(ui_leffile) cell_lib_fileslefcms9flp_8lm_2thick_techlef cell_lib_fileslefcms9flplvt_m_macroslef

set rda_Input(ui_core_cntl) aspect

set rda_Input(ui_aspect_ratio) 10

set rda_Input(ui_core_util) 07

set rda_Input(ui_core_height)

set rda_Input(ui_core_width)

set rda_Input(ui_core_to_left) 30

set rda_Input(ui_core_to_right) 30

set rda_Input(ui_core_to_top) 30set rda_Input(ui_core_to_bottom) 30

set rda_Input(ui_max_io_height) 0

set rda_Input(ui_row_height)

set rda_Input(ui_isHorTrackHalfPitch) 0

set rda_Input(ui_isVerTrackHalfPitch) 1

set rda_Input(ui_ioOri) R180

set rda_Input(ui_isOrigCenter) 0

set rda_Input(ui_exc_net)

set rda_Input(ui_delay_limit) 1000

set rda_Input(ui_net_delay) 10000ps

set rda_Input(ui_net_load) 05pf

set rda_Input(ui_in_tran_delay) 1200ps

set rda_Input(ui_captbl_file)

set rda_Input(ui_cap_scale) 10

set rda_Input(ui_xcap_scale) 10

set rda_Input(ui_res_scale) 10

set rda_Input(ui_shr_scale) 10set rda_Input(ui_time_unit) none

set rda_Input(ui_cap_unit)

set rda_Input(ui_sigstormlib)

set rda_Input(ui_cdb_file)

set rda_Input(ui_echo_file)

set rda_Input(ui_qxtech_file)

set rda_Input(ui_qxlib_file)

set rda_Input(ui_qxconf_file)

set rda_Input(ui_pwrnet) VDD

set rda_Input(ui_gndnet) VSS

set rda_Input(flip_first) 1

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set rda_Input(double_back) 1

set rda_Input(assign_buffer) 0

set rda_Input(ui_pg_connections) [list

PINVDD

PINVSS

]

set rda_Input(PINVDD) VDD

set rda_Input(PINVSS) VSS

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983105983120983120983109983118983108983113983128 983108 991251 983123983161983150983156983144983141983155983145983155 983107983151983150983142983145983143983157983154983137983156983145983151983150 983107983151983140983141

synopsys synthesis script

set hdlin_auto_save_templates true

set hdlin_check_no_latch true

set hdlin_warn_sens_list true

define_name_rules MYrules -map [ _ ] _

read_verilog verilog_inputoutv

current_design mips_pipeline_testbench

link

constraints are below

erase all attributes and constrains from the current design

reset_design

set wire loading mode to top

set_wire_load_mode top

Create clock with 5ns period

create_clock clk -name clk -period 5

change_names -rules MYrules -hierarchy

Compile with completely disolved design

compile -ungroup_all

Make sure we are at the top level

set current_design mips_pipeline_testbench

Generate area and constraints reports on the optimized design

report_area gt reportsarearpt

Generate timing report for worst case path

report_timing gt reportsdelayrpt

report_clock gt reportsclockrpt

Save the compiled design

write -format verilog -hierarchy -output synthesized_verilogpipeline_testbenchgatev

write_sdc synthesized_verilogpipeline_testbenchsdc

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CPU and the current_design parameter serves as the entry point overview file of that

hierarchy We ran Design Vision many many times before discovering this error

After synthesizing our CPU we ran into a third major pitfall when trying to time

the synthesized CPU in Design Vision We began synthesis by using the pipelined

testbench which contained a clock but did not have a clock as input When using the

testbench Design Vision said we had no clock and we couldnrsquot time our CPU We had

to have an output Y and input A then set them equal to each other on the posedge of the

clock along with running our MIPS pipeline module and with no reset signal For

whatever reason these changes added a clock to our synthesis and we could time the

pipelined CPU

After synthesizing we were able to move on to the on-die representation phase

where we encountered only minor easily remedied issues such as forgetting to check or

uncheck a dialog box entry etc All these issues were quickly taking care of by re-

reading the online tutorial

983123983145983149983157983148983137983156983141983140 983108983141983148983137983161

Following is the report created by Design Vision on simulated delay

Report timing

-path full-delay max-max_paths 1

Design mips_pipeline_testbenchVersion X-200509-SP2Date Fri Dec 12 142903 2008

A fanout number of 1000 was used for high fanout net computations

Operating Conditions tt_1p2v_25c Library scmetro_cms9flp-lvt_tt_1p2v_25cWire Load Model Mode top

Startpoint dutWB_MemtoReg_reg(rising edge-triggered flip-flop clocked by clk)

Endpoint dutMEM_Zero_reg(rising edge-triggered flip-flop clocked by clk)

Path Group clk

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Path Type max

Point Incr Path--------------------------------------------------------------------------clock clk (rise edge) 000 000clock network delay (ideal) 000 000dutWB_MemtoReg_regCK (DFFTRX1MTH) 000 000 rdutWB_MemtoReg_regQ (DFFTRX1MTH) 017 017 f

U335Y (BUFX2MTH) 016 033 fU970Y (AO22X2MTH) 017 049 fU258Y (BUFX4MTH) 008 057 fU282Y (AOI22X1MTH) 007 064 rU278Y (OAI2BB1X2MTH) 004 067 fU268Y (AO22X2MTH) 015 082 fdutEX_ALUadd_145U1_2CO (ADDFX2MTH) 023 105 fdutEX_ALUadd_145U1_3CO (ADDFX2MTH) 013 118 fdutEX_ALUadd_145U1_4CO (ADDFX2MTH) 013 131 fdutEX_ALUadd_145U1_5CO (ADDFX2MTH) 013 143 fdutEX_ALUadd_145U1_6CO (ADDFX2MTH) 013 156 fdutEX_ALUadd_145U1_7CO (ADDFX2MTH) 013 168 fdutEX_ALUadd_145U1_8CO (ADDFX2MTH) 013 181 fdutEX_ALUadd_145U1_9CO (ADDFX2MTH) 013 194 fdutEX_ALUadd_145U1_10CO (ADDFX2MTH) 013 206 fdutEX_ALUadd_145U1_11CO (ADDFX2MTH) 013 219 fdutEX_ALUadd_145U1_12CO (ADDFX2MTH) 013 232 f

dutEX_ALUadd_145U1_13CO (ADDFX2MTH) 013 244 fdutEX_ALUadd_145U1_14CO (ADDFX2MTH) 013 257 fdutEX_ALUadd_145U1_15CO (ADDFX2MTH) 013 270 fdutEX_ALUadd_145U1_16CO (ADDFX2MTH) 013 282 fdutEX_ALUadd_145U1_17CO (ADDFX2MTH) 013 295 fdutEX_ALUadd_145U1_18CO (ADDFX2MTH) 013 308 fdutEX_ALUadd_145U1_19CO (ADDFX2MTH) 013 320 fdutEX_ALUadd_145U1_20CO (ADDFX2MTH) 013 333 fdutEX_ALUadd_145U1_21CO (ADDFX2MTH) 013 346 fdutEX_ALUadd_145U1_22CO (ADDFX2MTH) 013 358 fdutEX_ALUadd_145U1_23CO (ADDFX2MTH) 013 371 fdutEX_ALUadd_145U1_24CO (ADDFX2MTH) 013 384 fdutEX_ALUadd_145U1_25CO (ADDFX2MTH) 013 396 fdutEX_ALUadd_145U1_26CO (ADDFX2MTH) 013 409 fdutEX_ALUadd_145U1_27CO (ADDFX2MTH) 014 423 fU272Y (NAND2X1MTH) 004 427 rU267Y (NAND3X2MTH) 005 432 f

dutEX_ALUadd_145U1_29CO (ADDFX2MTH) 012 444 fdutEX_ALUadd_145U1_30CO (ADDFX2MTH) 012 457 fdutEX_ALUadd_145U1_31Y (XOR3X1MTH) 009 466 fU251Y (NAND2X1MTH) 004 469 rU252Y (OAI2B11X2MTH) 007 476 fU269Y (NOR2XLMTH) 006 482 rU259Y (NAND2XLMTH) 004 486 fU289Y (NOR2X1MTH) 004 490 rdutMEM_Zero_regD (DFFTRX1MTH) 000 490 rdata arrival time 490

clock clk (rise edge) 500 500clock network delay (ideal) 000 500dutMEM_Zero_regCK (DFFTRX1MTH) 000 500 rlibrary setup time -009 491data required time 491--------------------------------------------------------------------------

data required time 491data arrival time -490--------------------------------------------------------------------------slack (MET) 001

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983105983120983120983109983118983108983113983128 983105 991251 983123983161983150983156983144983141983155983145983162983141983140 983111983137983156983141 983116983141983158983141983148 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125

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983105983120983120983109983118983108983113983128 983106 991251 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125 983119983150983085983108983145983141 983122983141983152983154983141983155983141983150983156983137983156983145983151983150

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983105983120983120983109983118983108983113983128 983107 991251 983109983150983139983151983157983150983156983141983154 983107983151983150983142983145983143983157983154983137983156983145983151983150 983110983145983148983141

SOC Encounter Input configuration file

global rda_Input

set rda_Input(ui_netlist) synthesized_verilogpipeline_testbenchgatev

set rda_Input(ui_timingcon_file) synthesized_verilogpipeline_testbenchsdc

set rda_Input(ui_topcell) mips_pipeline_testbench

set rda_Input(ui_netlisttype) Verilog

set rda_Input(ui_ilmlist)

set rda_Input(ui_settop) 1

set rda_Input(ui_celllib)

set rda_Input(ui_iolib)

set rda_Input(ui_areaiolib)

set rda_Input(ui_blklib)

set rda_Input(ui_kboxlib)

set rda_Input(ui_timelib) cell_lib_filesscmetro_cms9flp-lvt_tt_1p2v_25clib

set rda_Input(ui_smodDef)

set rda_Input(ui_smodData)

set rda_Input(ui_dpath)

set rda_Input(ui_tech_file)

set rda_Input(ui_buf_footprint) BUFX2MTH

set rda_Input(ui_delay_footprint) BUFX2MTH

set rda_Input(ui_inv_footprint) INVX1MTH

set rda_Input(ui_leffile) cell_lib_fileslefcms9flp_8lm_2thick_techlef cell_lib_fileslefcms9flplvt_m_macroslef

set rda_Input(ui_core_cntl) aspect

set rda_Input(ui_aspect_ratio) 10

set rda_Input(ui_core_util) 07

set rda_Input(ui_core_height)

set rda_Input(ui_core_width)

set rda_Input(ui_core_to_left) 30

set rda_Input(ui_core_to_right) 30

set rda_Input(ui_core_to_top) 30set rda_Input(ui_core_to_bottom) 30

set rda_Input(ui_max_io_height) 0

set rda_Input(ui_row_height)

set rda_Input(ui_isHorTrackHalfPitch) 0

set rda_Input(ui_isVerTrackHalfPitch) 1

set rda_Input(ui_ioOri) R180

set rda_Input(ui_isOrigCenter) 0

set rda_Input(ui_exc_net)

set rda_Input(ui_delay_limit) 1000

set rda_Input(ui_net_delay) 10000ps

set rda_Input(ui_net_load) 05pf

set rda_Input(ui_in_tran_delay) 1200ps

set rda_Input(ui_captbl_file)

set rda_Input(ui_cap_scale) 10

set rda_Input(ui_xcap_scale) 10

set rda_Input(ui_res_scale) 10

set rda_Input(ui_shr_scale) 10set rda_Input(ui_time_unit) none

set rda_Input(ui_cap_unit)

set rda_Input(ui_sigstormlib)

set rda_Input(ui_cdb_file)

set rda_Input(ui_echo_file)

set rda_Input(ui_qxtech_file)

set rda_Input(ui_qxlib_file)

set rda_Input(ui_qxconf_file)

set rda_Input(ui_pwrnet) VDD

set rda_Input(ui_gndnet) VSS

set rda_Input(flip_first) 1

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set rda_Input(double_back) 1

set rda_Input(assign_buffer) 0

set rda_Input(ui_pg_connections) [list

PINVDD

PINVSS

]

set rda_Input(PINVDD) VDD

set rda_Input(PINVSS) VSS

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983105983120983120983109983118983108983113983128 983108 991251 983123983161983150983156983144983141983155983145983155 983107983151983150983142983145983143983157983154983137983156983145983151983150 983107983151983140983141

synopsys synthesis script

set hdlin_auto_save_templates true

set hdlin_check_no_latch true

set hdlin_warn_sens_list true

define_name_rules MYrules -map [ _ ] _

read_verilog verilog_inputoutv

current_design mips_pipeline_testbench

link

constraints are below

erase all attributes and constrains from the current design

reset_design

set wire loading mode to top

set_wire_load_mode top

Create clock with 5ns period

create_clock clk -name clk -period 5

change_names -rules MYrules -hierarchy

Compile with completely disolved design

compile -ungroup_all

Make sure we are at the top level

set current_design mips_pipeline_testbench

Generate area and constraints reports on the optimized design

report_area gt reportsarearpt

Generate timing report for worst case path

report_timing gt reportsdelayrpt

report_clock gt reportsclockrpt

Save the compiled design

write -format verilog -hierarchy -output synthesized_verilogpipeline_testbenchgatev

write_sdc synthesized_verilogpipeline_testbenchsdc

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CPU and the current_design parameter serves as the entry point overview file of that

hierarchy We ran Design Vision many many times before discovering this error

After synthesizing our CPU we ran into a third major pitfall when trying to time

the synthesized CPU in Design Vision We began synthesis by using the pipelined

testbench which contained a clock but did not have a clock as input When using the

testbench Design Vision said we had no clock and we couldnrsquot time our CPU We had

to have an output Y and input A then set them equal to each other on the posedge of the

clock along with running our MIPS pipeline module and with no reset signal For

whatever reason these changes added a clock to our synthesis and we could time the

pipelined CPU

After synthesizing we were able to move on to the on-die representation phase

where we encountered only minor easily remedied issues such as forgetting to check or

uncheck a dialog box entry etc All these issues were quickly taking care of by re-

reading the online tutorial

983123983145983149983157983148983137983156983141983140 983108983141983148983137983161

Following is the report created by Design Vision on simulated delay

Report timing

-path full-delay max-max_paths 1

Design mips_pipeline_testbenchVersion X-200509-SP2Date Fri Dec 12 142903 2008

A fanout number of 1000 was used for high fanout net computations

Operating Conditions tt_1p2v_25c Library scmetro_cms9flp-lvt_tt_1p2v_25cWire Load Model Mode top

Startpoint dutWB_MemtoReg_reg(rising edge-triggered flip-flop clocked by clk)

Endpoint dutMEM_Zero_reg(rising edge-triggered flip-flop clocked by clk)

Path Group clk

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Path Type max

Point Incr Path--------------------------------------------------------------------------clock clk (rise edge) 000 000clock network delay (ideal) 000 000dutWB_MemtoReg_regCK (DFFTRX1MTH) 000 000 rdutWB_MemtoReg_regQ (DFFTRX1MTH) 017 017 f

U335Y (BUFX2MTH) 016 033 fU970Y (AO22X2MTH) 017 049 fU258Y (BUFX4MTH) 008 057 fU282Y (AOI22X1MTH) 007 064 rU278Y (OAI2BB1X2MTH) 004 067 fU268Y (AO22X2MTH) 015 082 fdutEX_ALUadd_145U1_2CO (ADDFX2MTH) 023 105 fdutEX_ALUadd_145U1_3CO (ADDFX2MTH) 013 118 fdutEX_ALUadd_145U1_4CO (ADDFX2MTH) 013 131 fdutEX_ALUadd_145U1_5CO (ADDFX2MTH) 013 143 fdutEX_ALUadd_145U1_6CO (ADDFX2MTH) 013 156 fdutEX_ALUadd_145U1_7CO (ADDFX2MTH) 013 168 fdutEX_ALUadd_145U1_8CO (ADDFX2MTH) 013 181 fdutEX_ALUadd_145U1_9CO (ADDFX2MTH) 013 194 fdutEX_ALUadd_145U1_10CO (ADDFX2MTH) 013 206 fdutEX_ALUadd_145U1_11CO (ADDFX2MTH) 013 219 fdutEX_ALUadd_145U1_12CO (ADDFX2MTH) 013 232 f

dutEX_ALUadd_145U1_13CO (ADDFX2MTH) 013 244 fdutEX_ALUadd_145U1_14CO (ADDFX2MTH) 013 257 fdutEX_ALUadd_145U1_15CO (ADDFX2MTH) 013 270 fdutEX_ALUadd_145U1_16CO (ADDFX2MTH) 013 282 fdutEX_ALUadd_145U1_17CO (ADDFX2MTH) 013 295 fdutEX_ALUadd_145U1_18CO (ADDFX2MTH) 013 308 fdutEX_ALUadd_145U1_19CO (ADDFX2MTH) 013 320 fdutEX_ALUadd_145U1_20CO (ADDFX2MTH) 013 333 fdutEX_ALUadd_145U1_21CO (ADDFX2MTH) 013 346 fdutEX_ALUadd_145U1_22CO (ADDFX2MTH) 013 358 fdutEX_ALUadd_145U1_23CO (ADDFX2MTH) 013 371 fdutEX_ALUadd_145U1_24CO (ADDFX2MTH) 013 384 fdutEX_ALUadd_145U1_25CO (ADDFX2MTH) 013 396 fdutEX_ALUadd_145U1_26CO (ADDFX2MTH) 013 409 fdutEX_ALUadd_145U1_27CO (ADDFX2MTH) 014 423 fU272Y (NAND2X1MTH) 004 427 rU267Y (NAND3X2MTH) 005 432 f

dutEX_ALUadd_145U1_29CO (ADDFX2MTH) 012 444 fdutEX_ALUadd_145U1_30CO (ADDFX2MTH) 012 457 fdutEX_ALUadd_145U1_31Y (XOR3X1MTH) 009 466 fU251Y (NAND2X1MTH) 004 469 rU252Y (OAI2B11X2MTH) 007 476 fU269Y (NOR2XLMTH) 006 482 rU259Y (NAND2XLMTH) 004 486 fU289Y (NOR2X1MTH) 004 490 rdutMEM_Zero_regD (DFFTRX1MTH) 000 490 rdata arrival time 490

clock clk (rise edge) 500 500clock network delay (ideal) 000 500dutMEM_Zero_regCK (DFFTRX1MTH) 000 500 rlibrary setup time -009 491data required time 491--------------------------------------------------------------------------

data required time 491data arrival time -490--------------------------------------------------------------------------slack (MET) 001

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983105983120983120983109983118983108983113983128 983105 991251 983123983161983150983156983144983141983155983145983162983141983140 983111983137983156983141 983116983141983158983141983148 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125

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983105983120983120983109983118983108983113983128 983106 991251 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125 983119983150983085983108983145983141 983122983141983152983154983141983155983141983150983156983137983156983145983151983150

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983105983120983120983109983118983108983113983128 983107 991251 983109983150983139983151983157983150983156983141983154 983107983151983150983142983145983143983157983154983137983156983145983151983150 983110983145983148983141

SOC Encounter Input configuration file

global rda_Input

set rda_Input(ui_netlist) synthesized_verilogpipeline_testbenchgatev

set rda_Input(ui_timingcon_file) synthesized_verilogpipeline_testbenchsdc

set rda_Input(ui_topcell) mips_pipeline_testbench

set rda_Input(ui_netlisttype) Verilog

set rda_Input(ui_ilmlist)

set rda_Input(ui_settop) 1

set rda_Input(ui_celllib)

set rda_Input(ui_iolib)

set rda_Input(ui_areaiolib)

set rda_Input(ui_blklib)

set rda_Input(ui_kboxlib)

set rda_Input(ui_timelib) cell_lib_filesscmetro_cms9flp-lvt_tt_1p2v_25clib

set rda_Input(ui_smodDef)

set rda_Input(ui_smodData)

set rda_Input(ui_dpath)

set rda_Input(ui_tech_file)

set rda_Input(ui_buf_footprint) BUFX2MTH

set rda_Input(ui_delay_footprint) BUFX2MTH

set rda_Input(ui_inv_footprint) INVX1MTH

set rda_Input(ui_leffile) cell_lib_fileslefcms9flp_8lm_2thick_techlef cell_lib_fileslefcms9flplvt_m_macroslef

set rda_Input(ui_core_cntl) aspect

set rda_Input(ui_aspect_ratio) 10

set rda_Input(ui_core_util) 07

set rda_Input(ui_core_height)

set rda_Input(ui_core_width)

set rda_Input(ui_core_to_left) 30

set rda_Input(ui_core_to_right) 30

set rda_Input(ui_core_to_top) 30set rda_Input(ui_core_to_bottom) 30

set rda_Input(ui_max_io_height) 0

set rda_Input(ui_row_height)

set rda_Input(ui_isHorTrackHalfPitch) 0

set rda_Input(ui_isVerTrackHalfPitch) 1

set rda_Input(ui_ioOri) R180

set rda_Input(ui_isOrigCenter) 0

set rda_Input(ui_exc_net)

set rda_Input(ui_delay_limit) 1000

set rda_Input(ui_net_delay) 10000ps

set rda_Input(ui_net_load) 05pf

set rda_Input(ui_in_tran_delay) 1200ps

set rda_Input(ui_captbl_file)

set rda_Input(ui_cap_scale) 10

set rda_Input(ui_xcap_scale) 10

set rda_Input(ui_res_scale) 10

set rda_Input(ui_shr_scale) 10set rda_Input(ui_time_unit) none

set rda_Input(ui_cap_unit)

set rda_Input(ui_sigstormlib)

set rda_Input(ui_cdb_file)

set rda_Input(ui_echo_file)

set rda_Input(ui_qxtech_file)

set rda_Input(ui_qxlib_file)

set rda_Input(ui_qxconf_file)

set rda_Input(ui_pwrnet) VDD

set rda_Input(ui_gndnet) VSS

set rda_Input(flip_first) 1

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set rda_Input(double_back) 1

set rda_Input(assign_buffer) 0

set rda_Input(ui_pg_connections) [list

PINVDD

PINVSS

]

set rda_Input(PINVDD) VDD

set rda_Input(PINVSS) VSS

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983105983120983120983109983118983108983113983128 983108 991251 983123983161983150983156983144983141983155983145983155 983107983151983150983142983145983143983157983154983137983156983145983151983150 983107983151983140983141

synopsys synthesis script

set hdlin_auto_save_templates true

set hdlin_check_no_latch true

set hdlin_warn_sens_list true

define_name_rules MYrules -map [ _ ] _

read_verilog verilog_inputoutv

current_design mips_pipeline_testbench

link

constraints are below

erase all attributes and constrains from the current design

reset_design

set wire loading mode to top

set_wire_load_mode top

Create clock with 5ns period

create_clock clk -name clk -period 5

change_names -rules MYrules -hierarchy

Compile with completely disolved design

compile -ungroup_all

Make sure we are at the top level

set current_design mips_pipeline_testbench

Generate area and constraints reports on the optimized design

report_area gt reportsarearpt

Generate timing report for worst case path

report_timing gt reportsdelayrpt

report_clock gt reportsclockrpt

Save the compiled design

write -format verilog -hierarchy -output synthesized_verilogpipeline_testbenchgatev

write_sdc synthesized_verilogpipeline_testbenchsdc

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Path Type max

Point Incr Path--------------------------------------------------------------------------clock clk (rise edge) 000 000clock network delay (ideal) 000 000dutWB_MemtoReg_regCK (DFFTRX1MTH) 000 000 rdutWB_MemtoReg_regQ (DFFTRX1MTH) 017 017 f

U335Y (BUFX2MTH) 016 033 fU970Y (AO22X2MTH) 017 049 fU258Y (BUFX4MTH) 008 057 fU282Y (AOI22X1MTH) 007 064 rU278Y (OAI2BB1X2MTH) 004 067 fU268Y (AO22X2MTH) 015 082 fdutEX_ALUadd_145U1_2CO (ADDFX2MTH) 023 105 fdutEX_ALUadd_145U1_3CO (ADDFX2MTH) 013 118 fdutEX_ALUadd_145U1_4CO (ADDFX2MTH) 013 131 fdutEX_ALUadd_145U1_5CO (ADDFX2MTH) 013 143 fdutEX_ALUadd_145U1_6CO (ADDFX2MTH) 013 156 fdutEX_ALUadd_145U1_7CO (ADDFX2MTH) 013 168 fdutEX_ALUadd_145U1_8CO (ADDFX2MTH) 013 181 fdutEX_ALUadd_145U1_9CO (ADDFX2MTH) 013 194 fdutEX_ALUadd_145U1_10CO (ADDFX2MTH) 013 206 fdutEX_ALUadd_145U1_11CO (ADDFX2MTH) 013 219 fdutEX_ALUadd_145U1_12CO (ADDFX2MTH) 013 232 f

dutEX_ALUadd_145U1_13CO (ADDFX2MTH) 013 244 fdutEX_ALUadd_145U1_14CO (ADDFX2MTH) 013 257 fdutEX_ALUadd_145U1_15CO (ADDFX2MTH) 013 270 fdutEX_ALUadd_145U1_16CO (ADDFX2MTH) 013 282 fdutEX_ALUadd_145U1_17CO (ADDFX2MTH) 013 295 fdutEX_ALUadd_145U1_18CO (ADDFX2MTH) 013 308 fdutEX_ALUadd_145U1_19CO (ADDFX2MTH) 013 320 fdutEX_ALUadd_145U1_20CO (ADDFX2MTH) 013 333 fdutEX_ALUadd_145U1_21CO (ADDFX2MTH) 013 346 fdutEX_ALUadd_145U1_22CO (ADDFX2MTH) 013 358 fdutEX_ALUadd_145U1_23CO (ADDFX2MTH) 013 371 fdutEX_ALUadd_145U1_24CO (ADDFX2MTH) 013 384 fdutEX_ALUadd_145U1_25CO (ADDFX2MTH) 013 396 fdutEX_ALUadd_145U1_26CO (ADDFX2MTH) 013 409 fdutEX_ALUadd_145U1_27CO (ADDFX2MTH) 014 423 fU272Y (NAND2X1MTH) 004 427 rU267Y (NAND3X2MTH) 005 432 f

dutEX_ALUadd_145U1_29CO (ADDFX2MTH) 012 444 fdutEX_ALUadd_145U1_30CO (ADDFX2MTH) 012 457 fdutEX_ALUadd_145U1_31Y (XOR3X1MTH) 009 466 fU251Y (NAND2X1MTH) 004 469 rU252Y (OAI2B11X2MTH) 007 476 fU269Y (NOR2XLMTH) 006 482 rU259Y (NAND2XLMTH) 004 486 fU289Y (NOR2X1MTH) 004 490 rdutMEM_Zero_regD (DFFTRX1MTH) 000 490 rdata arrival time 490

clock clk (rise edge) 500 500clock network delay (ideal) 000 500dutMEM_Zero_regCK (DFFTRX1MTH) 000 500 rlibrary setup time -009 491data required time 491--------------------------------------------------------------------------

data required time 491data arrival time -490--------------------------------------------------------------------------slack (MET) 001

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983105983120983120983109983118983108983113983128 983105 991251 983123983161983150983156983144983141983155983145983162983141983140 983111983137983156983141 983116983141983158983141983148 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125

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983105983120983120983109983118983108983113983128 983106 991251 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125 983119983150983085983108983145983141 983122983141983152983154983141983155983141983150983156983137983156983145983151983150

7222019 Extra Project hhhh

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983105983120983120983109983118983108983113983128 983107 991251 983109983150983139983151983157983150983156983141983154 983107983151983150983142983145983143983157983154983137983156983145983151983150 983110983145983148983141

SOC Encounter Input configuration file

global rda_Input

set rda_Input(ui_netlist) synthesized_verilogpipeline_testbenchgatev

set rda_Input(ui_timingcon_file) synthesized_verilogpipeline_testbenchsdc

set rda_Input(ui_topcell) mips_pipeline_testbench

set rda_Input(ui_netlisttype) Verilog

set rda_Input(ui_ilmlist)

set rda_Input(ui_settop) 1

set rda_Input(ui_celllib)

set rda_Input(ui_iolib)

set rda_Input(ui_areaiolib)

set rda_Input(ui_blklib)

set rda_Input(ui_kboxlib)

set rda_Input(ui_timelib) cell_lib_filesscmetro_cms9flp-lvt_tt_1p2v_25clib

set rda_Input(ui_smodDef)

set rda_Input(ui_smodData)

set rda_Input(ui_dpath)

set rda_Input(ui_tech_file)

set rda_Input(ui_buf_footprint) BUFX2MTH

set rda_Input(ui_delay_footprint) BUFX2MTH

set rda_Input(ui_inv_footprint) INVX1MTH

set rda_Input(ui_leffile) cell_lib_fileslefcms9flp_8lm_2thick_techlef cell_lib_fileslefcms9flplvt_m_macroslef

set rda_Input(ui_core_cntl) aspect

set rda_Input(ui_aspect_ratio) 10

set rda_Input(ui_core_util) 07

set rda_Input(ui_core_height)

set rda_Input(ui_core_width)

set rda_Input(ui_core_to_left) 30

set rda_Input(ui_core_to_right) 30

set rda_Input(ui_core_to_top) 30set rda_Input(ui_core_to_bottom) 30

set rda_Input(ui_max_io_height) 0

set rda_Input(ui_row_height)

set rda_Input(ui_isHorTrackHalfPitch) 0

set rda_Input(ui_isVerTrackHalfPitch) 1

set rda_Input(ui_ioOri) R180

set rda_Input(ui_isOrigCenter) 0

set rda_Input(ui_exc_net)

set rda_Input(ui_delay_limit) 1000

set rda_Input(ui_net_delay) 10000ps

set rda_Input(ui_net_load) 05pf

set rda_Input(ui_in_tran_delay) 1200ps

set rda_Input(ui_captbl_file)

set rda_Input(ui_cap_scale) 10

set rda_Input(ui_xcap_scale) 10

set rda_Input(ui_res_scale) 10

set rda_Input(ui_shr_scale) 10set rda_Input(ui_time_unit) none

set rda_Input(ui_cap_unit)

set rda_Input(ui_sigstormlib)

set rda_Input(ui_cdb_file)

set rda_Input(ui_echo_file)

set rda_Input(ui_qxtech_file)

set rda_Input(ui_qxlib_file)

set rda_Input(ui_qxconf_file)

set rda_Input(ui_pwrnet) VDD

set rda_Input(ui_gndnet) VSS

set rda_Input(flip_first) 1

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set rda_Input(double_back) 1

set rda_Input(assign_buffer) 0

set rda_Input(ui_pg_connections) [list

PINVDD

PINVSS

]

set rda_Input(PINVDD) VDD

set rda_Input(PINVSS) VSS

7222019 Extra Project hhhh

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983105983120983120983109983118983108983113983128 983108 991251 983123983161983150983156983144983141983155983145983155 983107983151983150983142983145983143983157983154983137983156983145983151983150 983107983151983140983141

synopsys synthesis script

set hdlin_auto_save_templates true

set hdlin_check_no_latch true

set hdlin_warn_sens_list true

define_name_rules MYrules -map [ _ ] _

read_verilog verilog_inputoutv

current_design mips_pipeline_testbench

link

constraints are below

erase all attributes and constrains from the current design

reset_design

set wire loading mode to top

set_wire_load_mode top

Create clock with 5ns period

create_clock clk -name clk -period 5

change_names -rules MYrules -hierarchy

Compile with completely disolved design

compile -ungroup_all

Make sure we are at the top level

set current_design mips_pipeline_testbench

Generate area and constraints reports on the optimized design

report_area gt reportsarearpt

Generate timing report for worst case path

report_timing gt reportsdelayrpt

report_clock gt reportsclockrpt

Save the compiled design

write -format verilog -hierarchy -output synthesized_verilogpipeline_testbenchgatev

write_sdc synthesized_verilogpipeline_testbenchsdc

7222019 Extra Project hhhh

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11

983105983120983120983109983118983108983113983128 983105 991251 983123983161983150983156983144983141983155983145983162983141983140 983111983137983156983141 983116983141983158983141983148 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 1215

12

983105983120983120983109983118983108983113983128 983106 991251 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125 983119983150983085983108983145983141 983122983141983152983154983141983155983141983150983156983137983156983145983151983150

7222019 Extra Project hhhh

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13

983105983120983120983109983118983108983113983128 983107 991251 983109983150983139983151983157983150983156983141983154 983107983151983150983142983145983143983157983154983137983156983145983151983150 983110983145983148983141

SOC Encounter Input configuration file

global rda_Input

set rda_Input(ui_netlist) synthesized_verilogpipeline_testbenchgatev

set rda_Input(ui_timingcon_file) synthesized_verilogpipeline_testbenchsdc

set rda_Input(ui_topcell) mips_pipeline_testbench

set rda_Input(ui_netlisttype) Verilog

set rda_Input(ui_ilmlist)

set rda_Input(ui_settop) 1

set rda_Input(ui_celllib)

set rda_Input(ui_iolib)

set rda_Input(ui_areaiolib)

set rda_Input(ui_blklib)

set rda_Input(ui_kboxlib)

set rda_Input(ui_timelib) cell_lib_filesscmetro_cms9flp-lvt_tt_1p2v_25clib

set rda_Input(ui_smodDef)

set rda_Input(ui_smodData)

set rda_Input(ui_dpath)

set rda_Input(ui_tech_file)

set rda_Input(ui_buf_footprint) BUFX2MTH

set rda_Input(ui_delay_footprint) BUFX2MTH

set rda_Input(ui_inv_footprint) INVX1MTH

set rda_Input(ui_leffile) cell_lib_fileslefcms9flp_8lm_2thick_techlef cell_lib_fileslefcms9flplvt_m_macroslef

set rda_Input(ui_core_cntl) aspect

set rda_Input(ui_aspect_ratio) 10

set rda_Input(ui_core_util) 07

set rda_Input(ui_core_height)

set rda_Input(ui_core_width)

set rda_Input(ui_core_to_left) 30

set rda_Input(ui_core_to_right) 30

set rda_Input(ui_core_to_top) 30set rda_Input(ui_core_to_bottom) 30

set rda_Input(ui_max_io_height) 0

set rda_Input(ui_row_height)

set rda_Input(ui_isHorTrackHalfPitch) 0

set rda_Input(ui_isVerTrackHalfPitch) 1

set rda_Input(ui_ioOri) R180

set rda_Input(ui_isOrigCenter) 0

set rda_Input(ui_exc_net)

set rda_Input(ui_delay_limit) 1000

set rda_Input(ui_net_delay) 10000ps

set rda_Input(ui_net_load) 05pf

set rda_Input(ui_in_tran_delay) 1200ps

set rda_Input(ui_captbl_file)

set rda_Input(ui_cap_scale) 10

set rda_Input(ui_xcap_scale) 10

set rda_Input(ui_res_scale) 10

set rda_Input(ui_shr_scale) 10set rda_Input(ui_time_unit) none

set rda_Input(ui_cap_unit)

set rda_Input(ui_sigstormlib)

set rda_Input(ui_cdb_file)

set rda_Input(ui_echo_file)

set rda_Input(ui_qxtech_file)

set rda_Input(ui_qxlib_file)

set rda_Input(ui_qxconf_file)

set rda_Input(ui_pwrnet) VDD

set rda_Input(ui_gndnet) VSS

set rda_Input(flip_first) 1

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set rda_Input(double_back) 1

set rda_Input(assign_buffer) 0

set rda_Input(ui_pg_connections) [list

PINVDD

PINVSS

]

set rda_Input(PINVDD) VDD

set rda_Input(PINVSS) VSS

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 1515

983105983120983120983109983118983108983113983128 983108 991251 983123983161983150983156983144983141983155983145983155 983107983151983150983142983145983143983157983154983137983156983145983151983150 983107983151983140983141

synopsys synthesis script

set hdlin_auto_save_templates true

set hdlin_check_no_latch true

set hdlin_warn_sens_list true

define_name_rules MYrules -map [ _ ] _

read_verilog verilog_inputoutv

current_design mips_pipeline_testbench

link

constraints are below

erase all attributes and constrains from the current design

reset_design

set wire loading mode to top

set_wire_load_mode top

Create clock with 5ns period

create_clock clk -name clk -period 5

change_names -rules MYrules -hierarchy

Compile with completely disolved design

compile -ungroup_all

Make sure we are at the top level

set current_design mips_pipeline_testbench

Generate area and constraints reports on the optimized design

report_area gt reportsarearpt

Generate timing report for worst case path

report_timing gt reportsdelayrpt

report_clock gt reportsclockrpt

Save the compiled design

write -format verilog -hierarchy -output synthesized_verilogpipeline_testbenchgatev

write_sdc synthesized_verilogpipeline_testbenchsdc

7222019 Extra Project hhhh

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12

983105983120983120983109983118983108983113983128 983106 991251 983120983145983152983141983148983145983150983141983140 983117983113983120983123 983107983120983125 983119983150983085983108983145983141 983122983141983152983154983141983155983141983150983156983137983156983145983151983150

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 1315

13

983105983120983120983109983118983108983113983128 983107 991251 983109983150983139983151983157983150983156983141983154 983107983151983150983142983145983143983157983154983137983156983145983151983150 983110983145983148983141

SOC Encounter Input configuration file

global rda_Input

set rda_Input(ui_netlist) synthesized_verilogpipeline_testbenchgatev

set rda_Input(ui_timingcon_file) synthesized_verilogpipeline_testbenchsdc

set rda_Input(ui_topcell) mips_pipeline_testbench

set rda_Input(ui_netlisttype) Verilog

set rda_Input(ui_ilmlist)

set rda_Input(ui_settop) 1

set rda_Input(ui_celllib)

set rda_Input(ui_iolib)

set rda_Input(ui_areaiolib)

set rda_Input(ui_blklib)

set rda_Input(ui_kboxlib)

set rda_Input(ui_timelib) cell_lib_filesscmetro_cms9flp-lvt_tt_1p2v_25clib

set rda_Input(ui_smodDef)

set rda_Input(ui_smodData)

set rda_Input(ui_dpath)

set rda_Input(ui_tech_file)

set rda_Input(ui_buf_footprint) BUFX2MTH

set rda_Input(ui_delay_footprint) BUFX2MTH

set rda_Input(ui_inv_footprint) INVX1MTH

set rda_Input(ui_leffile) cell_lib_fileslefcms9flp_8lm_2thick_techlef cell_lib_fileslefcms9flplvt_m_macroslef

set rda_Input(ui_core_cntl) aspect

set rda_Input(ui_aspect_ratio) 10

set rda_Input(ui_core_util) 07

set rda_Input(ui_core_height)

set rda_Input(ui_core_width)

set rda_Input(ui_core_to_left) 30

set rda_Input(ui_core_to_right) 30

set rda_Input(ui_core_to_top) 30set rda_Input(ui_core_to_bottom) 30

set rda_Input(ui_max_io_height) 0

set rda_Input(ui_row_height)

set rda_Input(ui_isHorTrackHalfPitch) 0

set rda_Input(ui_isVerTrackHalfPitch) 1

set rda_Input(ui_ioOri) R180

set rda_Input(ui_isOrigCenter) 0

set rda_Input(ui_exc_net)

set rda_Input(ui_delay_limit) 1000

set rda_Input(ui_net_delay) 10000ps

set rda_Input(ui_net_load) 05pf

set rda_Input(ui_in_tran_delay) 1200ps

set rda_Input(ui_captbl_file)

set rda_Input(ui_cap_scale) 10

set rda_Input(ui_xcap_scale) 10

set rda_Input(ui_res_scale) 10

set rda_Input(ui_shr_scale) 10set rda_Input(ui_time_unit) none

set rda_Input(ui_cap_unit)

set rda_Input(ui_sigstormlib)

set rda_Input(ui_cdb_file)

set rda_Input(ui_echo_file)

set rda_Input(ui_qxtech_file)

set rda_Input(ui_qxlib_file)

set rda_Input(ui_qxconf_file)

set rda_Input(ui_pwrnet) VDD

set rda_Input(ui_gndnet) VSS

set rda_Input(flip_first) 1

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set rda_Input(double_back) 1

set rda_Input(assign_buffer) 0

set rda_Input(ui_pg_connections) [list

PINVDD

PINVSS

]

set rda_Input(PINVDD) VDD

set rda_Input(PINVSS) VSS

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 1515

983105983120983120983109983118983108983113983128 983108 991251 983123983161983150983156983144983141983155983145983155 983107983151983150983142983145983143983157983154983137983156983145983151983150 983107983151983140983141

synopsys synthesis script

set hdlin_auto_save_templates true

set hdlin_check_no_latch true

set hdlin_warn_sens_list true

define_name_rules MYrules -map [ _ ] _

read_verilog verilog_inputoutv

current_design mips_pipeline_testbench

link

constraints are below

erase all attributes and constrains from the current design

reset_design

set wire loading mode to top

set_wire_load_mode top

Create clock with 5ns period

create_clock clk -name clk -period 5

change_names -rules MYrules -hierarchy

Compile with completely disolved design

compile -ungroup_all

Make sure we are at the top level

set current_design mips_pipeline_testbench

Generate area and constraints reports on the optimized design

report_area gt reportsarearpt

Generate timing report for worst case path

report_timing gt reportsdelayrpt

report_clock gt reportsclockrpt

Save the compiled design

write -format verilog -hierarchy -output synthesized_verilogpipeline_testbenchgatev

write_sdc synthesized_verilogpipeline_testbenchsdc

7222019 Extra Project hhhh

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983105983120983120983109983118983108983113983128 983107 991251 983109983150983139983151983157983150983156983141983154 983107983151983150983142983145983143983157983154983137983156983145983151983150 983110983145983148983141

SOC Encounter Input configuration file

global rda_Input

set rda_Input(ui_netlist) synthesized_verilogpipeline_testbenchgatev

set rda_Input(ui_timingcon_file) synthesized_verilogpipeline_testbenchsdc

set rda_Input(ui_topcell) mips_pipeline_testbench

set rda_Input(ui_netlisttype) Verilog

set rda_Input(ui_ilmlist)

set rda_Input(ui_settop) 1

set rda_Input(ui_celllib)

set rda_Input(ui_iolib)

set rda_Input(ui_areaiolib)

set rda_Input(ui_blklib)

set rda_Input(ui_kboxlib)

set rda_Input(ui_timelib) cell_lib_filesscmetro_cms9flp-lvt_tt_1p2v_25clib

set rda_Input(ui_smodDef)

set rda_Input(ui_smodData)

set rda_Input(ui_dpath)

set rda_Input(ui_tech_file)

set rda_Input(ui_buf_footprint) BUFX2MTH

set rda_Input(ui_delay_footprint) BUFX2MTH

set rda_Input(ui_inv_footprint) INVX1MTH

set rda_Input(ui_leffile) cell_lib_fileslefcms9flp_8lm_2thick_techlef cell_lib_fileslefcms9flplvt_m_macroslef

set rda_Input(ui_core_cntl) aspect

set rda_Input(ui_aspect_ratio) 10

set rda_Input(ui_core_util) 07

set rda_Input(ui_core_height)

set rda_Input(ui_core_width)

set rda_Input(ui_core_to_left) 30

set rda_Input(ui_core_to_right) 30

set rda_Input(ui_core_to_top) 30set rda_Input(ui_core_to_bottom) 30

set rda_Input(ui_max_io_height) 0

set rda_Input(ui_row_height)

set rda_Input(ui_isHorTrackHalfPitch) 0

set rda_Input(ui_isVerTrackHalfPitch) 1

set rda_Input(ui_ioOri) R180

set rda_Input(ui_isOrigCenter) 0

set rda_Input(ui_exc_net)

set rda_Input(ui_delay_limit) 1000

set rda_Input(ui_net_delay) 10000ps

set rda_Input(ui_net_load) 05pf

set rda_Input(ui_in_tran_delay) 1200ps

set rda_Input(ui_captbl_file)

set rda_Input(ui_cap_scale) 10

set rda_Input(ui_xcap_scale) 10

set rda_Input(ui_res_scale) 10

set rda_Input(ui_shr_scale) 10set rda_Input(ui_time_unit) none

set rda_Input(ui_cap_unit)

set rda_Input(ui_sigstormlib)

set rda_Input(ui_cdb_file)

set rda_Input(ui_echo_file)

set rda_Input(ui_qxtech_file)

set rda_Input(ui_qxlib_file)

set rda_Input(ui_qxconf_file)

set rda_Input(ui_pwrnet) VDD

set rda_Input(ui_gndnet) VSS

set rda_Input(flip_first) 1

7222019 Extra Project hhhh

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set rda_Input(double_back) 1

set rda_Input(assign_buffer) 0

set rda_Input(ui_pg_connections) [list

PINVDD

PINVSS

]

set rda_Input(PINVDD) VDD

set rda_Input(PINVSS) VSS

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 1515

983105983120983120983109983118983108983113983128 983108 991251 983123983161983150983156983144983141983155983145983155 983107983151983150983142983145983143983157983154983137983156983145983151983150 983107983151983140983141

synopsys synthesis script

set hdlin_auto_save_templates true

set hdlin_check_no_latch true

set hdlin_warn_sens_list true

define_name_rules MYrules -map [ _ ] _

read_verilog verilog_inputoutv

current_design mips_pipeline_testbench

link

constraints are below

erase all attributes and constrains from the current design

reset_design

set wire loading mode to top

set_wire_load_mode top

Create clock with 5ns period

create_clock clk -name clk -period 5

change_names -rules MYrules -hierarchy

Compile with completely disolved design

compile -ungroup_all

Make sure we are at the top level

set current_design mips_pipeline_testbench

Generate area and constraints reports on the optimized design

report_area gt reportsarearpt

Generate timing report for worst case path

report_timing gt reportsdelayrpt

report_clock gt reportsclockrpt

Save the compiled design

write -format verilog -hierarchy -output synthesized_verilogpipeline_testbenchgatev

write_sdc synthesized_verilogpipeline_testbenchsdc

7222019 Extra Project hhhh

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set rda_Input(double_back) 1

set rda_Input(assign_buffer) 0

set rda_Input(ui_pg_connections) [list

PINVDD

PINVSS

]

set rda_Input(PINVDD) VDD

set rda_Input(PINVSS) VSS

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 1515

983105983120983120983109983118983108983113983128 983108 991251 983123983161983150983156983144983141983155983145983155 983107983151983150983142983145983143983157983154983137983156983145983151983150 983107983151983140983141

synopsys synthesis script

set hdlin_auto_save_templates true

set hdlin_check_no_latch true

set hdlin_warn_sens_list true

define_name_rules MYrules -map [ _ ] _

read_verilog verilog_inputoutv

current_design mips_pipeline_testbench

link

constraints are below

erase all attributes and constrains from the current design

reset_design

set wire loading mode to top

set_wire_load_mode top

Create clock with 5ns period

create_clock clk -name clk -period 5

change_names -rules MYrules -hierarchy

Compile with completely disolved design

compile -ungroup_all

Make sure we are at the top level

set current_design mips_pipeline_testbench

Generate area and constraints reports on the optimized design

report_area gt reportsarearpt

Generate timing report for worst case path

report_timing gt reportsdelayrpt

report_clock gt reportsclockrpt

Save the compiled design

write -format verilog -hierarchy -output synthesized_verilogpipeline_testbenchgatev

write_sdc synthesized_verilogpipeline_testbenchsdc

7222019 Extra Project hhhh

httpslidepdfcomreaderfullextra-project-hhhh 1515

983105983120983120983109983118983108983113983128 983108 991251 983123983161983150983156983144983141983155983145983155 983107983151983150983142983145983143983157983154983137983156983145983151983150 983107983151983140983141

synopsys synthesis script

set hdlin_auto_save_templates true

set hdlin_check_no_latch true

set hdlin_warn_sens_list true

define_name_rules MYrules -map [ _ ] _

read_verilog verilog_inputoutv

current_design mips_pipeline_testbench

link

constraints are below

erase all attributes and constrains from the current design

reset_design

set wire loading mode to top

set_wire_load_mode top

Create clock with 5ns period

create_clock clk -name clk -period 5

change_names -rules MYrules -hierarchy

Compile with completely disolved design

compile -ungroup_all

Make sure we are at the top level

set current_design mips_pipeline_testbench

Generate area and constraints reports on the optimized design

report_area gt reportsarearpt

Generate timing report for worst case path

report_timing gt reportsdelayrpt

report_clock gt reportsclockrpt

Save the compiled design

write -format verilog -hierarchy -output synthesized_verilogpipeline_testbenchgatev

write_sdc synthesized_verilogpipeline_testbenchsdc