Concurrently held event:

　　　　 　　　　

Opening a New Chapter: Design Evolution Never Stops

Exhibition Report

Date： Wednesday, November 16 - Friday, November 18, 2011Place： Pacifico YokohamaOrganizer： Japan Electronics and Information Technology Industries Association

　　　　

www.edsfair.com/e

1

1. Exhibition Outline 2

2. EDSFair2011 Nov. Overview 3

3. Opening Event 4

4. Exhibition Configuration 5

5. Floor Map 6

6. Exhibitors 7

7. Conferences／Seminars 9

8. Special Program 11

9. Number and Profile of Visitors 12

10. PR Activities 17

11. Official Website 19

Contents

2

■ Name Electronic Design and Solution Fair 2011 November（EDSFair2011 Nov.）

■ Concurrently held event Embedded Technology 2011

■ Date Wednesday, November 16, 2011 to Friday, January 18, 2011 (3days)

■ Time Wednesday, November 16 : 10:00 a.m. to 5:00 p.m.

Thursday, November 17 : 10:00 a.m. to 6:00 p.m. ( 5:00p.m. to 6:00 p.m. Happy Hour)

Friday, November 18 : 10:00 a.m. to 5:00 p.m.

■ Place Pacifico Yokohama Exhibition Hall, Annex Hal l and Conference Center

■ Admission Registration required

○Visitor registration at the Gate : ¥1,000

○Online pre-registration/Invitational registration at the Gate : Free

■ Organizer Japan Electronics and Information Technology Industries Association (JEITA)

■ Cooperation Electronic Design Automation Consortium (EDAC)

■ Support Ministry of Economy, Trade and Industry, United States Embassy of Japan

Distributor’s Association of Foreign Semiconductors (DAFS), Yokohama City

■ Assistance Japan Embedded Systems Technology Association (JASA),

Institute of Electronics, Information and Communication Engineers (IEICE),

Information Processing Society of Japan (IPSJ),

Japan Electronics Packaging and Circuits Association (JPCA)

■ Management Japan Electronics Show Association (JESA)

12F Ote Center Bldg., 1-1-3, Otemachi, Chiyoda-ku, Tokyo 100-0004, Japan

Tel: +81-3-6212-5231 FAX: +81-3-6212-5225

1. Exhibition Outline

3

Sponsored by the Japan Electronics and Information Technology Industries Association (JEITA), the

Electronic Design and Solution Fair 2011 (EDSFair2011 Nov.) was held from November 16th to

November 18th , 2011 at Pacifico Yokohama in Japan.

Now in its 12th year, this exhibition was held simultaneously with Embedded Technology aimed to further

develop the exhibition for the common goal of maximizing that the integration of systems design,

software development, semiconductor (hardware) development is essential and to promote expansion in

these fields that the EDSFair, which is a technology exhibition in the field of hardware development and

ET, which is a technology exhibition in the fields of systems development and software development.

Though EDSFair was held two times, Januany and November 2011, a year due to currently held with ET,

a total of 80 exhibiting companies and organizations opened 109 booths and attracted 6,189 visitors,

exclude visitors registered in ET and visited EDSFair, in the 3 days as a unique exhibition that collects

together optimal technologies and solutions to capture fresh new areas of application, from device

development to systems design and software development.

On the second day, Thursday 17th, EDSFair×ET Special Collaborating Session; “Advanced virtual

system development and SW development solution changing the world. -Seamlessly integrate

SW/system/semiconductor development-”, and attracted 242 audiences who listened earnestly to learn

current situation/challenge in system/SW development arena, and also learn solution for them through

speech and talk session by system / SW developers and solution providers. In addition, 93 exhibitors’

seminars which enabled visitors to learn the latest technologies’ trend were held and attracted 1,754

audiences in total for 3 days.

Also at the Special Stage, the open session introduced new technology treads being discussed at

prestigious academy in EDA field, a session included the sequel of the LPB session held at last EDSFair

in January to deliver case study and discussed how to apply them and the third time of the Designers'

Session which has been well-received and became popular at EDSFair were held and attracted 335

audience along with System Design Forum 2011 which featured the latest EDA technology on the

session were held and offered opportunities to find best practice in the industry valuable for design

engineers and project managers.

The Special Zone also showcased topics and the latest in technologies of interest to engineers, which

were divided into the following three sectors: the Emerging Company Area offered solutions presented

by new venture companies worldwide; the University Plaza provided a venue where universities

presented R&D achievements to encourage technological exchanges between industry, academia, and

government; and the JEVeC Village was where domestic venture EDA developers gathered to promote

technologies and products utilizing the Monozukuri potential of Japanese corporations.

At the 5th Emerging Company Guided Tour, the tour guide introduced exhibitors’ technologies and

solutions which have less access to visitors and helped communications between visitors and exhibitors.

It provided a place to find new technologies and solution and attracted more than 50 tour participants not

only EDSFair visitors but also ET visitors in each tour.

Also "EDSFair Happy Hour" was held from 5 p.m. to 6 p.m. on Thursday, November 17 at the same time

as ET Festa. A number of related people attended this events and a place for exhibitors and visitors to

communicate was provided.

2. EDSFair2011 Nov. Overview

4

■ Opening Ceremony

The Opening Ceremony of EDSFair2011 Nov. and ET2011 was held at the gate of the Exhibition Hall 5 at

9:45 a.m. on Wednesday, November 16. The ceremony opened with congratulatory remarks from Minoru

Yanada, Chairman of Japan Embedded Systems Technology Association on behalf of the ET2011

organizer and Hisanori Tatae, Operating Officer of the Japan Electronics and Information Technology

Industries Association Executive Board then gave his greetings on behalf of the EDSFair2011 Nov.

organizer, and the aforementioned people along with Katsunori Watanabe, Director General Economic

Affairs Bureau, Yasuhiro Homma, Director Applied technology Group, Intel Architecture Technology

Group, Intel K.K., Toshihide Tsuboi, Senior Vice President, Renesas Electronics Corporation, Minoru

Yanada, Chairman, Japan Embedded Systems Technology Association (JASA), Masaru Fujiki, Vice

Chairman, Japan Embedded Systems Technology Association (JASA), Masaaki Yoshida, Chairman of

EDSFair2011 Nov.Excutive Committee, conducted the ribbon cutting.

3. Opening Event

5

■ Exhibits

●Hardware solutions： System LSI, ASIC/ASSP, MPU/MCU/DSP, FPGA/PLD and others

●Hardware development (EDA)：

IC design tools：

System level design (higher than RTL), Logic design (RTL to net list), Logic verification, Analog design/verification, Physical implementation, Physical verification/analysis, Signal integrity analysis, Test (DFT/BIST/ATPG/others), DFM (OPC/RET/PSM/LRC/ TCAD/others), ASIC Prototyping and others

PCB/SIP design tools：

Schematic capture, Analog design/verification, Layout, Signal Integrity/Power Integrity/EMC analysis, Electromagnetic field analysis, Thermal analysis and others

●Software solutions： Embedded OS, Device drivers, Firmware, Middleware, Virtual platform Development and others

●IC tester/analyzer ： IC testers, PCB testers, Analyzers and others

●IP core, Macro, Cell libraries

●Embedded processor development environments： Reconfigurable processors, ICE, Debuggers, Microcomputer CASE, Compilers/cross compliers, Simulators, Hardware/software co-design environments and others

●Design service-related (LSI/PCB)： Design houses, Design services, Design consulting, Prototyping/manufacturing, IP distribution services and others

●Design infrastructure (WS/PC, Network)

●Design data management tool： Design data management and others

●Mask shop, Foundry：

●University (R&D), Consortium：

●PR-related： Publications and others

■ Number and Profile of Exhibitors Exhibitors 80 companies・organizations／109 booths

4. Exhibition Configuration

6

Exhibits：Exhibition Hall D and part of C Hall

Conferences/Exhibitor Seminars：Conference Center 5F(503)/Annex Hall (F201)

Meeting Rooms 1F, M2F, 2F(D11,DM3,DM6,E205,E206,F201)

D Hall

5. Floor Map

7

*Joint participant company indented

■ Regular Area AET, INC.

Aldec-Japan K.K.

Applistar Corporation

The DINI Group

AT DESIGN LINKS CORPORATION

Accelicon Technologies, Inc.

ATE Service Corporation

ATopTech Co.,Ltd

Atrenta KK

AWR Japan

Berkeley Design Automation, Inc.

CALYPTO DESIGN SYSTEMS, K.K.

Carbon Design Systems Japan K.K.

CM Engineering Co., Ltd

CYBERNET SYSTEMS Co., Ltd.

CyberTec Inc.

Jasper Design Automation

Dorado Design Automation, Inc.

FORTE DESIGN SYSTEMS

FUJITSU LIMITED

GLOBALFOUNDRIES

IBIS QualityFramework EDA Standard WG

INNOTECH CORPORATION

Arteris Inc.

Calypto Design Systems, Inc.

Duolog Technologies Ltd.

Menta S.A.S.

KERNELON SILICON Incorporated

MoDeCH Inc.

Target Compiler Technologies N.V.

TowerJazz

(Tower Semiconductor Ltd. Jazz Semiconductor Inc.)

TranSwitch Corporation

IVIS Co., Ltd.

KANEMATSU ELECTRONICS LTD.

MENTOR GRAPHICS JAPAN CO., LTD.

MunEDA GmbH

NANGATE

Nihon EVE K.K.

Nihon Synopsys G.K.

NIMBIC, INC. （Formerly PHYSWARE INC)

ProPlus Design Solutions KK

Pulsic Japan Limited

Real Intent, Inc.

Semiconductor Technology Academic Research Center

SPRINGSOFT K.K.

Tanner Reserch Japan K.K.

■ Emerging Company Area A-R-Tec Corporation

Kobe University Nagata Lab.

Hiroshima University Yoshida Lab.

Blue Pearl Software, Inc.

CircuitSutra Technologies Pvt Ltd

DOCEA POWER

HD Lab

Japan Circuit Co.,Ltd.

Magillem Design Services

MathWorks Japan

Methodics, Inc.

Signal Process Logic Inc.

TERADYNE INC

6.Exhibitors

8

■ JEVeC VillageArtgraphics

ASTRON. Inc.

Gem Design Technologies, Inc.

Jedat Inc.

Keirex Technology Inc.

Trigence Semiconductor, Inc.

Mathematical Systems Inc.

PROTOtyping Japan Corp.

KAISemi, Inc.

CAST, Inc.

IRIS Technologies, Inc.

CreDist, Inc.

ASIP Solutions, Inc.

WIZnet Co. LTD.

TOOL CORPORATION

Euphonic Technologies, Inc.

■ University Plaza Graduate School of IPS, WASEDA Univ.

Higami and Takahashi Laboratory, Ehime University

Hiroshima University, Laboratory of Algorithm Engineering

Kyushu Institute of Technology, Nakamura Laboratory

Kajitani Laboratory The University of Kitakyushu, Departent of Media and Information Sciences

9

■ EDSFair×ET Special Collaborating Session Date：10am-12pm, Nov. 17 Thu, 2011

Venue：503, 5F Conference Center Fee：Free Number of

Audience

242

Title:

Advanced virtual system development and SW development solution changing the world.

-Seamlessly integrate SW/system/semiconductor development-

System and SW development is getting so complex and massive, and facing many tough challenges,

especially in Japanese major application such as mobile, consumer and automotive. On the other hand,

solution for those challenges is also evolving day by day. This session offered a great opportunity to learn

current situation/challenge in system/SW development arena, and also to learn solution for them through

speech and talk session by system / SW developers and solution providers.

Moderator ： Mr. Ikutaro Kojima Senior Editor, Tech-On!, Nikkei Business Publications, Inc. Panelists： Representative from EDA : Dr. Aart de Geus Chairman and CEO, Synopsys, Inc. Representative from SW development solution (IDE): Mr. Bob N. Ueyama Executive Vice President, eSOL Co., Ltd. Representative from consumer industry: Mr. Shigeo Suzuki Senior Staff Engineer, Software Platform Technology Development Div.2, CANON INC. Representative from consumer industry : Mr. Shigeru Kuroyanagi, General Manager, Automotive Software Engineering Div. TOYOTA MOTOR CORPORATION

7. Conferences／Seminars

10

■ Special Stage／System Design Forum 2011

Venue: F201 Annex Hall

Fee: Free

Audience: Special Stage: 268 total in 3 sessions／System Design Forum: 67

On Wednesday 16th, the open session introduced new technology treads being discussed at prestigious

academy in EDA field. Thursday 17th, it included the sequel of the LPB session held at last EDSFair in

January to deliver case study and discuss how to apply them. Also System Design Forum 2011 which featured

the latest EDA technology on the session was held.

This year was the third time of the Designers' Session on Friday 18th which has been well-received and

became popular at EDSFair, where you can find best practice in the industry valuable for design engineers

and project managers.

■ Exhibitors’ Seminars

Venue: Meeting rooms D11・DM3・DM6・E204・E205, Exhibition Hall / Meeting room F201, Annex Hall

Fee: Free

EDSFair2011 Nov. hosted exhibitor seminars for concentrated PR activities targeting limited number of 50 to

100 customers per 45-minute session. The Conference hosted

93 sessions in 6 rooms with 7 tracks by categories.

Track Session Audience

EE ESL track 30 395

EP Logic design＆Physical design／verification track 8 479

ED DFT/Functional verification/Design service track 21 219

EA AMS design・verification /PCB/SIP track 12 190

EL Low Power/IP/DFM track 12 175

EF Free track 7 185

ES Special track 3 111

Number of total Audiences 93 1,754

11

■ Special Zone 【Emerging Company Area】

13 Japanese and overseas venture companies brought together the latest information on solutions for speedy

uptake by designers and developers at an exhibition booth.

【JEVeC Village】

16 members companies of Japan EDA Venture Consortium came together for EDA development to promote

their technologies and products which utilizing the Monozukuri potential of Japanese corporations.

【University Plaza】

EDSFair offers an opportunity for university research institutes to present the results of their research projects

and to demonstrate achievements in R&D related to design technologies conducted at university institutions

while promoting increased collaboration between business and academia. In EDSFair2011 Nov., 5

universities presented demonstrations of achievements in R&D related to design technologies conducted at

university institutions.

■ Emrging Company Guided Tour The expert tour guides at design technology and EDA introduced participant companies’ key technologies in

Japanese at the main stage then visited their booth to support their presentation and questions and answers.

Tour Schedule

Nov. 16 [Wed.] 1st: 12:30-13:30 Nov. 18 [Fri.] 2nd: 12:30-13:40 ProPlus Design Solutions KK CM Engineering Co., Ltd Japan Circuit Co.,Ltd. Methodics, Inc. A-R-Tec Corporation

DOCEA POWER Blue Pearl Software, Inc. Magillem Design Services Circuit Sutra Technologies Pvt Ltd Signal Process Logic Inc. Art graphics

Tour Guide

Mr. Takashi Aikyo Director, Advanced Design & Test Technology IP & Technology Development and Manufacturing Unit Fujitsu Semiconductor Limited

Mr. Masami Murakata Chief Specialist, Design Technology Development Dept. Analog & Imaging IC Div. Toshiba Corporation Semiconductor & Storage Company

■ EDSFair Happy Hour

This year again, “EDSFair Happy Hour” was held on Thursday, November 17

from 17:00 to 18:00.

A number of visitors and exhibitors attended this event and made use of this

time as a place to have even deeper communication each other once a year.

8. Special Program

12

■ EDSFair2011 Nov. Number of Visitors

Nov.16 Nov.17 Nov.18 Total

EDSFair Visitors 1,489 2,360 2,340 6,189

ET Visitors 【FYR:Concurrently held event】

6,772 7,685 7,892 22,349

Total 8,261 10,045 10,232 28,538

(excluded visitors registered in ET and visited EDSFair)

Exhibitors : 80 companies and associations／Booths : 109 booths

【FYR Number of Visitors in the past】

Electronic Design and Solution Fair 2011 Nov. January

Jan.27 Jan 28 Total

EDSFair20Nov. Visitors 3,856 4,160 8,016

Exhibitors :Nov.8 companies and associations／Booths :199 booths

Electronic Design and Solution Fair 2010

Jan 28 Jan 29 Total

EDSFair2010 Visitors 4,288 5,012 9,300

Exhibitors :Nov.3 companies and associations／Booths :231 booths

■ Visitors’ Data

Type of Business

43.8%

26.1%

10.7%

8.6%

4.4%6.5%

Semiconductor and Electronic Component 43.8%Manufacturer 26.1%

Equipment Manufacturer 10.7%

Design and Related Service 8.6%

Tool Vendor 4.4%

Trading Company/Sale 6.5%

9. Number and Profile of Visitors

13

Breakdown of classification

Semiconductor and Electronic Component Manufacturer 43.8%

85.3%

1.3%

1.1%

1.0%

0.3%

2.7%

0.0% 10.0% 20.0% 30.0% 40.0% 50.0% 60.0% 70.0% 80.0% 90.0%

System LSI, ASIC, microcomputers, memories

FPGA/PLD

Printed circuit boards

Electronic components

FPGA/PLD

Other

Equipment Manufacturer 26.1%

22.6%

17.4%

14.7%

13.4%

7.7%

6.8%

6.4%

2.8%

1.3%

0.9%

1.6%

0.0% 5.0% 10.0% 15.0% 20.0% 25.0%

Computer‐related equipment

Industrial Equipment

General consumer electronics

Image‐processing equipment

Automobiles and transportation  equipment

Communication Equipment

Network‐related equipment

Medical equipment

Amusement

Broadcasting Equipment

Other

Design and Related Service 10.7%

41.7%

32.3%

10.9%

4.7%

0.5%

9.9%

0.0% 5.0% 10.0% 15.0% 20.0% 25.0% 30.0% 35.0% 40.0% 45.0%

Design house

Software development

Education/Consulting

IP provider

Network environment

Other

Tool Vender 8.6%

51.6%

17.4%

15.5%

2.6%

0.6%

12.3%

0.0% 10.0% 20.0% 30.0% 40.0% 50.0% 60.0%

LSI design tools

Printed circuit board design tools

Function and  logic design tools

Hardware/Board equipment

Microcomputer design tools

Other

Trading Company/Sales 4.4%

41.8%

13.9%

11.4%

8.9%

24.1%

0.0% 5.0% 10.0% 15.0% 20.0% 25.0% 30.0% 35.0% 40.0% 45.0%

Semiconductors 

Tools

Electronic equipment

Electronic components

Other

14

Details of Speciality

37.6%

21.6%

13.3%

8.5%

7.6%

1.8%0.2%

0.4%

9.0%

Design 37.6%

Design Envitronent Configration 21.6%

Reserch 13.3%

Sales 8.5%

Plannning/Advertising/Marketing 7.6%

Manufacturing/Testing 1.8%

Distribution 0.2%

Purchasing 0.4%

Other 9.0%

Breakdown of Design, Design Environment Configration and Research

Design

（37.6%）

Design Environment Configration（21.6%）

Research

（13.3%）

System-level 14.1% 11.5% 24.6%

Analog 9.4% 15.4% 13.6%

Function（RTL） 34.2% 15.1% 11.8%

Layout 11.8% 17.6% 10.1%

Software/Firmware Design 7.9% 3.4% 6.1%

Lithography/Mask/Process/Manufacture 0.3% 3.4% 5.7%

PCB 3.6% 7.0% 5.3%

Test 4.4% 9.4% 4.8%

Logic (Gate-level) 3.8% 3.4% 3.5%

TCAD 0.2% 2.1% 3.1%

IC Package 1.5% 2.1% 2.6%

Custom 1.4% 4.4% 2.2%

Macro IP 2.4% 1.6% 2.2%

FPGA/PLD 3.9% 2.1% 2.2%

SiP 0.3% 1.0% 1.3%

Device packaging 0.8% 0.5% 0.9%

15

Purpose of Visit（multiple answers）

82.0%

40.2%

19.2%

16.0%

14.3%

8.7%

8.1%

5.7%

1.4%

2.8%

Exhibition Booths

Exhibitor Seminar

Embedded Technology

Special Stage

Emerging Company Area

JEVeC Village

University Plaza

EDSFair×ET Special Collaborating Session

Emerging Company Guided Tour

Other

0.0% 20.0% 40.0% 60.0% 80.0% 100.0%

Age

2011 Nov. 2011 Jan. 2010

10’s 0.1% 0.1% 0.1%

20’s 9.4% 10.0% 11.6%

30 s 27.9% 27.9% 28.4%

40’s 36.7% 36.7% 36.6%

Over 50’s 25.9% 25.3% 23.2%

Frequency of Visit

Authority of Product introduction

I havedecision-making

authorityon productpurchasing.

8.1%

Myopinionsinfluence

purchasing52.2%

I am notinvolved inpurchasing.

39.7%

2011 Nov. 2011 Jan. 2010

First time 28.5% 30.9% 36.1%

Second times 11.6% 13.5% 13.1%

3-5 times 30.6% 30.5% 28.7%

Over 6 times 29.3% 25.1% 22.1%

2011 Nov.

2011 Jan. 2010

I have decision-making authority on product purchasing.

8.1% 9.9% 9.8%

My opinions influence purchasing

52.2% 50.4% 47.8%

I am not involved in purchasing.

39.7% 39.7% 42.4%

Second

times,

11.6%

3-5

times,

30.6%

First

time,

28.5%

Over 6

times,

29.3%

20’s,

9.4%Over

50’s,

25.9%

30 s,

27.9%

10’s,

0.1%

40’s,

36.7%

16

Recogination of event

2011 Nov.

2011 Jan.

2010

E-mail from Exhibitor 26.8% 26.2% 26.3

E-mail from the EDSFair Management Office 19.6% 16.5% 14.8

DM（EDSFair Leaflet） 14.0% 14.7% 12.4

Link from Search site 10.6% 12.6% 11.9

Link from exhibitor’s Website

6.5% 6.9% 7.7

Link from ET Website 3.4% 1.1% -

Newspaper/Magazine 1.8% 3.6% 4.1

Other 17.4% 18.4% 22.8

Link from

ET

Website

3.4%

Link from

Search

site

10.6%

Link from

exhibitor’

s Website

6.5%

Newspaper

/Magazine

1.8%

Other

17.4%

DM

（EDSFair

Leaflet）

14.0%

E-mail

from the

EDSFair

Managem

ent

Office

19.6%

E-mail

from

Exhibitor

26.8%

17

■ PR Activities

Press Releases

EDSFair2011 Nov.

（Nov.16～18）

EDSFair2011 Jan.

（Nov.27～28）

* Dissemination of release for Jointly holding

the EDSFair with ET (3/3)

* Dissemination of release for commencement

of exhibit application period.(4/6)

* Dissemination of release for commencement

of online visitors registration (9/13）

* Dissemination of release inviting press

coverage and Opening announcement (11/14)

* Press room set up （11/16～18）

* Release of event closing report （11/18）

* Dissemination of release for commencement

of exhibit application period（6/9）

* Dissemination of release for commencement

of online visitors registration（12/1）

* Dissemination of release inviting press

coverage and Opening announcement（1/20）

* Press room set up（1/27～28）

* Release of event closing report（1/28）

Number of Press

EDSFair2011 Nov. EDSFair2011 Jan. EDSFair2010

110 35 37

E-mailings

11 mailings of EDSFair2011 Nov. Official News sent to those in our past visitor database and this year's

pre-registrants.

Vol. Date Number of recipient

Vol.12 May 7 th 8,365

Vol.13 Oct. 7 th 8,382

Vol.14 Oct. 21st 8,453

Vol.15 Oct. 26th 8,480

Vol.16 Nov. 2nd 8,560

Vol.17 Nov. 9th 8,693

Vol. Date Number of recipient

Vol.18 Nov. 14th 8,803

Vol.19 Nov. 15th 8,830

Vol.20 Nov. 16th 8,868

Vol.21 Nov. 17th 8,906

Vol.22 Nov.18th 8,933

10. PR Activities

18

Creation of PR Tools (printed literature)

・PR leaflet/Invitation/Envelope (Japanese)

・Floor Map (Japanese)

19

■ URL

Official Website

http://www.efair.com

Browse：37,073

Page Views：165,802

Online Members Site

https://regist.jesa.or.jp/edsfair-regist/index.php

Pre-registration：Sep.13th～Nov.18th（till 15:00）

Registered members：17,259 members *included registered members in the past

11. Official Website

Organizer

Japan Electronics and Information Technology Industries Association (JEITA) 5F Ote Center Bldg. , 1-1-3, Otemachi , Chiyoda-ku, Tokyo 100-0004, Japan http://www.jeita.or.jp

Management/Contact

Japan Electronics Show Association (JESA) 12F Ote Center Bldg. , 1-1-3, Otemachi , Chiyoda-ku, Tokyo 100-0004, Japan TEL: +81-3-6212-5231 FAX: +81-3-6212-5225 E-mail: info2011@edsfair.com