Exercises with Finite State Machines · – No need to go through T.T.s and K-Maps • Current CAD...

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Exercises with Finite State Machines CS 64: Computer Organization and Design Logic Lecture #17 Winter 2019 Ziad Matni, Ph.D. Dept. of Computer Science, UCSB

Transcript of Exercises with Finite State Machines · – No need to go through T.T.s and K-Maps • Current CAD...

Page 1: Exercises with Finite State Machines · – No need to go through T.T.s and K-Maps • Current CAD software can do this automatically • Implemented with FPGA integrated circuits

ExerciseswithFiniteStateMachines

CS64:ComputerOrganizationandDesignLogicLecture#17Winter2019

ZiadMatni,Ph.D.

Dept.ofComputerScience,UCSB

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Administrative

•  Lab#8– DuenextweekonWednesday– PapercopydropoffatHFH2ndfloor

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Administrative

•  TheLast3WeeksofCS64:

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Date L# Topic Lab LabDue

2/26 14 CombinatorialLogic,SequentialLogic1 7(CL+SL) Wed.3/6

2/28 15 SequentialLogic23/5 16 FSM1

8(FSM) Wed.3/133/7 17 FSM23/12 18 DigitalLogicReview

9(Ethics) Fri.3/153/14 19 CSEthics&Impact

FinalExamReview

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DesigningtheCircuitfortheFSM

1.  WestartwithaT.T

–  Alsocalleda“StateTransitionTable”

2.  MakeK-Mapsandsimplify

–  Usuallygiveyouranswerasa“sum-of-products”form

3.  Designthecircuit–  HavetouseD-FFstorepresentthestatebits

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1.TheTruthTable(TheStateTransitionTable)

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State B2 B1 B0 I B2* B1* B0* FOUND

Initial 0 0 0 0 0 0 0 0

1 0 0 1 0

Found“1” 0 0 1 0 0 0 0 0

1 0 1 0 0

Found“11” 0 1 0 0 0 1 1 0

1 0 1 0 0

Found“110” 0 1 1 0 0 0 0 0

1 1 0 0 0

Found“1101” 1 0 0 0 0 0 0 1

1 0 1 0 1

CURRENTSTATE NEXTSTATEINPUT(S) OUTPUT(S)

Nextstate:K-Maps!

Outputs:Relatetostateinput

bits

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3.DesigntheCircuit

NotethatCLKistheinputtoALLtheD-FFs’clockinputs.Thisisasynchronousmachine.Notetheuseoflabels(example:B2orB0-bar)insteadofroutingwiresallovertheplace!NotethatIissuedbothBnandBn-barfromalltheD-FFs–itmakesiteasierwiththelabelingandyouwon’thavetouseNOTgates!Notethatthesoleoutput(FOUND)doesnotneedaD-FFbecauseitisNOTASTATEBIT!

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AND ORDFF

FPGAsandProgrammableLogic

Field-ProgrammableGateArrays

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The“OneHot”Method•  MostpopularlyusedinbuildingFSMs•  Giveeachstateit’sownD-FFoutput

–  #ofFFsneeded=#ofstates–  YouendupusingMORED-FFs,buttheimplementationiseasierto

automate

•  InputstotheD-FFsarecombinatoriallogicthatcansimplifiedintoa“sum-of-products”typeofBooleanexpression–  NoneedtogothroughT.T.sandK-Maps

•  CurrentCADsoftwarecandothisautomatically•  ImplementedwithFPGAintegratedcircuits

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EncodingourStatesPerthelastexample(“1101Detector”):Wehad5separatestates,sowe’regoingtoneed5bits(i.e.5DFFs)todescribethestates:NAME “Regular”Code“OneHot”Code OUTPUTSInitialState S0 000 00001 “1” S1 001 00010“11” S2 010 00100“110” S3 011 01000“1101” S4 100 10000 FOUND

•  Advantageofthis“OneHot”approach?–  Whenweimplementthemachinewithcircuits,wecanuseaD-FFfor

everystate(so,inthisexample,we’duse5ofthem)

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Usingthe“OneHot”CodetoDeterminetheCircuitDesign

•  Everystatehas1D-FF•  Wecanseethat

(followthearrows!!):S0*=S0.I+S1.I+S3.I+S4.IS1*=S0.IS2*=S1.I+S2.I+S4.IS3*=S2.IS4*=S3.IAlso,whenS4isTrue,FOUNDisTrue,i.e.FOUND=S4WehavenowdescribedALLtheoutputsofthemachineascombinationsofcertaininputsWITHOUTneedingtodoT.T.&K-Maps!

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“1” “11”

“110”“1101”

InitialState

Input=0 Input=1

Input=1

Input=0Input=0

FOUND=1

Input=1

S0

S4 S3

S2S1

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ImplementingtheCircuitFor“Detect1101”FSMUsingthe“OneHot”Method

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FSMExercise1•  GivenaFSMdescribedwiththefollowingstatediagram

where:–  TheinitialstateisS1–  Thereisonly1input,X–  Thereisonly1output,Y,

anditisinitializedto0

•  WhatstatedoyouendupinifXtakesonthesequentialvalues0110?

•  WhichoftheseinputswillresultinY=1attheendoftheirsequences?A.   0110B.   1111101C.   0101010

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X= X=

X=X=

1

Y=1

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FSMExercise1b•  Howmanybitsdoweneedto

representallthestatesinthisFSM?–  Usingregular,non-alternativemethods

•  WritetheT.T.forthisFSM

•  Writethenext-statefunctionsforthisFSM

•  DesignthedigitallogiccircuittoimplementthisFSM,showingallinputsandalloutputs

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X= X=

X=X=

1

Y=1

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FSMExercise2•  DesignaFSMthattakesin2single-bitbinaryinputs,AandBandalwaysis

resetto(beginsin)aninitialstate.

•  ThemachinewillmovefromtheinitialstateonlyifA&&Bistrue.Onceitdoesthat,however,itwillgothroughNstatessequentially,onceforeverytimeA||Bistrue.

•  Onthelaststate,itsimplygoestotheinitialstateagainandrepeats.

A.  DrawthestatediagramforN=3.B.   Usingthe“one-hotmethod”,howmanybitsdoweneedtorepresentall

thestatesinthisFSM?C.  Writethenext-statefunctionsforthisFSMusingtheapproachinB.D.  Designthedig.logiccircuittoimplementtheFSMusingyourresultssofar

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FSMExercise3•  ConsidertheFSMcircuit,

shownhereusingthe“one-hotmethod”

A.  Identifythenon-clockinputsandoutputs

B.  Writethenextstateequations

C.  WritetheT.T.forthisFSM

D.  DrawthestatediagramforthisFSM

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D QClk

y1

Clk

D QClk

y2

Clk

x

OR

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YOURTO-DOs

•  Lab8

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