Exercises for Active Loads & IC MOS...
Transcript of Exercises for Active Loads & IC MOS...
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Exercises for Active Loads & IC MOS Amplifiers
ECE 102, Fall 2011, F. Najmabadi
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Exercise 1: Compute the voltage gain of the circuit below.
Q1 is a source follower and Q2 is its active load
)||(1)||(
211
211
oom
oomv rrg
rrgA+
=
Signal
CD Fundamental Configuration
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Exercise 2: Compute the voltage gain of the circuit below.
Signal
Q1 is a CS Amp Q2/Q3 are the active load
LR)||( 11 Lomv RrgA −=
Need to Find RL
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Finding RL
3322 )1( oomoL rrgrR ++=
) ||(
)1( )1(
32211
322
2233322
3322
oomomv
oom
omooomo
oomoL
rrgrgArrg
rgrrrgrrrgrR
−=≈
+=+≈++=
LR
11 omv rgA −≈⇒>> :Typically 1322 ooom rrrg
Providing a large active load (e.g., a cascode load) for a CS amplifier does not increase the gain drastically (only by a factor of two)
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Exercise 3: Compute the Bias point details of transistors in the circuit below with µnCox = 200 µA/V2, µpCox = 65 µA/V2, (W/L) = 10, Vtp = − 0.6 V, Vtn = 0.6 V, VAp = − 10 V, VAn = 20 V: A) Ignore channel-width modulation B) Include channel-width modulation and set the DC voltage at VG2 = 0.77 V.
V 3.06.09.0||V 9.01.23
11
11
=−=−==−=−=
tpSGOV
GDDSG
VVVVVV
1-
-1
V 05.0 /1
V 1.0 ||/1
==
==
Ann
App
V
V
λ
λ
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A) Ignore channel-width modulation
V 3.0 1 =OVV
µnCox = 200 µA/V2, µpCox = 65 µA/V2, (W/L) = 10, Vtn = 0.6 V
A 3.29
)3.0(1010655.05.0
1
26211
µ
µ
=
××××== −
D
OVoxpD
I
VL
WCI
A 3.29 12 µ== DD II
V 171.0
10102005.05.0
2
22
6222
=
××××== −
OV
OVOVoxnD
V
VVL
WCI µ
V 771.0 V 771.06.0171.0
222
22
=+==+=+=
SGSG
tnOVGS
VVVVVV
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B) Include channel-width modulation and set the DC voltage at VG2 = 0.77 V µnCox = 200 µA/V2, µpCox = 65 µA/V2, (W/L) = 10, Vtp = − 0.6 V, Vtn = 0.6 V, λp = 0.1 V-1 , λn = 0.05 V-1
V 17.0 V 77.0
V 3.0
2
22
1
===
=
OV
GGS
OV
VVV
V
)1(5.0
)1(5.0
22
22
12
11
DSnOVoxnD
SDpOVoxpD
VVL
WCI
VVL
WCI
λµ
λµ
+=
+=
21
226
126
22
212
1
21
049.0988.01.01)05.01()17.0(10200)1.01()3.0(1065
)1(5.0)1(5.0
DSSD
DSSD
DSnOVoxnSDpOVoxp
DD
VVVV
VVL
WCVVL
WC
II
+=++×=+×
+=+
=
−−
λµλµ
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321 =+ DSSD VV
012.049.0
049.0988.01.01
21
21
=−+−
+=+
DSSD
DSSD
VV
VV
KVL:
V 93.1 V 07.1
2
1
==
DS
SD
VV
A30.3A30.31.035)(A) 3.29(
)07.105.01()3.0(1010655.0
)1(5.0
2
1
26
12
11
µµµ
λµ
==×=
×+××××=
+=
−
D
D
SDpOVoxpD
II
VVL
WCI
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??
V 771.0A 3.29
V 3.0
2
1
22
21
1
==
====
=
DS
SD
GGS
DD
OV
VV
VVII
Vµ
V 93.1V 07.1
V 770.0A 3.30
V 3.0µ
Ignore channel-width modulation
V 1V 2
V 780.0A 3.31
V 3.0µ
−−−−
V 800.0A 3.32
V 3.0µ
Include channel-width modulation
Specified parameters
Ignoring channel-width modulation gives relatively accurate results for ID and VOV (thus, gm and ro) o But we cannot find VDS
In reality (including channel-width modulation), VG2 is also specified. o We find unique values for VDS o Precise biasing of VG2 (DC value of vi ) is required.
Q2 in triode!
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Exercise 4: Design the circuit below for a gain of 20 and a power budget of 2 mW. Assume transistors have the same Vov with µnCox = 100 µA/V2, µpCox = 50 µA/V2, (W/L)3 = 20/0.18, λp = 0.2 V−1, λn = 0.1 V−1, and Vtn = 0.4 V. Ignore channel-width modulation in biasing calculations. (Design: Find (W/L) of all transistors, Iref , and VG3 )
This is a CS amplifier (Q3) with an active load (Q2) biased with a current mirror (Q1 & Q2)
)||()||( 23333
2
oomLomv
oL
rrgRrgArR
−=−==
23 :Also DD II =
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323
23
3233
3233
23
2323 1)/(
)/()/()/(|| o
oo
oo
oo
oooo r
rrrr
rrrrrr ×
+=
+×
=+×
=λλ
λλλλλλ
Note the only active load transistor parameter that enters the gain formula is λ2 1)/(
)/()||( 23
2333233 +×−=−=
λλλλ
omoomv rgrrgA
3
33
2
OV
Dm V
Ig = 1
333
Do I
rλ
=3222
211
DDo II
rλλ
== 32
32 oo rr
λλ
=⇒
1)/()/(2
1)/()/(12
1)/()/(
23
23
3323
23
333
3
23
2333 +
×−=+
××−=+
×−=λλ
λλλλλ
λλλλλ
λλ
OVDOV
Domv VIV
IrgA
V 33.0 32
1.0220 3
3
=⇒×= OVOV
VV32
2
3 2 2 oon
p rr =→==λλ
λλ
The relevant parameters of transistor amplifier are λ & VOV
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V 33.0321 === OVOVOV VVV
2623
33 )33.0(
18.020101005.05.0 ××××=
= −
OVoxnD VL
WCI µ
V 73.0V 73.04.033.0
333
33
=+==+=+=
SGSG
tnOVGS
VVVVVV
A 6173 µ=DI A 61732 µ== DD II
18.0402
10050
5.05.0
32
32
32
33
22
22
=
×=
×=
×
=
=
=
LW
LW
LW
LW
IVL
WCVL
WCI DOVoxnOVoxpD µµ
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A 6173 µ=DI
A 61732 µ== DD II
18.0402
32
=
×=
LW
LW
Current Mirror:
2
1
2 )/()/(
LWLW
II
D
ref =3-
3
-33
1011.1
W10 3)( 8.1
×=+
×=+=
refD
refD
II
IIP
A 616 µ=refI
2
16
6
)/()/(
1061710616
LWLW
=××
−
−
18.0
40 21
=
=
LW
LW
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Exercise 5: Design the common gate stage of the circuit below for a gain of 20 and an input impedance of 150 Ω for (W/L)3 = 40/0.18 and ID5 = ID2 = 2 Iref Assume Q1 and Q2 have the same VOV , µnCox = 100 µA/V2, λp = 0.2 V-1, and λn = 0.1 V-1. Ignore channel-width modulation in biasing calculations. (Design: Find W/L of all transistors and Iref )
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Signal
1) Q1 is a CG amplifier
2) Q3 is the active load for the CG amplifier as well as for biasing
3) Q2 provides the current source which is necessary in the source circuit for biasing Q1
4) Q4 is the reference leg of Q3-Q4 current mirror
6) Qref is the primary transistor for all current steering circuits
5) Q5 provides the reference current for the Q3-Q4 current mirror
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1
11
2
OV
Dm V
Ig = 1
111
Do I
rλ
=1333
311
DDo II
rλλ
==
331
31 2 ooo rrr ==
λλ
1113
1331 3
21)/(
)/(|| oooo rrrr ×=×+
=λλ
λλ
1111311
232
32)||(
OVomoomv V
rgrrgAλ
×=×=≈
V 33.0 1.02
32 20 1
1
=⇒×= OVOV
VV
Gain = 20
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11
13
11
131
11
31 3/1)/1(1 mm
oo
om
ooo
om
ooCG gg
rrrg
rrrrg
rrR =+
=+
≈+
+=
CGQi RRR ||2=
mA/V 20 3150 11
=⇒= mm
gg
Ri
RQ2
RCG
Input Resistance = 150 Ω
22 oQ rR =
122
3|| m
CGCGQiQCG gRRRRRR =≈=⇒<<
mA 333.02
1020 10202 3
13
1
11 =
××
=⇒×==−
−D
OV
Dm I
VIg
2
1
621
11
3 )33.0(101005.05.0103 ×
×××=
==× −−
LWV
LWCI OVoxnD µ
18.099551
1
==
LW
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mA 3123 === DDD III
mA 3254 === DDD IIImA 5.15.0 5 == Dref II
18.040 &
18.099
31
=
=
LW
LW
18.0
99 12
12 =
=
⇒=
LW
LWII DD
18.0505.0
)/()/(
222
=
×=
⇒=
LW
LW
LWLW
II
ref
ref
D
ref
18.0
40 )/()/(
343
4
3
4 =
=
⇒=
LW
LW
LWLW
II
D
D
18.0992
)/()/(
555
=
×=
⇒=
ref
ref
D
ref
LW
LW
LWLW
II
Q1 and Q2 have the same Vov
Current Mirrors
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Every Cascode stage increases R by gmro
oomoom
oomo
rrgrrgrrgr
)(
)1(2
1122
≈+≈
++
oomomom
omommo
rrgrgrgrgrggr
2232
2233
)(
)1(
≈+≈
++
2omrg
Exercise 6: Compute R (assume ro1 = ro2 = ro3 and gm1 = gm2 = gm3)
Double Cascode
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Exercise 7: Compute all indicated R’s, v’s, and i’s . Assume identical transistors are identical. (S&S Problem 7.34)
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1 orR =
)(
)1( 2
2
oomoom
oomo
rrgrrgrrgrR
≈+≈
++=
1
)(1
23 o
om
oomo
om
o rrg
rrgrr g
RrR =+
+=
++
=
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oom
oomo
om
o rrg
rrgrr g
RrR 1
)(1
23 =
++
=+
+=
From previous slide:
CS amplifier:
)||()||( 3 oomomv rrgRrgA −=−=
5.0 1 iom vrgv −=
5.05.0 3
13 im
o
iom vgr
vrgRvi ==−=
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From previous slide:
A simpler method:
)(5.0)(5.0 22242 iomomim vrgrgvgRiv −=−=−=
5.0 34 imvgii ==
)( 2 oom rrgR =
Cascode amplifier (we can use cascode gain to find v2)
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From previous slide:
5.05.0 153 iomoim vrgrvgRiv −=−=−=
5.0 45 imvgii ==
1 orR =
Q3 is NOT an amp configuration It is part of the active load!
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vgs = 0, current source is open circuit:
5.0 0
57
6
imvgiii
−===
From Text book
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Exercise 8: Due to manufacturing error, the input terminal of a cascode amplifier is mis-configured as is shown. Compute vo. Assume identical transistors are identical.
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From previous Problem:
)( 2 oom rrgR =
oS rR =
This is a CG configuration )||( 2 omomv rgRrgA ≈=
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)( 2 oom rrgR =
oS rR =
Q1 does not affect the gain, but it changes the input resistance to:
orR 3 =From previous problem:
5.0|||| 3 oooSi rrrRRR ===
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Exercise 9: Due to manufacturing error, a parasitic resistance has appeared between drain and source of Q1. Compute vo. Assume identical transistors are identical.
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From previous Problem:
3 orR =
)||( 22 omomv rgRrgA ≈= )||||()||||( 31 poompomv RrrgRRrgA −=−=Q2: CG configuration: Q1: CS configuration:
)||||( 221 pooomvvv RrrrgAAA −==
)( 2 oom rrgR =
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When a resistor is placed between Drain and Source of a transistor, there is a simpler and more elegant way to solve the circuit
Rrr oo ||=′
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From previous Problem:
oom rrgR )(2 =
orR =3
omomv rgRrgA ≈= )||( 22
oi rRR == 32)||||()||( 11 opomLomv rRrgRrgA −=′−=
Q2: CG configuration: Q1: CS configuration:
oiL rRR == 21
)||||(221 pooomvvv RrrrgAAA −==
poo Rrr ||=′
![Page 33: Exercises for Active Loads & IC MOS Amplifiersaries.ucsd.edu/NAJMABADI/CLASS/ECE102/11-F/NOTES/ECE102...Exercise 4: Design the circuit below for a gain of 20 and a power budget of](https://reader034.fdocuments.in/reader034/viewer/2022051808/600af695133323460a5a9a4b/html5/thumbnails/33.jpg)
Exercise 10: Due to manufacturing error, a parasitic resistance has appeared between drain and source of Q2. Compute vo. Assume identical transistors are identical.
![Page 34: Exercises for Active Loads & IC MOS Amplifiersaries.ucsd.edu/NAJMABADI/CLASS/ECE102/11-F/NOTES/ECE102...Exercise 4: Design the circuit below for a gain of 20 and a power budget of](https://reader034.fdocuments.in/reader034/viewer/2022051808/600af695133323460a5a9a4b/html5/thumbnails/34.jpg)
From previous Problem:
oom rrgR )(2 =
)||()||( 22 pomomomv RrgrgRrgA =′≈′=
o
o
om
om
om
oi r
rrg
rgrg
RrR′
≈′+
≈′+
+′=
222
2 11
)||()||(2
11o
oomLomv r
rrgRrgA′
−=−=
Q2: CG configuration:
Q1: CS configuration:
)||||(221 pooomvvv RrrrgAAA −==
poo Rrr ||=′
oomoo rrgrr )( <<<′
po
oiL Rr
rRR||
2
21 ==