Bang-Bang type PLL for balanced three phasevoltages

It is essential that the PLL system should work under distorted utility condi-tions. Moreover, it also should be able to lock-in as fast as possible and providethe reference signal without distortion. Since the PLL system is implemented ina digital manner using a digital signal processor (DSP), a bang-bang type PLLis proposed which gets locked faster and easier to implement for balanced gridvoltages. From the Figure 1 the grid voltages va, vb and vc in the d-q domain

bc

d qto

d

q

abctodq

dq0

sece

Oscillator+

H

Compav

v

v

v

v

q

d

v

v

ee

L

e

e

Figure 1: Bang-Bang type PLL.

arevq(n+ 1) = va(n+ 1) (1)

vd(n+ 1) = 0.57735(vc(n+ 1) vb(n+ 1)) (2)voltages vd and vq in the de-qe domain are

vqe(n+ 1) = vq(n+ 1)ce(n) vd(n+ 1)se(n) (3)

vde(n+ 1) = vq(n+ 1)se(n) + vd(n+ 1)ce(n) (4)

difference equations for the harmonic oscillator can be written as

se(n+ 1) = se(n) + e(n+ 1).ts.ce(n) (5)

ce(n+ 1) = ce(n) e(n+ 1).ts.se(n+ 1) (6)where ts is the sampling time, equations (5) and (6) can be written in statespace form as[

se(n+ 1)ce(n+ 1)

]=

[1 00 1

] [sece

]+

[ce(n)

se(n+ 1)]u(n+ 1) (7)

whereu(n+ 1) = e(n+ 1).ts (8)

Using (4) and (7) it follows

vde(n+1) = vq(n+1)se(n1)+vq(n+1)u(n)ce(n1)+vd(n+1)ce(n1)vd(n+1)u(n)se(n)(9)

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The control which ensures vde = 0, can be found by solving the following equa-tion:

vq(n+1)se(n1)+u(n) (vq(n+ 1)ce(n 1) vd(n+ 1)se(n))+vd(n+1)ce(n1) = 0.(10)

It should be noted that the above equation is obtained by setting vde = 0 in(9). For notational simplicity let us define

Qa vq(n+ 1)ce(n 1) vd(n+ 1)se(n) (11)(n) vq(n+ 1)se(n 1) + vd(n+ 1)ce(n 1) (12)

Using the above definition, (10) can be rewritten as

vde(n+ 1) = (n) +Qau(n) (13)

from the above equation dead-beat type of control law can be derived as

u(n) = e(n)ts = Q1a (n) (14)Since the above control law is computationally intensive. The objective of forc-ing vde towards zero can also be achieved by the following discontinuous control

u(n) = Msign(vde) (15)where M = Q1a N and N is chosen so that

| | + N n (16)where is a small positive constant. It is straightforward to verify that thecontrol Eqn. (15) ensures decay of absolute value of vde. From (13) and (15) wecan write vde(n+ 1) as

vde(n+ 1) = (n)Nsign(vde) (17)In the figure the block comparator is a switch, which switches between tworeference frequencies. They are upper (H) and lower (L) limits of e, andswitch state depends upon the error vde. The output of the comparator drivesthe harmonic oscillator to reduce the error and locks to the system frequency.Figure shows the characteristics of vde by switching (n) with a specific band.To understand how

vde

approaches zero, consider the follwing two cases:

Case-1 when vde > 0, vde(n+1) = (n)N , for the condition of Eqn. (16)it follows vde(n + 1) < 0. As shown in Figure 1 the control law ensuresdecay of vde at certain minimum rate () and reaches to zero.

Case-2 when vde < 0, vde(n+1) = (n)+N , for the condition of Eqn. (16)it follows vde(n + 1) > 0. In this case vde moves towards vde = 0 line atcertain minimum rate () of increase.

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From Eqn. (16) it is clear that the minimum rate at which vde approaches tovde = 0 is . By considering the minimum decay rate of absolute value of vde

(nf )max vde(0)

(18)

where nf is the maximum sampling instants at which vde becomes zero. How-ever, it is worth noting that when the value of is smaller, then the decay rateof vde becomes higher. When = 0, the decay rate is N . By increasing the thedecay rate of absolute value of vde increases. Whenever vde crosses vde = 0 linefrom either side, the control law forces back vde on vde = 0 line. Eventually, thisleads to continuously crossing and recrossing of vde = 0 line. This phenomena iscalled chattering [?]. To avoid the chattering a band across vde = 0 line can beintroduced; the switching takes place when vde is out side the band from eitherside. This solution reduces the excessive crossing and recorssing of vde = 0 line.

Figure shows the simulation results of PLL for L = 46 Hz and H = 55 Hz.Initially the grid frequency is set at 50 Hz, to observe the transient responseof the proposed system when t = 80 ms the grid frequency is switched to 45Hz. Figure shows the tracking performance of PLL and response time of controloutput vde. Figure shows the simulation results of PLL for L = 40 Hz andH = 60 Hz. Initially the grid frequency is set at 50 Hz, when t = 80 ms thegrid frequency is switched to 45 Hz. Figure shows the tracking performanceof PLL for L = 35 Hz, H = 65 Hz. Initially the grid frequency is set at50 Hz, when t = 80 ms the frequency is switched to 45 Hz. Figure shows thetracking performance of PLL for L = 35 Hz and H = 65 Hz. Initially thegrid frequency is set at 55 Hz, when t = 80 ms the frequency is switched to 45Hz. The effects of values of H and L upon the performance of PLL are asfollows:

Initially error is negative, so H is applied as an input to the harmonic os-cillator. Due to this, the output frequency increases faster and waveformsas shown in, gets locked faster. So increasing H will increase the responsetime. During this time L is zero. This large difference in HL resultsin fast locking.

Lower band (L) if increased, will affect the response by increasing thelocking time, but the reference frequency should be within H and L.Otherwise system will not get it locked.

From the experimental results for a given band of switching frequency the PLLtracks the references in less than half cycle. The tasks carried out by the DSP(TMS320VC33) for implementation of PLL takes 1.16 s in total for a time stepof 20 s. Where transformations conversion time is 660 ns and PLL algorithmexecution time is 500 ns. These results are well justified in terms of transientresponse and code optimization.

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