Evolving Spiking Neural Networks

Final Year Project Presentation2nd April 2007

Yusuf Cinar - 4ECE

Project Aim

The aim of this project is to develop reconfigurable network connectivity in a Spiking Neural Network.

Neuron 1w1

Neuron 3w3

Neuron 4w4

Neuron 2w2

Neuron 1w1

Neuron 3w3

Neuron 4w4

Neuron 2w2

Project Aim

A Multiplexer System is proposed to be used to provide the dynamic connectivity in between neurons.

System consists of 4 Multiplexer Boards – 16 Multiplexers A Base Board

Multiplexer System

1

1213

24

25

36

37

48ADG726 / ADG 732

1

1213

24

25

36

37

48ADG726 / ADG 732

1

1213

24

25

36

37

48ADG726 / ADG 732

1

1213

24

25

36

37

48ADG726 / ADG 732

1

1213

24

25

36

37

48ADG726 / ADG 732

1

1213

24

25

36

37

48ADG726 / ADG 732

1

1213

24

25

36

37

48ADG726 / ADG 732

AB

E

CD

F G H

Mux

Boa

rd 3

Mux

Boa

rd 2

Mux

Boa

rd 1

Mux

Boa

rd 0

1

2

39

40

13

2

1 2

9 10

1 2

9 10

1

2

15

16

1

2

15

16

1

2

15

16

1

2

15

16

Multiplexer System

The core responsibility in the project has been to test the Multiplexer System if it functions properly.

In order to test the system, I had to; Gain skills in Programming IO Cards Improve Digital and Analogue Electronics

Knowledge Figure out the connections in the system Manipulate the Amplicon connector

Programming IO Cards

The IO Cards used in the project NIDAQ 6009 USB x 4Amplicon PCI 272

PC Controlled

MUX System

Amplicon PCI 272

NIDAQ x 4

16 outputs

16 inputs

4 Address lines

16 WR lines

Power up Mux System, VDD-GND

Testing MUX System

Testing MUX System

In order to have a stable testing environment an Interface Board has been designed so that System has solid connections.

By the help of Interface Board, user only has to run the software to complete a full test.i.e. avoiding user from getting into

connection details of the system

Testing MUX System

Interface Board sits in between 4 NIDAQ Devices and MUX System

M(0,0) M(3,3)

E1 F11

2

15

16

1

2

15

16

1

2

15

16

1

2

15

16

G1 H1

C11

2

9

10

1

2

9

10

D1

INPUTS

0 15

OUTPUTS

Testing MUX System

M(0,0) M(3,3)

E1 F11

2

15

16

1

2

15

16

1

2

15

16

1

2

15

16G1 H1

C11

2

9

10

1

2

9

10D1

INPUTS0 15

OUTPUTS

AB

E

CD

F G H

Mux B

oard 3

Mux B

oard 2

Mux B

oard 1

Mux B

oard 0

1

2

39

40

13

2

1 2

9 10

1 2

9 10

1

2

15

16

1

2

15

16

1

2

15

16

1

2

15

16

NIDAQ 6009 x 2 NIDAQ 6009 x 2

AMPLICON PCI 272

VB CODE

Testing MUX System - AlgorithmDefault Settings

Set Input(i)=1Others = 0

Enable&Disable Mux(k, j)

Set Address = t

Read Outputs of

Multiplexers

t = i

OutMux(k, j) =1

Status PASS

Status FAIL

t = 15

j = 3

k = 3

i = 15

OutMux(k, j) =0

Increment t

Increment j

Increment k

Increment i

END

START

Y

Y

N

N

N

N

N

Y

N

Y

Y

N

Y

N

Testing is performed using digital inputs and outputs

Testing strategy is based on Checking every single input line Checking every address line Checking every control bits (WR lines) Checking every single output line

The testing strategy finds out if Each Multiplexer operates properly itself Multiplexers interfere with each other

Testing MUX System - Algorithm

Results

It is found out that one of the Boards has a Multiplexer which is not functioning correctly (Board 1-MUX 0)

The ports for Input line 3 have been both grounded and they never work for any Multiplexer. The reason originates from a problem on Base Board.

Results

Board 1 – Mux 0 will have to be produced from the scratch. It affects the operations of other Multiplexers.

The problem with Input Line 3 does not necessarily stop us progressing as in the proposed system Input Line 3 is not used.

Additional Skills Gained

The Concept of FPAA Technology The design and simulation of FPAAs

using Anadigm Designer 2 Software Insights of Neural Networks Hardware Skills

Questions?