EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS

17
Approved for public domain release (N68936-05-C-0066 on 10-10-2008) © 2008 BAE Systems - All rights reserved EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS Joseph R. Marshall 5 November 2008 – International SpaceWire Conference

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EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS. Joseph R. Marshall 5 November 2008 – International SpaceWire Conference. SpaceWire Components and their Applications. SpaceWire ASIC Mini-RF Control Processor and Software - PowerPoint PPT Presentation

Transcript of EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS

Page 1: EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS

Approved for public domain release (N68936-05-C-0066 on 10-10-2008)© 2008 BAE Systems - All rights reserved

EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS

Joseph R. Marshall5 November 2008 – International SpaceWire Conference

Page 2: EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS

Components II Session - Marshall Paper - Page 2 5 November 2008Approved for public domain release (N68936-05-C-0066 on 10-10-2008)

© 2008 BAE Systems - All rights reserved

SpaceWire Components and their Applications

• SpaceWire ASIC• Mini-RF Control Processor and Software• SpaceWire Evaluation Board and Usage• Next Generation SpaceWire ASICs

Page 3: EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS

Components II Session - Marshall Paper - Page 3 5 November 2008Approved for public domain release (N68936-05-C-0066 on 10-10-2008)

© 2008 BAE Systems - All rights reserved

4 Port SpaceWire ASIC Block Diagram and Features

SRAM

PCI 2.2

DMA

SOC Combined GSFC’s SpaceWire Core with BAE’s Core-Based Bridge ASIC

Page 4: EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS

Components II Session - Marshall Paper - Page 4 5 November 2008Approved for public domain release (N68936-05-C-0066 on 10-10-2008)

© 2008 BAE Systems - All rights reserved

LRO Command and Data Handling (C&DH) / Spacecraft Architecture

RAD750SBC

Data StorageBoard(DSB)

(4)

HK/IO

LROC

LAMP

LOLA

MAC

1553B

LEND

DRLE

CRATER

SpaceWire

1553B

Science Downlink

Mini-RF

BAESpaceWire

ASIC

1553 Summit

(BC)

cPCI

SpaceWire FPGA

SpaceWire FPGA

SpaceWire FPGA

SpaceWire FPGA

BAE SpaceWire

ASIC

C&DH

LVPC

SUBSYSTEMS (ACS, PSE, PRO/DEP)

Backplane

HGA

S-Xpndr

Ka-Xmtr

HGAGimbals

1553 Summit

(RT)

AnalogInputs

HK Downlink

LAMP Tlm

cPCI

USO9600

USO9500

cPCI signalsPOR

Comm Card

Ka-Comm S-Comm

(A)(B)

NAC1 WACNAC2

PCI

SpaceWire ASIC Key to

LRO SpaceWire

Network

Page 5: EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS

Components II Session - Marshall Paper - Page 5 5 November 2008Approved for public domain release (N68936-05-C-0066 on 10-10-2008)

© 2008 BAE Systems - All rights reserved

MINI-RF

Mini-RF Processor-Centric View

Control Processor Slice

External Power

Other Mini-RF Slices

Te

mp

era

ture

Mo

nito

rs

Dis

cre

te C

on

tro

ls&

Sta

tus

Se

rial P

erip

he

ral

Inte

rfa

ce

Sp

ace

Wire

SpaceWire

Other LROElements

RAD750 Control Processorin Mini-RF Payload used

SpaceWire for external interface and high speed

internal interfaces

Page 6: EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS

Components II Session - Marshall Paper - Page 6 5 November 2008Approved for public domain release (N68936-05-C-0066 on 10-10-2008)

© 2008 BAE Systems - All rights reserved

Control Processor Interfaces

RAD750

Control

Processor

28V Power

28V ReturnJ01(15)

SpaceWire Port A

J04-7(4x9)

SpaceWire Port B

SpaceWire Port C

SpaceWire Port D

8 Temp Sense

SpaceWire JTAG

RS422 UARTP08(51)

J03(51)

SPI + 2 Disc + Gnd

SPI + 2 Disc + Gnd

2 Discretes + Gnd

2 Discretes + Gnd

Boot Discretes2 Discretes + Gnd

CPU JTAG

RAD750 COP/JTAG

Control & Status

J02(37)

Four SpaceWire ports are used to perform all high

speed interfacing

Page 7: EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS

Components II Session - Marshall Paper - Page 7 5 November 2008Approved for public domain release (N68936-05-C-0066 on 10-10-2008)

© 2008 BAE Systems - All rights reserved

Mini-RF RAD750 Control Processor Block Diagram

P60X Bus

Serial Peripheral Interface (SPI)

SpaceW

ire Addr

& C

trl

Local Memory Address & Controls

Local Memory Data

JTA

Gs

RAD750

SUROMPROM

64Kbytes + ECC(32K x 8 bits x 3)

EnhancedPower PCI

ASIC

Local Mem.SRAM

4MBytes + ECC(512K x 40 bits x 2)

A/D Conv.

SpaceWireASIC

SpaceWireSRAM

4MBytes + ECC(512K x 40 bits x 2)

SpW2

SpW1

SpW3

SpW0

STE Pri

ma

ry

Po

we

r

Dis

cret

es

AR

EX

&X

MIT

Local Mem.EEPROM

4MBytes + ECC(512K x 40 bits x 2)

XCVR

QD

WS

, D

RX

n&

Th

erm

isto

rs

SpaceWire Data

RS-422Buffers

UA

RT

VREF

AnalogMux

LV

DS

LV

DS

AC

TQ

244

AC

138Analog Mux

Selection Discretes

8 External Thermistors3 Internal Thermistors

Bi-Level and Pulsed Bi-level Discretes

QDWS

DRX1

DRX2

AREX

XMIT

UA

RT S

pWJT

AG

EP

PC

I JT

AG

Dis

cret

es

RA

D75

0 JT

AG

+5.0VVoltage

Regulator

Nat. Semi.

PCI Bus

Reset

Reset

AC05 AC14

POR1_N

POR0_N

13 Internal Voltages/References

P60X Bus

Serial Peripheral Interface (SPI)

SpaceW

ire Addr

& C

trlS

paceWire A

ddr&

Ctrl

Local Memory Address & ControlsLocal Memory Address & Controls

Local Memory DataLocal Memory Data

JTA

Gs

RAD750

SUROMPROM

64Kbytes + ECC(32K x 8 bits x 3)

EnhancedPower PCI

ASIC

Local Mem.SRAM

4MBytes + ECC(512K x 40 bits x 2)

A/D Conv.

SpaceWireASIC

SpaceWireSRAM

4MBytes + ECC(512K x 40 bits x 2)

SpW2

SpW1

SpW3

SpW0

STE Pri

ma

ry

Po

we

r

Dis

cret

es

AR

EX

&X

MIT

Local Mem.EEPROM

4MBytes + ECC(512K x 40 bits x 2)

XCVR

QD

WS

, D

RX

n&

Th

erm

isto

rs

SpaceWire Data

RS-422Buffers

UA

RT

VREF

AnalogMux

LV

DS

LV

DS

AC

TQ

244

AC

138Analog Mux

Selection Discretes

8 External Thermistors3 Internal Thermistors

Bi-Level and Pulsed Bi-level DiscretesBi-Level and Pulsed Bi-level Discretes

QDWS

DRX1

DRX2

AREX

XMIT

UA

RT S

pWJT

AG

EP

PC

I JT

AG

Dis

cret

es

RA

D75

0 JT

AG

+5.0VVoltage

Regulator

Nat. Semi.

PCI Bus

Reset

Reset

AC05 AC14

POR1_N

POR0_N

13 Internal Voltages/References

Mini-RF Processor Board Leveraged elements from several previous

processor designs including LRO SBC

Page 8: EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS

Components II Session - Marshall Paper - Page 8 5 November 2008Approved for public domain release (N68936-05-C-0066 on 10-10-2008)

© 2008 BAE Systems - All rights reserved

Control Processor Slice Isometric Views

Control Processor Self-Contained within a stackable Slice

with all connections by cable

SpaceWire Connectors

Page 9: EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS

Components II Session - Marshall Paper - Page 9 5 November 2008Approved for public domain release (N68936-05-C-0066 on 10-10-2008)

© 2008 BAE Systems - All rights reserved

Internal Software Structure

Control Processor Hardware

VxWorks

Device Drivers (OS extensions)

RAD750 BSP

CP Software Application

CP SUROM

Mini-RF Payload softwareSelf-contained on Slice in

PROM and EEPROMBuilt mostly from existing

software modules

Page 10: EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS

Components II Session - Marshall Paper - Page 10 5 November 2008Approved for public domain release (N68936-05-C-0066 on 10-10-2008)

© 2008 BAE Systems - All rights reserved

SpaceWire Evaluation Board Block Diagram

A subset of the LRO SBC (and Mini-RF Processor),

the SpaceWire Evaluation Board provides

a Low Cost Breadboard for space applications

Page 11: EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS

Components II Session - Marshall Paper - Page 11 5 November 2008Approved for public domain release (N68936-05-C-0066 on 10-10-2008)

© 2008 BAE Systems - All rights reserved

SpaceWire ASIC Evaluation Board Photos

Easily fit on a 6U-160 CompactPCI board, The SpaceWire Evaluation Board plugs

into standard COTS Backplanes

Page 12: EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS

Components II Session - Marshall Paper - Page 12 5 November 2008Approved for public domain release (N68936-05-C-0066 on 10-10-2008)

© 2008 BAE Systems - All rights reserved

Multi-Port Router from SpaceWire Evaluation Boards

JTAG

SpaceWireASIC

Eval Bd 1

SpaceWireASIC

Eval Bd 2

SpaceWireASIC

Eval Bd 4

SpaceWireASIC

Eval Bd 3

SpaceWire Port

SpaceWire Port

SpaceWire Port

PC

I Bu

s

PCI Bus

PCI Bus PCI Bus

PCI Bus

SpaceWire Port 1

SpaceWire Port 2

SpaceWire Port 3

SpaceWire Port 8

SpaceWire Port 9

SpaceWire Port 10

SpaceWire Port 5

SpaceWire Port 6

SpaceWire Port 7

SpaceWire Port 4

SpaceWire Port 12

SpaceWire Port 11SpaceWire Port 13

SpaceWire Port 14

SpaceWire Port 15

SpaceWire Port 16

RAD750Evaluation

Board

PCI Bus

Multiple Evaluation Boards may be combined to breadboard router

Performance with more oorts than a single ASIC

Page 13: EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS

Components II Session - Marshall Paper - Page 13 5 November 2008Approved for public domain release (N68936-05-C-0066 on 10-10-2008)

© 2008 BAE Systems - All rights reserved

Next Generation ASIC Block Diagram

Integrates SpaceWire with RAD750 Interfaces

Page 14: EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS

Components II Session - Marshall Paper - Page 14 5 November 2008Approved for public domain release (N68936-05-C-0066 on 10-10-2008)

© 2008 BAE Systems - All rights reserved

RAD6000MC ASIC block diagram

On-chip bus (OCB) connection medium

Embedded microcontroller

(EMC)

64

OCB master

64

OCB slave

64 KB SRAM

Memory

OCB Slave

64 KB SRAM

memory

OCB slave

6464

programmable interrupt discretes

(PIDs)

MISC

32

OCB slave

JTAG

32

OCB slave

JTAG master (JTAG)

33 MHz PCI 2.2

64 64

OCB master

OCB slave

PCI-64

clocks/reset

Clock and test (CAT)

32

PLL

OCB slave

JTAG

32

OCB master

JTAG slave (JTAG)

Memory

RAD6000MCTM

microcontroller ASIC

I/O

RAD6000TM

microprocessor

COP

OCB slave

32

COP master

33/66MHz

1553 A/B

64

OCB slave

D1553 core

64 KB SRAM

UART

UART

32

OCB slave

up to 48 external analog inputs

Analog multiplexer

12-bit A/Dconverter

OCB master

OCB slave

64 3264

Analog I/O control (AIC)

OCB master

Three 12-bit D/A converters

3 external analog outputs

SpaceWire router

and four(4) links

SpaceWire I/F x4

64

OCB master

32

OCB slave

64

Router I/F (RIF)

OCB master

FIF

O

FIF

O

OCB master

OCB slave

64 3264

Router I/F (RIF)

OCB master

FIF

O

FIF

O

32 KB C-RAMTM

memory

64

OCB slave

Reused

New

Minor modMajor mod

DDC IP

external memory

Memory control (MCTL)

64 3264

OCB master

OCB slave

OCB master

Direct memory access (DMA)

Local interface function (LIF)

64

OCB slave

OCB master

64 64

OCB slave

On-chip bus (OCB) connection mediumOn-chip bus (OCB) connection medium

Embedded microcontroller

(EMC)

64

OCB master

64

OCB slave

Embedded microcontroller

(EMC)

64

OCB master

64

OCB slave

64 KB SRAM

Memory

OCB Slave

64 KB SRAM

memory

OCB slave

6464

64 KB SRAM

Memory

OCB Slave

64 KB SRAM

memory

OCB slave

6464

programmable interrupt discretes

(PIDs)

MISC

32

OCB slave

programmable interrupt discretes

(PIDs)

MISC

32

OCB slave

JTAG

32

OCB slave

JTAG master (JTAG)

JTAG

32

OCB slave

JTAG master (JTAG)

33 MHz PCI 2.2

64 64

OCB master

OCB slave

PCI-64

33 MHz PCI 2.2

64 64

OCB master

OCB slave

64 64

OCB master

OCB slave

PCI-64

clocks/reset

Clock and test (CAT)

32

PLL

OCB slave

clocks/reset

Clock and test (CAT)

32

PLL

OCB slave

JTAG

32

OCB master

JTAG slave (JTAG)

JTAG

32

OCB master

JTAG slave (JTAG)

Memory

RAD6000MCTM

microcontroller ASIC

I/O

RAD6000TM

microprocessor

COP

OCB slave

32

COP master

I/O

RAD6000TM

microprocessor

COP

OCB slave

32

COP master

33/66MHz

1553 A/B

64

OCB slave

D1553 core

64 KB SRAM

1553 A/B

64

OCB slave

D1553 core

64 KB SRAM

UART

UART

32

OCB slave

UART

UART

32

OCB slave

up to 48 external analog inputs

Analog multiplexer

12-bit A/Dconverter

OCB master

OCB slave

64 3264 64 3264

Analog I/O control (AIC)

OCB master

Three 12-bit D/A converters

3 external analog outputs

SpaceWire router

and four(4) links

SpaceWire I/F x4

64

OCB master

32

OCB slave

64

Router I/F (RIF)

OCB master

FIF

O

FIF

O

64

OCB master

32

OCB slave

64

Router I/F (RIF)

OCB master

FIF

O

FIF

O

FIF

O

FIF

O

OCB master

OCB slave

64 3264

Router I/F (RIF)

OCB master

FIF

O

FIF

O

OCB master

OCB slave

64 3264 64 3264

Router I/F (RIF)

OCB master

FIF

O

FIF

O

FIF

O

FIF

O

32 KB C-RAMTM

memory

64

OCB slave

32 KB C-RAMTM

memory

64

OCB slave

Reused

New

Minor modMajor mod

ReusedReused

NewNew

Minor modMinor modMajor modMajor mod

DDC IP

external memory

Memory control (MCTL)

external memory

Memory control (MCTL)

64 3264

OCB master

OCB slave

OCB master

Direct memory access (DMA)

64 3264

OCB master

OCB slave

OCB master

Direct memory access (DMA)

OCB master

OCB slave

OCB master

Direct memory access (DMA)

Local interface function (LIF)

64

OCB slave

OCB master

64 64

OCB slave

Local interface function (LIF)

64

OCB slave

OCB master

64 64

OCB slave

Integrates SpaceWire with Embedded RAD6000

Page 15: EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS

Components II Session - Marshall Paper - Page 15 5 November 2008Approved for public domain release (N68936-05-C-0066 on 10-10-2008)

© 2008 BAE Systems - All rights reserved

Core-Based ASIC Evolution

ProductEnhanced Power

PCI ASIC SpaceWire ASICNext Generation

Bridge ASIC

RAD6000 Microcontroller

ASICParameterExternal Processor Interface 60X I/F (RAD750) No 60X I/F (RAD750) NoInternal Processors EMC EMC EMC RAD750, EMCInternal SRAM 32KB 32KB 96 KB 192 KBInternal C-RAM No No No 32 KBExternal Memory I/F 2 GB 2 GB 2 GB 2 GBDMA Controller Yes Yes Yes YesSpaceWire Ports No 4 x 264 MHz 4 x 320 MHz 4 x 320 MHzSpaceWire Router No 7 Port 7 Port 7 PortSpaceWire PLL No Yes Yes Yes1553 Interface No No Yes YesAnalog to Digital Converter No No No 12 bit, 8.25 MspsDigital to Analog Converter No No No 3 x 12 bit, 1 KspsAnalog Multiplexor No No No 48 inputPCI Bus 32 bit 2 x 32 bit 32 & 64 bit 64 bit JTAG Interfaces Master & Slave Master & Slave Master & Slave Master & Slave16550 Compatible UART Yes Yes Yes YesProgrammable Timers and Discretes Yes Yes Yes YesStatus Flight Flight Prototype Design

Continuing Evolution of Core-Based ASICs for Processing Applications

Page 16: EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS

Components II Session - Marshall Paper - Page 16 5 November 2008Approved for public domain release (N68936-05-C-0066 on 10-10-2008)

© 2008 BAE Systems - All rights reserved

Summary

• BAE System’s 4 Port SpaceWire ASIC, a core based system on a chip, is a key component of the LRO SBC and Mini-RF Payload

• The Mini-RF Control Processor utilizes SpaceWire for C&DH communications and high performance control of the Mini-RF Payload

• Software is self-contained and was built on full set of SpaceWire and RAD750 building blocks

• Evaluation Board has been developed that may be used to breadboard SpaceWire applications using the SpaceWire ASIC

• SpaceWire cores being combined with RAD750 and RAD6000 families for highest performance processing and standalone instrument applications as part of evolution of our system on a chip devices

Page 17: EVOLUTION AND APPLICATIONS OF SYSTEM ON A CHIP SPACEWIRE COMPONENTS FOR SPACEBORNE MISSIONS

Components II Session - Marshall Paper - Page 17 5 November 2008Approved for public domain release (N68936-05-C-0066 on 10-10-2008)

© 2008 BAE Systems - All rights reserved

Questions? [email protected]