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Aim:

The aim of this project is to design a 3-bit even parity generator that can detect a one-bit

error in a message and draw the CMOS layout in L-dit! which can then be simulated

using "S"#C$

Abstract:

%n even parity bit generator generates an output of & if the number of '(s in the input

se)uence is even and ' if the number of '(s in the input se)uence is odd$ The chec*er

circuit gives an output of & if there is no error in the parity bit generated$ Thus it basicallychec*s to see if the parity bit generator is error free or not$

Schematic:

The design procedure is made simple by writing the truth table for the circuit$

Truth table:

Message Even parity bit Checker bit

X Y Z P C

& & & & &

& & ' ' &

& ' & ' &

& ' ' & &

' & & ' &

' & ' & &

' ' & & &

' ' ' ' &

The circuit can now be derived by drawing the +-map for the output$

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,rom this the minimal output e)uation is ZYXZYXXYZZYXZYXP =+++=

This function can be implemented using eclusive-or gates$ The schematic of the parity

generator circuit is shown in ,igure '$

Figure : Parity bit generat!r

Similarly the chec*er circuit can be designed using .O/ gates! where

PZYXC = and the circuit is shown in ,igure 0$

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Figure ": Checker circuit

1ow the parity bit generator and the chec*er circuit can be combined into one circuit for

simplicity$ The final schematic of the circuit is shown in ,igure 3$

Figure #: C!mbine$ schematic !% b!th parity bit generat!r an$ checker circuit

The final layout consists of four .O/ gates! which can be designed! in L-2#T using the

CMOS technology$ The basic building bloc*s in CMOS technology are MOS,T(s$ %

MOS,T is a metal oide semiconductor field effect transistor$ The advantages of

MOS,T over 4T(s are! they are smaller in si5e and the drain and source terminals are

interchangeable$ This provides the designers with area minimi5ation on the chip$

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S!%t&are use$:

'$ L-2#T student version for drawing the layouts$

0$ "S"#C for simulating the layouts$

'asic buil$ing bl!cks:

MOS,T(s are the basic building bloc*s$ There are three main components to a CMOS

transistor$ The Source and 2rain can be interchanged at the silicon level and

occasionally at the device level$ These are the main current carrying terminals$ The 6ate

is separated from the Composite 7Silicon8 by a thin layer of SiO0! which acts as an

insulator or dielectric$ #n the CMOS world you can create a Capacitor by shorting the

Source and 2rain together calling that one terminal! and using the 6ate for the otherterminal$ The difference between an 1MOS and a "MOS device depends on the type of

9LL 7base8 the transistor is sitting in$The layout of a p-channel MOS,T drawn in L-

dit is shown in ,igure :$ Layout of a MOS,T using L-dit is very straightforward$ %n

n-channel device is constructed by creating an n; region ndiff defined by

n$i%% ( )ACT*+E, %12 )-SE.ECT,

% P/.Yover n$i%%creates the transistor$ The drawing steps for creating the n,T are as

follows$

'$ Construct an ACT*+Ebo

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Figure 0: nM/SFET

,igure > shows that nMOS,T is constructed without violating any design

rules$

Figure 1: 23C %ile %!r Figure 0

,igure ? is the traction definition file for the layout in ,igure :$

Figure 4: E5tract $e%initi!n %ile %!r lay!ut in Figure 0

>

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% p-channel MOS,T follows the same basic order! ecept that the n-well must be

defined$ The steps are@

'$ Create an -6E..region for the pMOS,T$

0$ Construct an ACT*+Ebo$ "rovide an ACT*+Eand -SE.ECTbo within -6E..for the n-well contact

7to A228

1ote that the n; contact formed in step > is needed to bias the n-well to the power supply

voltage$

,igure B shows the layout of a pMOS,T$ 2esign is constructed se)uentially by

performing 2/C at each stage$

Figure 7: pM/SFET

,igure shows the 2/C file for a pMOS,T$ %ll design rules are obeyed$

Figure 8: 23C %ile %!r Figure 7

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,igure D shows the etraction definition file for the layout in ,igure B$

Figure 9: E5tract $e%initi!n %ile %!r lay!ut in Figure 7

The definition files are etracted using the morbn0&$et file! which gives the information

about the transistors and the corresponding nodes and parasitic capacitances$ This is used

as a netlist in the "S"#C to generate the output waveform$

Pr!ce$ure:

%ny layout in L-dit can be drawn using these two transistors$ #n this project! four .O/

gates are needed which can be built from the basic transistors$ #t is important to

understand the schematic of an .O/ gate$ % simple .O/ gate can be built using two

inverters and two transmission gates$

CMOS Inverter:

The schematic of a CMOS inverter circuit is shown in ,igure '&$ #t consists of a p-,T

and an n-,T connected bac* in the form of a complimentary pair$ The gates of the two

transistors are connected to the input pulse and the inverted output pulse is obtained at the

point where the source of the p-,T is connected to the drain of the n-,T$ 9hen the

B

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input pulse is at & level! the p-,T turns O1 and the 2C voltage A22is observed at the

output$ 9hen the input is at =#6= level! the n-,T turns O1 and the ground voltage & is

observed at the output$

Figure : CM/S *nverter

The layout of an inverter in L-dit is shown in ,igure ''$

Figure : *nverter lay!ut

The $S"C file is etracted from this layout! which is shown in ,igure '0$ This file

indicates that there are two transistors in the layout i$e$! M' and M$ The line M' '' 3 '&

"MOS indicates the nodes for the p-MOS,T in the order 2rain 6ate Source$ y

observing the node numbers for both the transistors we can say that node 3 is the

"MOS

1MOS

A22

ASS

AOETA#1

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common gate where the input pulse is to be given and node '& is the common point

where output is obtained$ Aoltage A22is given at node '' and A SSis given at node D$ y

using this information a $C#/ file can be created wherein the values for these voltages are

specified at corresponding nodes$

Figure ": ;SPC %ile %!r inverter

The $cir file for an inverter is shown in ,igure '3$

D

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Figure #: ;C*3 %ile %!r an inverter

The lines A22 '' & 2C > and A612 D & 2C & indicate the voltages between the starting

node and ending node and 2C specifies the type of voltage given$ The general format of

these lines can be written as

Node_ name starting_node ending_node voltage_type value

The net line in the $cir file indicates the pulse voltage given at the input$ The general

format for this type of input is

Node_ name starting_node ending_node PULSE (low_value high_value td tr t tp !"

=ere tdis the time delay! tris rise time! tfis fall time! tpis the pulse width and T is the

time period of the pulse$ L-edit consists of a file SC1%$S"C which defines the dot model

parameters for the transistors$ This file has to be included in the $cir file$ Lastly! #!$%N

&ns &'nsindicates the type of simulation i$e$! in this case it is the transient analysis$ The

general format for this is

#!$%N step_sie simulation_time

,inally the #P$)*Eline specifies the output probe in the layout$ This file is compiled in

the "S"#C %F2$ The input and the output pulses are observed by running the probe in

"S"#C$ The "S"#C simulation of the inverter is shown in ,igure ':$

Figure 0: PSP*CE simulati!n !% an inverter

'&

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Transmission gate:

% transmission gate consists of a "MOS and an 1MOS connected in a way that input is

transmitted in one condition and bloc*ed in other condition$ The schematic of a

transmission gate is shown in ,igure '>$

Figure 1: Transmissi!n gate schematic

The operation of a transmission gate is as follows@ when S is LO9! both "MOS and

1MOS are O,, and the input % is not transmitted to the other end$ 9hen S is =#6=!

both "MOS and 1MOS are O1 allowing % to pass through the gate$ ,igure '? shows the

layout of a transmission gate in L-dit$

Figure 4: .

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The etraction and simulation steps are the same for every layout and thus are repeated

for the transmission gate$ The $cir file and the "S"#C simulation of the transmission gate

are shown in ,igures 'B and ' respectively$

Figure 7: ;cir %ile %!r transmissi!n gate

Figure 8: PSP*CE simulati!n !% transmissi!n gate

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XOR gate using inverters and transmission gates:

The .O/ gate consists of two inverters and two transmission gates$ The schematic of

.O/ gate is shown in ,igure 'D$

Figure 9: Schematic !% X/3 gate

The layout of .O/ gate in L-dit is drawn by creating the basic cells$ The transistors are

used as instances in drawing the layouts of inverter and transmission gates$ This feature is

available in L-dit in the cell menu$ The cells are then flattened$ 1ow by using the

inverter and transmission gate as instances the .O/ layout is completed$ ,igure 0&

shows the layout of .O/ gate in L-dit$ Two inverters are used since we need both %(

and ( in the .O/ function$ The $C#/ file in ,igure 0' shows that there are transistors

in the .O/ gate$ The output of an .O/ gate is & when both the inputs are same$ This can

be observed in the "S"#C simulation waveforms obtained for this layout$ The

waveforms are shown in ,igure 00$

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Figure ": .ay!ut !% X/3 gate in .

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Figure "#: .$'3 < tract A0$&? I

G T2 ,ile C@J"%/#TK! Cell Cell&! tract 2efinition ,ile C@JMO/10&$et I

C'B ''D & 3'$0D',,C' ''0 & 3'$0D',,

C'D '&> & 3'$0D',,

C0& DD & 3'$0D',,C3B '03 & 3&$3&3,,C3 '00 & 3&$3&3,,

C3D '0' & 3&$3&3,,C:& '0& & 3&$3&3,,

C:' '' & ':$&?>,,C:0 ''? & ::$&,,

C:3 ''> & 0B$&>B,,C:: ''3 & '?3$:B3,,

C:> ''' & ':$&?>,,C:? '&D & :$3B0,,C:B '& & 0B$&>B,,C: '&? & 0&$DD?,,

C:D '&: & ':$&?>,,C>& '&0 & ?&$??,,

C>' '&' & 0B$&>B,,C>0 D & ':$&?>,,

C>3 D? & 0B$&>B,,C>: D: & 0&$DD?,,

M' ''D '&D '' : "MOS L0E 9':E

M0 ''3 '&D ''? B "MOS L0E 9'3EM3 ''> '' ''? '' "MOS L0E 9'3EM: ''D ''3 ''> '> "MOS L0E 9':EM> ''0 '&0 ''' 'D "MOS L0E 9':E

'?

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M? '&? '&0 '&D 00 "MOS L0E 9'3E

MB '& ''' '&D 0? "MOS L0E 9'3EM ''0 '&? '& 3& "MOS L0E 9':E

MD '&> '&? '&: 33 "MOS L0E 9':EM'& ''3 '&? '&0 3? "MOS L0E 9'3E

M'' '&' '&: '&0 :& "MOS L0E 9'3EM'0 '&> ''3 '&' :: "MOS L0E 9':E

M'3 DD :B D : "MOS L0E 9':EM': D: :B ''3 >' "MOS L0E 9'3E

M'> D? D ''3 >> "MOS L0E 9'3EM'? DD D: D? >D "MOS L0E 9':EM>B '03 '&D '' D3 1MOS L0E 9'3EM> ''> '&D ''? D3 1MOS L0E 9'3E

M>D ''3 '' ''? D3 1MOS L0E 9'3EM?& '03 ''3 ''> D3 1MOS L0E 9'3EM?' '00 '&0 ''' D3 1MOS L0E 9'3EM?0 '& '&0 '&D D3 1MOS L0E 9'3E

M?3 '&? ''' '&D D3 1MOS L0E 9'3EM?: '00 '&? '& D3 1MOS L0E 9'3EM?> '0' '&? '&: D3 1MOS L0E 9'3EM?? '&' '&? '&0 D3 1MOS L0E 9'3E

M?B ''3 '&: '&0 D3 1MOS L0E 9'3E

M? '0' ''3 '&' D3 1MOS L0E 9'3EM?D '0& :B D D3 1MOS L0E 9'3EMB& D? :B ''3 D3 1MOS L0E 9'3E

MB' D: D ''3 D3 1MOS L0E 9'3EMB0 '0& D: D? D3 1MOS L0E 9'3E

$MO2L 1MOS 1MOS LAL0 L2&$0>&&&&E TO.:'B$&&&&&-'&; 1SE?$'&?'D;': ATO&$0>&& +":$D'D&&&-&> 6%MM%&$'B0; "=#&$? EO>D: E."?$?00B>-&0 EC/#T>&&&

; 2LT%>$&3& AM%.?>>:B$3 .4&$0>&&&&E L%M2%?$?3?'DB-&3; 1,S'$D;'' 1,,' 1SS'$&&&&&&;'& T"6'$&&&&&&; /S=30$B:&&&& C62O3$'&>3:>-'& C6SO3$'&>3:>-'& C6O3$:>3&-'&; C4D$:D:D&&-&> M4&$:B&DD C4S9:$:'&'&&-'& M4S9&$33:&?& "&$&&&&&

$MO2L "MOS "MOS LAL0 L2&$00B03?E TO.:'B$&&&&&-'&

; 1SE'$&>?'0:;'? ATO-&$D3B&: +"'$B3'&&&-&> 6%MM%&$B'>; "=#&$? EO0&D E."&$0333' EC/#T:B>&D$D

; 2LT%'$&B'BD AM%.'&&&&& .4&$0>&&&&E L%M2%:$3D':0-&0; 1,S3$0B;'' 1,,'$&&' 1SS'$&&&&&&;'& T"6-'$&&&&&&; /S=B0$D?&&&& C62O0$00>>-'& C6SO0$00>>-'& C6O>$0D03B>-'&; C43$00:0&&-&: M4&$>:D>? C4S90$DBD'&&-'& M4S9&$3'&&B "&$&&&&&

$T/%1 0ns 0&ns

$"/O$12

Figure "0: ;C*3 %ile %!r the parity bit generat!r=checker

Applicati!n !% parity bit generat!r circuit:

"arity bit generator is used in digital communications where the messages are transmitted

in the form of '(s and &(s$ #n communications! a message has to be transmitted between

two points without any loss or errors$ This is done by chec*ing the message bits at the

'B

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