Even Counter

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BATANGAS STATE UNIVERSITY College of Engineering, Architecture and Fine Arts ECE/ICE/MEXE Department ECE 409 - Digital Principles and Logic Design Homework Submitted By: Marzo, Shintaro D. Submitted to: Engr. Ralph Gerard B. Sangalang

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Transcript of Even Counter

Page 1: Even Counter

BATANGAS STATE UNIVERSITYCollege of Engineering, Architecture and Fine ArtsECE/ICE/MEXE Department

ECE 409 - Digital Principles and Logic DesignHomework

Submitted By:Marzo, Shintaro D.

Submitted to:Engr. Ralph Gerard B. Sangalang

September 17, 2015

Page 2: Even Counter

Design a counter that counts consecutive even numbers from 0 to 98.SolutionI approach the problem by intuition, having 2 outputs to show through seven segment displays, the tens and ones digit via 7447 (BCD to Seven Segment Decoder). The ones digit must show only 0, 2, 4, 6, 8 and resets. The tens digit will count up when the ones digit resets or when it transitions from 8 to 0. The easiest way to do this is to use 7493 to work as a BCD counter by connecting the reset pins to QD and QB. What happens is that, when the counter is supposed to count ‘1010’ (10) it will reset to ‘0000’ making the last count before it resets is ‘1000’ (8) for ones digit and ‘1001’ for tens digit.For the ones counter, I connected the input clock ‘A’ to its output ‘QA’ so that it will always be ‘0’ because the counter is supposed to count even numbers. The output QD of this counter will serve as the input clock for the tens counter. This counter is triggered by negative edge which means that when the ones counter resets, the tens counter will count up, thus a counter that counts consecutive even number from 00 to 98.

Page 3: Even Counter

Inside 7493

TIMING DIAGRAM

Page 4: Even Counter

Tens 0 1 2 3 4 5 6 7 8 9 0

Ones 0 2 4 6 8 0 2 4 6 8 0 2 4 6 8 0 2 4 6 8 0 2 4 6 8 0 2 4 6 8 0 2 4 6 8 0 2 4 6 8 0 2 4 6 8 0 2 4 6 8 0