Application Note 1258

Evaluating Tributary Jitterfrom the SDH Network

2

3

The network architecture

In the long term, the synchronousSDH network may develop tothe state where asynchronousnetworks will only exist at theperiphery of the synchronousnetwork, and all transport throughthe network is on SDH. However,this is an ideal model that may notbe prevalent until well into thenext century. At present,and during this intervening periodas the SDH network evolves,the hybrid synchronous/asynchro-nous network will predominate.Thus a signal may experienceseveral synchronous/asynchro-nous conversions during itspassage through the network.

As SDH equipment is installed inthe network, SDH islands willappear. Initially, these SDHislands are likely to be point-to-point networks. As the SDHportions of the network increase,these islands will merge to formlarger more sophisticated islandsconsisting of not only PathTerminating Equipment (PTE) butalso Add/Drop Multiplexers(ADM), Digital Cross-connectSystems (DCS), etc. As thetributary signal traverses theselarger SDH islands as part of anVC, phase and/or frequencydifferences between SDH networkelements will induce pointeractivity in the SDH signal.

Introduction

The innovation of using pointersto track the position of the VirtualContainer (VC) within SDHsignals has produced manybenefits that will minimize thecost and complexity of networkequipment. For example, SDHremoves the need for back-to-backmultiplexers/demultiplexers incross-connects and add/dropmultiplexers by enabling anycustomer payload to be locatedand tracked without the need todismantle the multiple layers ofhierarchy within the structure.However, due to the large inherentphase step associated with apointer movement (ie, 24UI perAU-4 pointer movement), com-pared to that produced by pulsestuffing techniques used in asyn-chronous multiplexing, the SDHnetwork has the potential ofcreating large jitter transients inthe demultiplexed tributaryoutputs. The need to characterizethe jitter performance ofdemultiplexers is being consid-ered by Standards Committeessuch as ITU Study Group 13 at thetime of writing (April 1994).

The impact of this pointer activitywill be to increase the jitter on theasynchronous tributary signalpassing out of the SDH island.This will produce an accumulationof jitter on the tributary signal asit traverses the multiple islands inits transmission path.

For the long term network devel-opment scenario, (when end-to-end SDH transmission is preva-lent), the jitter performance of theterminating PTE will be the maincontributor to jitter on thedemultiplexed tributary signal.However, until reaching this stageof development, the networkwill become filled with SDHislands. A tributary signal’stransmission path may involvetraversing multiple SDH islands,and the problem of jitter accumu-lation will exist.

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In order to achieve this with the32 island model, the maximumjitter from a PTE is limited to1.3UI. Table 1 shows how thisbudget has been allocated be-tween mapping jitter, singlepointer movements and degradedsynchronization conditions.

Characterization of jitterperformance

G.783 presently includes pointertest sequences [3]. These se-quences are aimed to emulateexpected network degradations.

During 1992, Telecom Canadacarried out testing to verify thetheoretically predicted responsesto various types of pointer activityon PTEs [4]. As well as verifyingthe theoretically predicted re-sponses to variations in pulsestuffing ratios (used to map thetributary signal into the VC), andto single pointer movements,Telecom Canada also showed thatthe defined tests did not fullyrepresent the pointer sequencesthat a real network mightproduce.

With the results from the practicalexperimentation and the specifica-tion of jitter performance in termsof three network conditions, (anexample of which is shown inTable 1), ANSI have reviewed thepointer movement sequences [5].The aim was to produce tests thatmore closely emulated realnetwork conditions and also allowmeasurement of the specifiedjitter thresholds.

Analysis of the network

In order to specify the jitter limitson a PTE, analysis has beenperformed to predict the expectedjitter accumulation that mightoccur as a tributary signal passesthrough multiple SDH islands. Theobjective of this study is toproduce a model that represents apractical worst-case example of anetwork that may be used totransfer a PDH signal. {A similarstudy carried out by Bellcore forthe SONET world produced a 32SONET island model, each ofwhich contains 10 pointerprocessing nodes [1], (Figure 1).}

To ensure that the jitter accumula-tion does not cause servicedegradation at the output of thelast SDH island, the totalnetwork jitter must not exceedthat specified for the tributaryrate [2]. Therefore, each PTE mustnot only meet this specificationbut will have to exhibit a farbetter performance if the jitter atthe output of the last SDH islandis to meet this requirement.

Once the size and structure of thenetwork model has been agreed,the allocation of the amount ofjitter which can be generatedby the various jitter-producingeffects will be performed toensure that the total network jitterdoes not exceed the specifiedlimit on a tributary signal. As anexample of the order of magnitudethat is likely to be settled upon,ANSI tackled a similar problemfor the DS3 interface whichrequires that the peak-to-peakjitter shall not exceed 5UI, (in the10Hz to 400 kHz range).

Also, as a further result of theexperimentation, it has becomeclear that test methodologyguidelines need to be produced inorder to achieve accurate andrepeatable results.

Liasion between ANSI and ITU hasprompted ITU to also review thepointer test sequences. StudyGroup 13 is, at the time of printing,considering how the sequence inG.783 should be expanded/modi-fied.

5

Figure 1: Hybrid network model produced for the transfer of DS3 through a SONET Network. ITU Study Group 13 is investi-

gating the generation of a similar model for each of the CEPT rates.

Table 1: ANSI jitter specification for a DS3 signal demultiplexed from a single SDH/SONET island.

Jitter category Jitter allocation

(UI p-p)

Mapping jitter A0 0.40(Note 1)

Single isolated A1 A0 + 0.30pointer

Degradedsynchronization A2 1.3conditions

Notes

1. Jitter from a SONET island in which

there is no pointer activity.

2. The DS3 will be jitter free as it enters

the SONET island.

Island 1

Pointer Processing

OC-N OC-N

Ptr

Adj

D

DSONET

Island DSONET

Island

Jitter

DS3

Network

Output Jitter

DS3A

Jitter

Free

A- Asynchronous Network M - Mapper

D - Desynchronizer

MM

Island 2 Island 32

A

A

Jitter

M

6

Figure 2(a) : Single isolated pointer test.

Figure 2(b): Burst-of-3 test.

The new test sequences

The test sequences developed byANSI have already been acceptedfor inclusion in G.783 for theNorth American portions of SDH.It is likely that similar networkscenarios will be considered bythe Study Group in order toproduce test sequences for theCEPT-mapped signal.

The first of the new testsequences was developed toemulate the situation when thereis no pointer activity. This testrequires the frequency of thetributary signal to be varied tofind the maximum jitter produceddue to the pulse stuffing ratioused to map the tributary signalinto the VC, ie, Mapping Jitter.

This test checks the specificationof the maximum jitter on theoutput due to the process ofextracting the tributary signalfrom the VC.

The second criterion defines theresponse to a Single Isolated

Pointer movement. This is testedusing a sequence which has asingle pointer movement every30 seconds, Figure 2(a). Thepointer movements are spaced 30seconds apart in order to allowtime for the effects of each move-ment to completely die out beforeanother pointer movement isapplied. This ensures that theresultant jitter measured is thatproduced by a single pointermovement.

Two test sequences have beendefined to measure the perform-ance of a PTE in a Degraded

Synchronization Condition.

The first test emulates the net-work condition where phase noisein a chain of network elements(eg, ADMs, cross-connects, etc)accumulates to produce a burst ofpointers with minimum spacing.

Figure 2(b) shows the test definedto cover this condition. Like thesingle pointer test, the bursts areset 30 seconds apart to allow timefor the effects of each burst to dieout before the next burst isapplied.

The second test emulates thenetwork condition when theoriginating PTE loses lock to thesystem clock. This condition willcause continuous pointer move-ments to be generated. On top ofthis background, extra pointeractivity may occur due to phasenoise from the other nodes of anetwork. Therefore, on top of thebackground of continuous pointermovements, an added or canceledperturbation to the backgroundsequence is performed every30 seconds.

Initialization Cooling DownMeasurement 1

(30 s)

Measurement 2

(30 s)

Measurement 3

(30 s)

Single

Pointer

Movement

Initialization Cooling DownMeasurement 1

(30 s)

Measurement 2

(30 s)

Measurement 3

(30 s)

500 µµs500 µµs

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In the original sequences, theclock synchronization loss wasrepresented by continuous evenlyspaced pointer movements.However, this is not always thecase in practice. Experimentationhas shown that gaps are generatedin the pointer sequence due to theeffects of the positioning of theSDH overhead bytes. For exam-ple, when an VC-4 is cross-con-nected, a repetitive sequence of87 evenly spaced pointer move-ments followed by a gap equiva-lent to 3 missing pointer move-ments is generated. Table 2shows the effect on the jitteroutput from the 87/3 sequencecompared to that produced by theoriginal G.783 test.

Similar effects can be predictedfor all types of SDH VCs. It ispossible by the use of sophisti-cated pointer processing nodes toremove this effect and produceregular, evenly spaced pointermovements. However, this is notspecified as a requirement for thenetwork equipment, and as themost straight forward techniquesproduce this effect, PTEs willhave to be designed to cope withthis sequence.

Figure 2(c) shows the new se-quence that has been defined toemulate the clock synchronizationloss condition for DS3 testing.

Figure 2(c): Periodic pointer adjustment test sequence.

Table 2:

Experimental results showing effect of

87/3 sequence.

Jitter on

Pointer demultiplexed DS3

sequence (UIp-p)

G.783 test: regular pointers 0.15 with one missing pointer

87/3 sequence 0.60

Notes

1. In both cases, the pointer spacing

was set at 33 ms, equivalent to a

frequency offset of 4.6 ppm.

2. The results were obtained by testing

the DS3 drop port from the

HP 37704A SONET test set.

87 3

T

86 4

AAAAAAAAAAAA

AAAAAAAAAAAA

AAAAAAAAAAAA

AAAAAAAAAAAA

AAAAAAAAAAAA

AAAAAAAAAAAA

AAAAAAAAAAAA

AAAAAAAAAAAAGroup A Group A Group AGroup A

Initialization Cooling Down Measurement 1

≥≥ 30 s

Measurement 2

≥≥ 30 s

Measurement 3

≥≥ 30 s

Measurement 10

≥≥ 30 s

44Additional Pointer

Adjustment 43 3

Pointer

Adjustment

Absent Pointers due to

Section Overhead

Pattern 2Pattern 3

Cancelled Pointer

Adjustment

t = 500 µµs

AAAAAAAAAAAA

AAAAAAAAAAAAGroup A

Pattern 2 or 3 Pattern 1Pattern 1 Pattern 1Pattern 1

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Figure 4: PTE test configuration.

Figure 3: Typical block diagram of a E3 PTE.

MTS

Clock

SDH Test Set

SDH Test Set

Test Signal

Test Signal

PTE Under Test

PTE Under Test Jitter Test Set

Jitter Test Set

Clock Extracted

and used to lock

Test Signal

HP 37717A

HP 37717A

HP 37724A

HP 37724A

E3

E3

CLK

RX

STM-n

TX

E3

TX

STM-n

MTS

CLK

RX

E3

RX

STM-n

TX

E3

TX

STM-n

RX

E3

TX

STM-n

RX

STM-n

TX

STM-n

RX

STM-n

a) Synchronize Test Set to PTE by frequency locking Test

Set's Transmitter to the MTS Clock used by PTE.

b) Synchronize Test Set to PTE by frequency locking Test Set's

Transmitter to the Clock extracted from the SDH

signal generated by the PTE.

Path Terminating Network Element

Receive

STM-n

Drop

E3

Front-End

Pointer

Processing

Block

E3

Demultiplexer

Block

Internal

STM-n

Internal

STM-1

Oscillator

Recovered

E3 Clock

9

The second effect of this structurecomes from the elastic storewhich will be present in the front-end pointer processing block.This store will absorb some of thepointer activity in the receivedSTM-n signal before producingany pointer movements in theinternal STM-n signal. (Cases havebeen observed where as many as15 movements are absorbed.)If a pointer sequence test isperformed, it is necessary toprime this elastic store to ensurethe pointer sequence applied tothe PTE is that which appears atthe input to the demultiplexerblock. (This can be achieved byapplying a test signal containingcontinuous pointer movements ofthe same polarity as those usedduring the testing until jitterspikes are detected on the tribu-tary output each time a pointermovement occurs in the testsignal.)

Summary

By tightly specifying the jittergenerated by PTEs before thereis significant deployment of SDHequipment, network operators canavoid major problems once themultiple SDH island scenariobecomes a reality. The definitionof sequences which simulate realnetwork conditions, accompaniedby test methodology guidelines,will allow network operators togain confidence that equipmentthey are installing in their net-works will interwork with theexisting asynchronous networksboth now and in the future.

Test methodology

As a side-effect of the practicalexperimentation being carriedout, it became clear that there wasa need to clarify the testmethodology in order to obtainaccurate and repeatable measure-ments. Factors like the number ofrepetitions of each pointersequence test are beingconsidered to produce implemen-tation guidelines for each testsequence. Two of the mostimportant requirements arise fromthe structure of the PTEs avail-able today.

By testing PTEs, it has been foundthat many contain front-endpointer processing blocks thatextract the VC-n from the receivedsignal and pass it into an inter-nally generated STM-n before thesignal is demultiplexed to extractthe tributary signal, Figure 3.

For effective testing of a PTEwith this architecture, it is impera-tive that the frequency of theinternal STM-n signal is locked tothe frequency of the test signalbeing applied to the PTE.If this is not accomplished,frequency and/or phase differ-ences between the two STM-nsignals will produce pointeractivity on the internal STM-nsignal. These pointer movementswill produce spurious spikes ofjitter on the tributary signal.Figure 4 shows two possible testconfigurations which will synchro-nize the test signal to the PTE andhence avoid this problem.

References

1. T1X1.2, “SONET HypotheticalReference Circuit (HRC)",T1X1.2/93-015, March 1993.

2. ITU Recommendation G.823, " The Control of Jitter and

Wander within Digital Net-works which are based on the2.048 Mbit/s Hierarchy".Vol III - Fascicle III.5, BlueBook.

3. Revised RecommendationG.783, CCITT COM XV-R110-E, Nov'92.

4 K. Mahon, “Significance ofTelecom Canada’s SONETJitter Accumulation Measure-ments”, Telecom Canada,T1X1.3/92-129, November 1992.

5. ANSI, "Synchronous OpticalNetwork (SONET): Jitter atNetwork Interfaces", T1X1.3/93-006R3, Aug. '93.

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Figure A1: Typical SDH transmission network.

An SDH network

Figure A1 shows a typical SDHtransmission network. Thetributary signal, which in thisexample is an E4, enters thenetwork through path terminatingequipment (PTE). This elementmaps the E4 into an VC-4 in theSTM-n signal. At the far end, theterminating unit demultiplexes theSTM-n signal and reconstitutes theE4 tributary signal. Along theSDH transmission path, the STM-nmay pass through various SDHnetwork elements which arepointer processing nodes, eg,digital cross-connects.

At the entry point to the network,the frequency variations fromnominal E4 rate are catered for bypulse stuffing the E4 as it ismapped into the VC-4.

Network emulation modelfor a SDH test set

Introduction

The fundamental objective of anytest set transmitter is to repro-duce, in a controllable and repeat-able fashion, signals which aretrue representations of conditionsin a real network. To produce aSDH test set which meets thesecriteria when generatingSTM-n signals containing pointermovements, the concept of anetwork emulation model aids inhighlighting the important charac-teristics of such a signal.

There will be no pointer move-ments in the STM-n signal out ofthe first element, only variations inpulse stuffing rate (which handlesall frequency and phase varia-tions). Pointer movements areinduced in the transmission pathwhen an VC-4 is transferredbetween STM-n signals, ie, as itpasses through a network elementwhich is a pointer processingnode.

It is important to notice that whena pointer movement is induced inthe network, there is no effect onthe pulse stuffing ratio used tomap the E4 into the VC-4, (as thisis always defined at the entry pointto the SDH network). Therefore,the pulse stuffing ratio will remainconstant during any pointeractivity, with this ratio beingdefined by the long term averageVC-4 rate relative to the E4 rate.

E4STM-n

E4STM-n

PTE NE NE PTE

STM-n

Appendix A

11

Figure A2 : Test set emulation model.

Test set emulation model

The reduced network modelwhich must be emulated in orderto accurately reproduce signalscontaining pointer movements,consists of a PTE plus a networkelement which provides pointerprocessing functions. Figure A2shows the emulation model. Inthis model, the pulse stuffing rateis controlled by the relativefrequency of the E4 rate (f1) to theinternal STM-n line rate (f2). Therate of pointer additions is con-trolled by the relative frequency ofthe internal STM-n line rate (f2) tothe output STM-n line rate (f3).With this model, (as in the realnetwork), when pointer move-ments are introduced, there willnot be a step change in the pulsestuffing rate around the pointermovement to counteract theapparent step change in VC-4 rate.

The defined pointer testsequences consist of repetitivepatterns of pointer movements,all of which are the same polarity.This implies that an offset existsbetween the line rate (f3) and VC-4rate (controlled by f2). As thedefinition for the sequencesrequires that the line rate remainsconstant, the internal STM-n (f2)rate must change to generate thesepointer movements. Changing f2will also cause a step change inthe pulse stuffing ratio. A stepchange of this nature would notoccur in the network as linefrequencies are restricted bynetwork equipment specificationsfrom suddenly changing rate. Thecooling down period defined at thestart of the sequences providestime for the effects of the stepchange to die out before the jittermeasurements are performed.

Summary

By defining a test set transmitterin terms of a network emulationmodel, it is possible to highlight,and hence ensure reproduction ofthe important characteristics ofsignals containing pointer move-ments. This model clarifies theneed for the pulse stuffing processto be independent from the gen-eration of pointer movements.The implementation of this emula-tion model in a SDH test set willensure accurate production of thestimuli required to measure thetributary jitter performance of aterminating PTE.

E4 STM-nSTM-n

PTE NE

(Pointer

Processing

Functions)

Pulse Stuffing Rate controlled by f1 <-> f2

Pointer Movement Rate controlled by f2 <-> f3

f1 f2 f3

12

This means that if it is more than200 ms between the peak values,then the actual peak-to-peak jitterwill not be measured.

2. The bandwidth of the circuitused to recover the carrierfrequency is such that therecovered clock phase will tracktransients that last as long as thatshown in Figure B.2. When thissignal is compared to the inputsignal in order to measure thejitter, it will not be possible to seethe true magnitude of the jitter dueto the tracking effect in thereference clock being used.

This table clearly shows the needto test SDH demultiplexingequipment with test signals thatcontain pointer movements inorder to accurately characterize itsperformance.

Traditional jittermeasurement circuits

The jitter that has existed in PDHnetworks prior to the introductionof SDH has been sinusoidal innature. Jitter measurementcircuits, therefore, were producedthat were capable of accuratelymeasuring the peak-to-peak jitterof repetitive waveforms. FigureB.1 shows a typical measurementtechnique that requires the jitterwaveform to be repetitive.

The repetition rate of the jittertransients in the pure PDHnetwork was relatively high (eg,20 Hz for 2.048 Mbit/s). The carrierfrequency recovery circuit,therefore, would track any phasechanges at rates less than thisbandwidth.

SDH tributary jittercharacteristics

A single pointer movementequates to an instantaneous phasestep. This causes the output phaseof the desychronizer to respond ina similar manner to that shown inFigure B.2. Two effects stop thetraditional measurement circuitfrom giving a true measure of thepeak jitter:

1. Positive and negative peaksneed to occur within 200 ms ofone another, ie, the peak-to-peakvalue is the difference between thepositive reading and the negativereading during a measurementperiod.

Measuring tributary jitterout of an SDH network

SDH tributary jittercharacteristics

The innovation of using pointers totrack the position of the VirtualContainer (VC) within SDH signalshas produced many benefits thatwill minimize the cost andcomplexity of network equipment.However, due to the large inherentphase step associated with apointer movement (eg, 24UI perVC-4 pointer movement),compared to that produced bypulse stuffing techniques used inasynchronous multiplexing, theSDH network has the potential ofcreating large jitter transients inthe demultiplexed tributaryoutputs. Not only are the phasesteps much larger, thecharacteristics of the jitterproduced are completely differentfrom these previously experiencedin the PDH network.

The effect of pointermovements

Experimentation has confirmedthat the jitter created at ademultiplexer output issignificantly greater when the SDHsignal arriving at the PathTerminating Network Element(PTE) contains pointermovements. One naturalphenomenon known as the "87/3"sequence (see Note, Page 14),which occurs in the VC-4 pointerwhen a node within the SDHnetwork loses timingsynchronization, can have theeffect of generating large jittertransients. The test results shownin Table 1 highlight the relativemagnitude of jitter that can resultfrom each effect.

Table 1:

Experimental results highlighting the

relative effect of pointer movements on

the tributary jitter.

Jitter

Network condition measured

(UI p-p)

No pointer movements 0.09

Single pointer movements 0.12

The "87/3" sequence 0.60produced when an nodeis offset by 4.6 ppm

Appendix B

13

Figure B.1: Jitter measurement in a PDH network.

Figure B.2: Input phase and desychronizer response in the presence of a single pointer movement.

xSearch for Positive Peak Search for Negative Peak

100 ms 100 ms

Jitter Threshold

The peak-to-peak jitter during the 200 ms measurement

interval is the difference between the positive peak in

the first 100 ms, and the negative peak during the second

100 ms period. The maximum peak-to-peak jitter during

a gating period is the largest value measured during one

of the 200 ms measurement intervals.

-3-

0-

24-

18-

12-

-

6-

-

-

-

1 2 3 4 5 6 7 8 9 10

Time (seconds)

Phase

(UI)

Desync Input

Phase

Desync Output

Phase Response

14

1.The voltage-controlled oscillator(VCO) used to track the carrier frequency signal being receivedhas a bandwidth of 4 Hz. This willprovide a better reference for themeasurement of long transientsproduced by pointer activity.

2. Separate positive and negativepeak detectors will ensure that allspikes of jitter are capturedirrespective of when they occurwithin the measurement period.

HP 37717A jittermeasurement circuit

The jitter measurement module forthe HP 37717A PDH/SDH BER andjitter test set is the first in a newgeneration of jitter measurementimplementations. To allowaccurate measurement of jittercreated by the SDH network intothe PDH network, the followingtechniques have been employed:

3. The maximum peak-to-peakjitter displayed by the instrumentwill be the difference between thepositive and negative peaks withinthe gating period, ie, the use offixed measurement periods withinthe gating period will no longer beemployed.

By the use of these techniques, theHP 37717A provides a jitter testerthat will give accurate measure ofjitter in a PDH signal, irrespectiveof the network topology that thesignal has passed through.

The "87/3" sequence

When a pointer processing nodewhich is cross connecting VC-4payloads loses lock to the mastertiming source in the network, thefrequency difference between thefree-run reference in the networkelement and the master timingsource will have the effect ofgenerating evenly spaced pointermovements, T seconds apart.However, rather than continuouslyevenly spaced pointer movements,

87 3

T

Pointer

Adjustment

Absent Pointers due to

Section and Line Overhead

some equipment produces a 90 × Tseconds sequence in which apointer movement occurs duringthe first 87 periods but no pointeris produced during the last 3periods, ie, an "87/3" sequence.This effect is caused by thepositioning of the SectionOverhead within an SDH frame.The cross-connection of otherpayloads can also have an effect ofproducing repetitive sequences ofunevenly spaced pointermovements.

Note

15

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