xBridgeEthernet to HDLC Bridge IC

nSYSTech xBridge

Compliant IEEE802.3 PHY I/F with MII/RMII

Compliant IEEE802.3 MAC I/F with RMIIStore & Forward method

HDLC serial WAN I/F

MAC Filtering function

Fluent memory type Interface function

Operating Voltage : 3.3 VOperating Frequency : 50 MHz

Package Type : 100-pin PQFP

MII or RMII Ethernet PHY I/F10Mbps full/half-duplex I/F supports

CRC32 check and generation

Ethernet Back Pressure function

Address Learning (Address Aging)

Address Recognition and ForwardingAddress Locking Function (1/2/3/4 MAC User)

SRAM - minimum 1Mb (64K x 16)

EDO - minimum 8Mb (512K x 16)

SDRAM - minimum 8Mb (512K x 16)

Variable Length Packet Buffer - efficient buffer memory management

Full-duplex serial Tx/Rx

CRC16 check and generation

Osc. or X-tal for Master clockRMII Ethernet MAC I/F

10Mbps full/half-duplex I/FEthernet Back Pressure function

Store & Forward method

SRAM / EDO / SDRAM Buffer selectableTx/Rx Buffer Management

General Description Solution for high performance packet forwarding between LAN and WAN

Bridge

FeaturesOverview

Various Ethernet PHY I/F

MAC Filtering Function

Fluent memory type Interface function

HDLC serial WAN I/F

Operating Frequency : 50MHz

Operating Voltage : 3.3 volts (Core/IO)

Package Type: 100-pin PQFP

Various Ethernet MAC I/F

Various Ethernet MAC I/F

The xBridge is the Cost-effective Ethernet to HDLC Bridge on a single chip.

It performs Ethernet to HDLC bitstream conversion buffer managementand bit rate adaptation with a throughput latency of only one frame.

Together with automatic learning and aging,wire-speed filtering and forwarding.

This chip has various memory controller which can manage SRAM,SDRAM and EDO.

It supports management function with MDIO for user's needs.

The xBridge is suitable for CPE and DSLAM implementations of ADSL,SDSL,VDSL and G.SHDSL.

- 1 -

nSYSTech xBridge

Pin Configuration

Bridge

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

1234567891011121314151617181920

7069686766656463626160595857565554535251

7172737475767778798081828384858687888990919293949596979899100

TP

4T

P3

TP

2T

P1

VS

ST

P0

TM

1V

DD

TM

0D

PLX

_FU

LL/H

ALF

BA

CK

PR

ES

SU

RE

RM

II/M

IILO

OP

BA

CK

1V

SS

LOO

PB

AC

K0

LEA

RN

_EN

VD

DLO

CK

_MA

C_E

NLO

CK

_DIR

LOC

K_M

AC

_SIZ

E1

LOC

K_M

AC

_SIZ

E0

BU

F_R

AT

IO1

BU

F_R

AT

IO0

RA

M_T

YP

E1

RA

M_T

YP

E0

FO

RT

ES

T1

SM

OD

ES

CA

ND

15D

14

TxD

3C

OL

CR

SH

DLC

-CLK

HD

LC-R

XD

HD

LC_T

XD

O�

HD

LC_T

XD

O_O

C�

HD

LC_T

X_L

ED

�H

DLC

_RX

_LE

D�

AO

�V

DD

�A

1�A

2�V

SS

�A

3�A

4�A

5�A

6�V

DD

�A

7�A

8�V

SS

�A

9�A

10(A

P)�

A11

/LC

AS

/LD

OM

�A

12/U

CA

S1/

UD

OM

A13

/WE

/WE

�A

14/O

E/C

AS

A15

/NC

/RA

SO

E/N

C/C

LK

nSYSTechxBridge 1.0

RESETVDDFORTEST0XINXOUTVSSCLK25MRxCLKTxCLKRxDVRxD0VDDRxD1RxD2VSSRxD3TxENTxDoTxD1TxD2

D13D12D11D10VSS

D9D8

VDDD7D6D5D4D3D2

VSSD1D0

VDDCS/NC/CS

WE/RAS/NC

- 2 -

BridgenSYSTech xBridge

Pin Description

VDD(PVDD1Z) Supply voltage for core cells. DC 3.3V

Supply voltage for I/O cells DC 3.3VGround for core cells

Ground for I/O cells

Master Reset50MHz (Clock Input)

25MHz Clock Out

For Test. Tie Low for normal Op.For Test

For TestTie Low for normal Op.Chip Scan Test EnableTie Low for normal Op.Chip Scan ModeTie Low for normal Op.

P 2, 31, 53, 84P 12, 39, 63, 93

P 6, 34, 56, 87

P 15, 42, 66, 96I 1

I 4

I 92, 94

I 3, 75

I 73

I 74

O 5 O 7

O 95, 97, 98, 99, 100

VDD(PVDD2Z)

VSS(PVSS1Z)VSS(PVSS2Z)

*RESETXIN

XOUTCLK25MTM[0:1]

TM[0:4]

FORTEST[0:1]

SCAN

SMODE

HDLC_CLK HDLC CLOCK 5V-Tolerant Input

HDLC RxD 5V-Tolerant InputHDLC TxD for 3.3V I/F

HDLC TxD for open drain I/F

HDLC TX Frame window LED ONHDLC RX Frame window LED ON

I 24I 25

O 26

O 27O 28

O 29

HDLC_RXD

HDLC_TXDOHDLC_TXDO_OC

HDLC_TX_LEDHDLC_RX_LED

RxCLK Receiver clock input from Ethernet PHY. �(MII only)

Transmit clock input from Ethernet PHY. �(MII only)

Receiver data valid input from Ethernet.CRSDV in case of RMII

Receiver data input from Ethernet.Only lower 2 bits (RxD[0:1])are used in case�of RMII

Transmit data output enable signal to�Ethernet.Transmit data output to Ethernet.Only lower 2 bits (TxD[0:1]) are used in case of RMII

Collision input signal from Ethernet PHY. �(MII only)Carrier sense signal from Ethernet PHY.�(MII only)

I 8

I 9

I 10

I 11,13,14,16

O 17

I 22

I 23

O 18,19,20,21

TxCLK

RxDV

RxD[0:3]

TxEN]

TxD[0:3]

COL

CRS

A[0:9] Memory Address[0:9]

SRAM mode : Address10EDO mode : N.C(no connection)SDRAM mode : Address10/SAP

SRAM mode : Address11EDO mode : *LCAS(Column Address �Storbe)SDRAM mode : LDQM(Data I/O Mask)

SRAM mode : Address12EDO mode : *UCAS(Column Address �Storbe)SDRAM mode : UDQM(Data I/O Mask)SRAM mode : Address13EDO mode : *WE(Write Enable) SDRAM mode : *WE(Write Enable)SRAM mode : Address14EDO mode : *OE(Output Enable) SDRAM mode : *CAS(Column Address �Storbe)SRAM mode : Address15EDO mode : N.C(no connection)SDRAM mode : *RAS(Row Address�Storbe)

SRAM mode : *OE(Output Enable)EDO mode : N.C(no connection)SDRAM mode : CLK(SDRAM CLK)SRAM mode : *WE(Write Enable)EDO mode : *RAS(Row Address Storbe)EDO mode : N.C(no connection)

SRAM mode : *CS(Chip Select)SDRAM mode : *CS(Chip Select)EDO mode : N.C(no connection)

Data Input(5V-Tolerant)/Output

O 30,32,33,35,36, � 37,38,40,41,43

O 44

O 45

O 46

O 48

O 49

O 50

O 51

O 52

O 54, 55, 57, 58, � 59, 60, 61, 62, � 64, 65, 67, 68, � 69, 70, 71, 72

O 47

A10(AP)

A11/*LCAS/LDQM

A12/*UCAS1/UDQM

A13/*WE/*WE

A14/*OE/*CAS

A15/NC/*RAS

*OE/NC/CLK

*WE/*RAS/NC

*CS/NC/*CS

D[0:15]

Signal Names Type Pin No. Description

Signal Names Type Pin No. Description

Signal Names Type Pin No. Description

Signal Names Type Pin No. Description

1. Basic signals ( * denotes Low Active Signals) 4. Memory I/F Signals

2. Ethernet I/F Signals

3. HDLC I/F Signals

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Bridge

RAM_TYPE[0:1] I 76,77

I 78,79BUF_RATIO[0:1]

I 80,81LOCK_MAC_SIZE[0:1]

I 82

I 83

I 85

LOCK_DIR

LOCK_MAC_EN

LEARN_EN

MAC Address Filtering Direction0 : HDLC to Ethernet1 : Ethernet to HDLC (used in CPE)

MAC LOCKING Function ENABLE0 : MAC Locking Fn Disable1 : MAC Locking Fn Enable

MAC Address Learning Enable0 : MAC Addr Learning Fn Disable1 : MAC Addr Learning Fn Enable

I 89RMII_MII MII/RMII Selection0 : MII1 : RMII

I 90

I 91

BACKPRESSURE

DPLX_FULL/*HALFFull/Half Duplex0 : Half Duplex1 : Full Duplex

Half Duplex Mode Flow Control. 0 : Back Pressure Disable1 : Back Pressure Enable

I 86,88LOOPBACK[0:1] Loop Back Mode for Test �Tie Low for normal Op.

RAM_TYPE0 pin 76 RAM_TYPE1 pin 77

Buffer Type Selection

WAN/LAN Buffer Size Ratio

MAC Address Locking Size

0 0

0

0

1

1 11

SDRAM

EDOSRAM

NOT AVAILABLE

BUF_RARIO0 pin 78 BUF_RATIO1 pin79

0 0

0

0

1

1 11

1(WAN):9(LAN)

5(WAN):5(LAN)

NOT AVAILABLE

9(WAN):1(LAN)

LOCK_MAC_SIZE0 �pin80

LOCK_MAC_SIZE1 �pin81

0 0

0

0

1

1 11

1 MAC

2 MAC

3 MAC4 MAC

nSYSTech xBridge

Signal Names Type Pin No. Description

5. Configuration Signals

- 4 -

(used in CO)

BridgenSYSTech xBridge

Functional Description1. SYSTEM XBRIDGE is a bridge chip between WAN(HDLC) and LAN(Ethernet). Like LAN to LAN bridge, XBRIDGE do forwarding, filtering, and locking of packets between � WAN and LAN. It's most significant function is packet forwarding.

CLK/RESET/TESTCONTROL

WAN IFHDLCController

FORWARDING ENGINE

LANIFETHERNETController

FILTERINGFUNC

LOCKINGFUNC

BUFFER MANAGER

Internal Control & Data path

External Control & Data path

SDRAM�Controller

EDO DRAM�Controller

SRAM�Controller

BUS�Arbiter

AGING FUNC

RXDIN

LEARN_EN

LOCK_MAC_SIZE[1:0]

LOCK_DIR

RAM_TYPE[1:0]

BUFF_RATIO[1:0]

RESETXIN

XOUTCLK25M

SCAN

SMODE

LOOPBACK[1:0]

FORTEST[1:0]

D[15:0]

Address & Control Signals

LOCK_MAC_EN

HDLC_CLK

TXDOUT

TXDOUT33

TX_LED

RX_LED COL CRS

BACKPRESSURE

RxD[3:0]

TxD[3:0]

RxDV

TxEN

RMII/MII

RxCLK,TxCLK

nSYS Backbone

- 5 -

Bridge

2. Ethernet Controller XBRIDGE has both rolls of MAC and PHY. As a MAC, XBRIDGE could be connected to Ethernet PHY and connected to SWITCHING Controller as a PHY(with RMII). To be connected to these, XBRIDGE support MII(Media Independent Interface) and RMII(Reduced Media Independent Interface). And XBRIDGE support both Full Duplex and Half Duplex in 10Mbps.(DPLX_FULL/*HALF)

2.1 The Role of Ethernet MAC by MII XBRIDGE could support the Ethernet PHY by MII. In this case, CRS(Carrier Sense), COL(Collision) pin should be input from Ethernet PHY.

2.1.1 Transmission When a Frame is prepared, XBRIDGE send it immediately. At that time, first of all XBRIDGE should check the Ethernet line if there is another activity. The signal which indicate this activity is CRS. When this signal is LOW, TxEN and TxD[3:0] is sent to Ethernet PHY synchronizing with TxCLK.

2.1.2 Reception While CRS is asserted XBRIDGE receive the ethernet data. And RxD is SFD(Start Frame Delimitter), XBRIDGE begin to packet the Ethernet nibble Data to store in the external SRAM/EDO/SDRAM with the 16bit data. But when there is a collision that packet is discarded.If buffer is full during receiving operation, XBRIDGE generate the TxEN to keep Ethernet PHY from sending packets. This function is controlled depend on Ethernet Back Pressure pin. To latch the RxD at the stable period, XBRIDGE latch the RxD at the RxCLK rising edge.

2.2 The Role of MAC by RMII RMII is similar to the MII, except: - The data path is two bits wide instead of four. -The Main Clock must be 50MHz instead of 25MHz. - All timing for both transmit and receive is referenced to a single Main Clock(50MHz) instead of TxCLK (2.5MHz) for transmission and RxCLK(2.5MHz) for Reception. -The MII RxDV and CRS inputs are combined into one signal that is outputted on the CRS pin.(Refer to the RMII Spec.) So COL, CRS pins are not used in RMII Mode. - RxD[1:0] = 00 from start of CRS until valid data is ready to be output.

To support 10Mbps Mode, each data Di-Bit must be input on TxD[1:0] and output on RxD[1:0] for ten consecutive main clock.(50MHz) All input and output data is triggered on rising edge of Main Clock.

PRE PRE 1st 2th 3th 4th 5th 6th 7th 8thPRE PRE PRE PRE SFD

TxCLK

TxEN

CRS

TXD[3:0]

400ns

180ns

PRE PRE 1st 2ndPRE PRE PRE PRE SFD

RxCLK

RxV

TXD[3:0]

400ns

(a) Start part

(b) End part

n-4th n-3th n-2th n-1th nth

RxCLK

RxDV

RxD[3:0]

nSYSTech xBridge

Data latch

Figure 1.1 MII Trasmission

Figure 1.2 MII Reception

- 6 -

Bridge

Main Clock

TxEN

TxD[1:0]

20ns

PRE SFD 1st

note1

2.3 The Roll of PHY XBRIDGE could support the Switching Controller RMII. In MII mode, CRS and COL signals aren't generated from XBRIDGE. ��2.4 Pin configuration 2.4.1 MII Mode (RMII/*MII : GND) � Ethernet PHY Interface

COL (Input) COL (Output)

CRS (Output)

TxCLK (Output)

TxEN (Input)

TxD[3:0] (Input)

RxCLK (Output)

RxDV (Output)

RxD[3:0] (Output)

25MHz CLK(Input)

CRS (Input)

TxCLK (Input)

TxEN (Output)

TxD[3:0] (Output)

RxCLK (Input)

RxDV (Input)

RxD[3:0] (Input)

CLK25M(Output)

2.4.2 RMII Mode (RMII/*MII = VDD)� Ethernet PHY Interface

nSYSTech xBridge

XBRIDGE Chip Ethernet PHY Chip

XBRIDGE Chip

XIN (Input)

TxEN (Output)

TxD[1:0] (Output)

RxDV (Input)

RxD[1:0] (Input)

Ethernet PHY Chip

50MHz CLK (Input)

TxEN (Input)

TxD[1:0] (Input)

CRS_DV (Output)

RxD[1:0] (Output)

note1:Each Di-Bit is present on RxD[1:0] for 10 consecutive Main Clock.

Figure 1.3 RMII Transmission

- 7 -

Bridge

Ethernet Switch Interface

3.CRC(Cyclk Redundancy Check) & Generation XBRIDGE has the CRC function which reduce the traffic on SDSL line. When packet is transffered from ethernet PHY, this module checks the 32 CRC-check. If the packet's CRC is not correct, XBRIDGE discard it so it's not transffered. Of cource, When XBRIDGE sends the packets to ethernet PHY, generates the CRC 32. CRC-32 : X + X + X + X + X + X + X + X + X + X + X + X + X + 1

4. HDLC Controller XBRIDGE has an interface to HDLC. XBRIDGE's main function is forwarding Ethernet Packet from local Lan to WAN and vice versa. A Packet from Ethernet saved in XBRIDGE's buffer memory. After completion of receiving Ethernet packet from Ethernet, HDLC Controller read the packet stored in buffer memory and forward it to WAN via HDLC interface signaling. And, a packet from WAN which are saved in the other addressed XBRIDGE's buffer memory,forwarded to Ethernet via. Ethernet RMII/*MII Interface signaling.

4.1 HDLC Frame Receiver A received packet consists of an opening flag, data bytes, and 16-bit CRC, and a closing flag. Serial data from the HDLC_RXD packed in byte data and stored to XBRIDGE's external buffer memory. The order of bytes received in a data packet starts with bit 1 in the first data byte.

4.1.1 Operation The receive cycle starts with the detection of data after the opening flag in the packet. After a flag is detected, he HDLC checks the data bit stream for minimum(less then 62 bytes including CRC-16) and maximum(more hen 1534 bytes including CRC-16) packet length, zero deletion, abort characters, and idle characters. During normal reception of packet, the HDLC Controller request a write permission to XBRIDGE's BUFFER MANAGER. After all data bytes are received and closing flag was detected, HDLC Controller update WAN to LAN semaphore status. CRC16 2 byte in received packet will be removed by HDLC Controller. The minimum memory write access rate via BUFFER MANAGER is normally equal to four bytes reception rate.Afterwards, the HDLC enters an internal not busy state, and de -assert memory write request to BUFFER MANAGER.

4.1.2 Clocking The HDLC Controller Receiver get data from HDLC_RXD in negative edge of HDLC_CLK.. So it must have a guaranteed timing margin in setup and hold for HDLC_CLK's negative edge.

nSYSTech xBridge

latched_RXD

HDLC_RXDIN

HCLK

> 100 ns

0 1 1 1 1 1 1 0 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8

0 1 1 1 1 1 1 0 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8

flag

HDLC_CLKHDLC_CLK

4.1.3 Flag Detection The HDLC supports the following received flag (01111110) sequense : - Multiple flags between packets (...0111111001111110....) - A flag shared as the closing and opening flag between two packets (...Data CRC 01111110 Data...) - A shared zero between flags (...011111101111110..) All incoming flags are ignored and discarded by the HDLC. The first bit received which is not part of the flag character signifies the start of the packet. If a flag is received during a packet, it indicates the end of the packet. The CRC is checked (the last two bytes of the packet), and a decision is generated to forward or not.

XBRIDGE Chip

XIN (Input)

RxDV (Input)

RxD[1:0] (Input)

TxEN (Output)

TxD[1:0] (Output)

Ethernet Switch Chip

50MHz CLK (Input)

TxEN (Output)

TxD[1:0] (Output)

CRS_RxDV (Input)

RxD[1:0] (Input)

- 8 -

32 26 23 16 12 11 10 8 7 5 4 2

Bridge

4.1.4 Zero DeletionEach bit received between the opening and closing flag is checked for zero bit insertion. A zero that follows five contiguous ones is discarded from the incoming bit stream. HDLC is defined this feature to avoid the occurence of flag in user data field.

4.1.5 Packet LengthThe received (and transmitted) packet is monitored for length pre-determined by XBRIDGE chip itself. The minimum packet data size must be longer than 62 bytes (including 2 bytes of CRC-16) and the maximum packet data size must be shorter than 1534 bytes (including 2 bytes of CRC-16).When the incoming packet exceeds the maximum length or are shorter than the minimum length, the HDLC Controller discard the packet by flushing the memory buffer region, and waits for the next packet to be received.

4.1.6 Cyclic Redundancy Check (CRC)The frame check sequence (FCS) consists of 16 bits immediately preceding the closing flag. The 16-bit FSC detects data errors through the use of a cyclic redundancy check (CRC) code. The CRC is generated from the incoming data and compared against the received CRC (remainder), carried in the FCS field of the packet. If the comparison does not match because of a bit error or burst error, the HDLC discard the packet by flushing the memory buffer regions, and waits for the next packet to be received.The CRC check polynomials are as follows :

CRC-16 :

nSYSTech xBridge

X +X + X + 1

X +X +X +1

16 12 5

16 12 5

HDLC_TXDOUT33

HDLC_TXDOUT

HCLK

> 100 ns

0 1 1 1 1 1 1 0 bit0 bit2 bit3 bit4 bit5 bit6 bit7 bit8bit1

0 1 1 1 1 1 1 0 bit0 bit2 bit3 bit4 bit5 bit6 bit7 bit8bit1

HDLC_CLK

_OC

HDLC_CLK

HDLC_TXD

HDLC_TXD_OC

4.2.3 Flag GenerationThe HDLC Controller Transmitter generates either a single (01111110) or multiple flags (0111111001111110...), depending on the packet data �present in the external memory buffer stored by LAN interface.

4.2.4 Zero InsertionThe data in the packet read from the external buffer memory is checked for the number of contiguous ones prior to trasmission. A zero is insertedinto the transmitted bit stream after five contiguous ones are detected, excluding flags or abort characters. By this, HDLC can avoid the confusion between flag and data which has the same value with flag.

4.2.5 Cyclic Redundancy Check (CRC) GenerationThe frame check sequence (FCS) consists of 16-bits immediately preceding the closing flag. the 16-bit FCS detects data errors through the use of�a cyclic redundancy check (CRC) code. When all user data transmitted, the calculated value is transmitted after the last data byte, and enclose the �frame with a closing flag. The CRC generation polynomials are as follows :CRC-16 :

4.2.1 OperationThe transmitter timing is asynchronous in relationship with the receive timing. Internal HDLC timing, the read buffer memory control, FORWARD-ING ENGINE semaphore interface timing, are derived from the external HDLC_CLK clock. HDLC Controller's Transmitter waits semaphore pending in FORWARDING ENGINE. If there are pending semaphore value, HDLC Controller Transmitter check the semaphore status and learn the buffered packet information. After that sequence, Transmitter start open flag to the HDLC_TXDOUT/HDLC_TXDOUT33, read data from memory buffer, tran-sfer the data to the line with synchronizing HDLC_CLK. Like the receiver, transmitting frame must have features for zero insertion, CRC generation, and flags for start and complete and idle states.

4.2.2 ClockingThe HDLC Controller Transmitter send data to HDLC_RXD at positive edge of external HDLC_CLK..

4.2 HDLC Frame Transmitter A transmitted packet consists of an opening flag, data bytes, and 16-bit CRC, and a closing flag. Serial data sent via HDLC_TXDOUT (for external 5v pull-up) and HDLC_TXDOUT33 (for 3.3v). Before sent via HDLC_TXDOUT, HDLC Controller read data from BUFFER MANAGER and serialize it. The order of bytes transmitting in a data packet starts with bit 1 in the first data byte.

- 9 -

Bridge

5. BUFFER MANAGERBUFFER MANAGER has an packet data interface between HDLC and Ethernet Controller and external Memory. BUFFER MANAGER has a role of controlling external memory buffer and servicing the data transfer requests from HDLC and Ethernet. Whichever Memory, you want to use in your applications, you can just connect the memory (SDRAM, DRAM, SRAM) to XBRIDGE directly without any GLUEs.

5.1 SDRAM Control XBRIDGE's BUFFER MANAGER includes SDRAM Controller. Supporting minimum SDRAM size is 8Mb(512Kx16). The Column Address are fixed in 8bit. XBRIDGE's �BUFFER MANAGER supports only 16-bit Memory DATA BUS. So there are 2 CAS signals. SDRAM operating clock is driven by XBRIDGE's SCLK. It's clock speedis same as XIN. It means the operating clock for XBRIDGE will be used the access clock for SDRAM. It generates Auto Refresh by SDRAM Controller's internal Refresh Control Logic.

5.2 EDO DRAM ControlXBRIDGE'x BUFFER MANAGER includes EDO/FPM DRAM Controller. Supporting minimum EDO/FPM DRAM size is 8Mb(512Kx16). The Column Address are fixed in 8bit (which are 256 \column). There are 2 CAS signals for 16 bit DATA bus interface. XBRIDGE supports maximum 60ns tCAC(Access Time from CAS signal), so any kind of EDO/FPMaccess time could be satisfied by XBRIDGE's DRAM Controller. Controller generates CBR by DRAM Controller's internal Refresh Control Logic.

5.3 SRAM ControlXBRIDGE'x BUFFER MANAGER also includes SRAM Controller. Supporting minimum SRAM size is 1Mb(64Kx16). The access times(tRC:Read Cycle Time, tWC:Write Cycle Time) of SRAM are maximum 40ns.

5.4 Memory Signals Mux-tablePSC withZero

Insertion

nSYSTech xBridge

SDRAM

EDO/FPM

SRAM

D[15:0]

D[15:0]

D[15:0]

A[0:10],A[10] for SAP

A[0:9]

A[0:15]

DQM0 DQM1 nWE nCAS nRAS nCS

nCAS0 nCAS1 nWE nOE nRAS

nOE nWE nCS

SCLK 2'b00

2'b01

2'b10

ADDRESS bus CONTROL signals CLOCKDATA busMemory typeRAM_TYPE[1:0] MCNTR[0:9],

- 10 -

6. FORWARDING ENGINE�

FORWARDING ENGINE has a function to interface a packet descriptors between HDLC Controller and Ethernet Controller. And it works as a core part in forwarding packets. All packets received any side of port, must be stored to external buffer memory. After receiving completed, the receiver (HDLC Receiver or Ethernet Receiver) report to the FOR-WARDING ENGINE to set a flag which has a meaning that a valid packet is received correctly, and the other side interface transmitter (Ethernet Transmitter or HDLC Transmitter) gets the flag and packet descriptor to transfer its interface line.Transmitter start data transfer with the packet descriptor in FORWARDING ENGINE. In completion for the requested packet descriptor, transmitter report to the FORWARDING ENGINE to clear flag to notify that packet forwarding is done correctly.

Another important function of FORWARDING ENGINE is flow control. If Reciever's data reception rate is faster than Transmitter's data transfer success rate, then our external buffer memory may be overflow in near future. For this case of buffer overrun, FORWARDING ENGINE control the receiver to stop receiving or generate not-acknowledge inform-ation to it's counter-part transmitter, until the buffer memory overrun solved.

XBRIDGE's FORWARDING ENGINE manages buffers by units not by packets. A packet received is divided in 128-byte unit, and stored in external memory in these unit based blocks. A packet less than 128 bytes could be assigned in a single 128-byte unit, and the other packet more than 128 bytes must be assigned in some multiple 128-byte units. In this 128-byte unit usage architecture, XBRIDGE perform best buffer managing scheme than other similar ICs.

FORWARDING ENGINE also controls the three internal Packet managing FUNCTION. The first is ADDRESS LOCKING FUNCTION, the second is ADDRESS FILTERING FUNC-TION and the last is AGING FUNCTION. ADDRESS LOCKING FUNCTION restricts the number of users to access ISP access points. If ADDRESS LOCKING FUNCTION is enabled with 2 MAC address lock, then only two user's MAC packet should be forwarded to the other side network. The maximum MAC address lock is 4. ADDRESS FILTERING FUNCTION restricts the dummy traffic flooding to the other side network. For example, when a user resided in network A, wants to talk to the other one who also resided in network A, XBRIDGE restricts these talking packets to the other network, B, or C, .. etc.. This feature performed by learning who is here network A, and to whom current packet headed. So, the packet is heading to the same network, XBRIDGE's FORWARDING ENGINE do not forward the other side network, because he knows the packet's destination is resided in the same network. By ADDRESS FILTERING FUNCTION, dummy traffic should be reduced significantly. FILTERING ADDRESS table size could be 512 MAC table or 2048 MAC table or 4096 MAC table. ADDRESS AGING FUNCTION makes sure that the user is alive in the network. If there is no activities from the user, ADDRESS AGING FUNCTION removes the user's ADDRESS from FILTERING ADDRESS table. The aging timer interval is fixed in 300sec.

Bridge

7. Mode Selection GuideXBRIDGE chip has several kind of configuration selection pins. There are some mode pins for Ethernet Interface, HDLC interface, Memory Interface, and Buffer usage.

7.1 Ethernet Interface mode selection Before interfacing to Ethernet, XBRIDGE must be configured for Ethernet interface below PINs properly. XBRIDGE supports RMII(reduced Media Independent I nterface) and MII(Media Independent Interface). And XBRIDGE supports Ethernet for Full duplex and half duplex mode. And if it is chosen half duplex mode, the back pressure mode for flow control could be also selectable.

7.2 Memory and Buffer usage mode selectionXBRIDGE has so many configuration selection mode for Memory Buffer usage. These various configuration selection PINs must be set for the application properly.

RMII/*MII

BACKPRESSURE

DPLX_FULL/*HALF

RMII or MII selection PIN. 1 : RMII0 : MII

BACKPRESSURE mode enable PIN for Half duplex mode flow control1 : BACKPRESSURE Enabled (with DPLX_FULL/*HALF = 0)0 : BACKPRESSURE Disabled

Full duplex Ethernet interface mode enable PIN1 : Ethernet Full duplex mode0 : Ethernet Half duplex mode

RAM_TYPE[0:1]

BUF_RATIO[0:1]

External Memory Selection PIN

External Memory Buffer Ratio selection PIN

RAM_TYPE0

BUF_RATIO0

0 0

0

0

1

1

11

RAM_TYPE1

BUF_RATIO1

SDRAM

EDO/FPM DRAM

SRAM

NOT AVAILABLE

0 0

0

0

1

1

11

WAN to LAN 1 : 9

WAN to LAN 5 : 5

WAN to LAN 5 : 5

WAN to LAN 9 : 1

nSYSTech xBridge

Mode PIN name Descriptions

Mode PIN name Descriptions

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Bridge

7.4 Extra Function mode selection XBRIDGE supports Address locking function for ISP's special application usage. By this function, ISP can restrict the number of users to the service point. The Locking function can be executed in any direction(HDLC or Ethernet).

RAM_TYPE[0:1]

LOCK_DIR

LOCK_MAC_EN

LEARN_EN

External Memory Selection PIN

MAC Address Lock function Interface Selection1 : Ethernet Interface Locking (used in CPE)0 : HDLC Interface Locking (used in CO)

MAC Address Locking function Enable1 : Locking Enable0 : Locking Disable

Ethernet side Address Learning Enable to avoid Dummy Traffic 1 : LEARNING/AGING/FILTERING Enable0 : LEARNING/AGING/FILTERING Disable

LOCK_MAC_SIZE0 LOCK_MAC_SIZE1

0 0

0

1

1

1

0

1

1 MAC address usable

2 MAC address usable

3 MAC address usable

4 MAC address usable

nSYSTech xBridge

Mode PIN name Descriptions

AC and DC Information 1. DC Characteristics

Recommended operating conditions and electrical characteristics are summarized in the following table.

Parameter Condition Min. Typ. Max.

VDD Supply Voltage 3.0V 3.3V 3.6V VIL Input Low TTL Compatible 0.8V Voltage CMOS Compatible 0.3VDD

VIH Input High TTL Compatible 2.0V Voltage CMOS Compatible 0.7VDD

VOH Output High Voltage 2.4V VDD

VOL Output Low Voltage 0.2V 0.4V

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BridgenSYSTech xBridge

nSYST

echxB

ridge 1.0

100

71

7051

50

21

20 1

HD

HEE

D

Pin Detail

c

LA1AA2

L1seePin Detail

y

be

Symbol

A 0.134(MAX)

0.010(MIN)

0.112 0.005

0.551 0.004 14.000 0.102

20.000 0.102

0.677 0.008 17.200 0.200

23.200 0.200

0.810 0.152

1.600 0.152

0.913 0.008

0.032 0.006

0.063 0.006

0.003(MAX) 0.076(MAX)

0 ~ 7

0.787 0.004

0.026(BSC)

0.012(TYP)

0.006(TYP)

D

E

L

y

A1

A2

HD

HE

L1

b

c

INCH MM

e

0 ~ 7

3.404(MAX)

0.254(MAX)

0.300(TYP)

0.150(TYP)

0.650(BSC)

2.845 0.127

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