Enabling 100GbE Using 4 x 25 Gb/s

Retimed Interfaces

Ed Frlan

Principal Product Definition Specialist

Gennum Corporation

Edward.Frlan@gennum.com

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Agenda

� 100 GbE Optical Module Trends

� Key Terms for 100 GbE

� System Architectures

� Benefits of a Retiming Architecture

� 25G CAUI-4 Challenges

� CFP2 Design Example

� Summary

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100 GbE Optical Module Trends

� Standard CFP module will transition to CFP2

• 3.2” x 5.7” form factor →→→→ 1.6” x 5.2”

• 10x 10.3G elec I/F →→→→ 4x 25G elec I/F

• 100GBASE-LR4 CFP power of 20W/24W typ/max

→→→→ CFP2 of 10W/12W typ/max

� 10:4 PMA gearbox function moves out of

module and onto line card

� CFP2 module requires both Tx and Rx

retiming blocks for LR4/ER4 applications as

well as some equalization capability

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Key Terms for 100 GbE

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� CAUI (100Gb Attachment Unit Interface)• CAUI interface for 100Gb/s, organized into 10 lanes

• Each lane runs at 10.3125Gb/s

• Intended for chip-to-chip or host-to-module interface

� CAUI-4 (100Gb 4x25G Attachment Unit Interface)• CAUI-4 interface for 100Gb/s, organized into 4 lanes

• Each lane runs at 25.78125Gb/s

• CAUI-4 is a fully retimed interface

� CPPI (100Gb Parallel Physical Interface)• Organized into 10 lanes, each lane running at 10.3125Gb/s

• Used for SR links not requiring a retimed interface

� CPPI-4 (100Gb 4x25G Parallel Physical Interface)• Organized into 4 lanes, each lane running at 25.78125Gb/s

• May be used in future 100GBASE-CR4/SR4 links

• CPPI-4 interface is not yet defined

Key Terms for 100 GbE

� CEI-28G-SR (28Gb/s Short Reach)• Intended for CAUI-4 chip-to-chip interface

• Allows for up to 15 dB loss between 10:4 gearbox and ASIC– Implies 6” - 12” reach based upon PCB material

• Equalization based upon combination of transmit FIR de-emphasis and receive equalization

� CEI-28G-VSR (28Gb/s Very Short Reach)• Intended for CAUI-4 chip-to-module interface

• Likely to allow for up to 8dB loss between module and PHY– Implies 4” – 8” reach depending upon PCB material

• Equalization likely to be based upon combination of transmit FIR de-emphasis and receive CTLE analog equalization

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Line Card

Present CFP System Architecture

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100 GbE CFP Module

QuadLaserDriver

Laser(x4)

QuadTIA

PhotoDiode(x4)

10:4 PMA SER / DES(Gear-box)

ASIC

MUX

DMUX

CFP

100GBASE-LR4

100GBASE-ER4

CAUI

� 10:4 PMA and PMD sublayers in module

CFP2 System Architecture

� PMA 4:4 and PMD sublayers in module, 10:4 PMA sublayer now on line card

� 25G CAUI-25G interface to leverage OIF CEI-28G-VSR recommendation

Line Card 100 GbE Module

QuadLaserDriver

Laser(x4)

QuadTIA

PhotoDiode(x4)

ASIC

10:4 PMASER/DES(Gearbox)

MUX

DMUX

CAUICAUI-4

(28G-VSR)

QuadTx CDR

QuadRx CDR

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Future CFP2 System Architecture

� Entire sytem is 25G based up to ASIC

� Separate 4x25G retimer block (PMA 4:4 sublayer) will be required for longer links with more loss

Line Card 100 GbE Module

QuadLaserDriver

Laser(x4)

QuadTIA

PhotoDiode(x4)

FutureASIC

4x25GRetimerBlock

MUX

DMUX

CAUI-4

(28G-

SR/VSR)

CAUI-4

(28G-VSR)

QuadTx CDR

QuadRx CDR

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Key Definition - Retiming

� Serial Data Input• High amounts of noise/jitter

(timing uncertainty)

• Difficult for receiver to distinguish between 0 and 1

� Retimed Output• Uses recovered clock to retime

the serial data stream

• Removes high frequency noise

• Results in low output jitter

• Easier for receiver to distinguish between 0 and 1

Phase

Detector

Charge Pump/

Loop FilterVCO

PLL (Phase-Locked Loop)

clk

D

Q

Serial

Data Input

Retimed

Output

Recovered

Clock

CDR (Clock and Data Recovery) Block

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Benefits of a Retiming Architecture

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� Retiming architecture enables longer link lengths and longer trace lengths

• Retimer resets the jitter budget, so jitter budget can be distributed amongst fewer components

• Enables copper cable assemblies >10m vs. 7m goal

• Enables MMF links of 300m vs. 100m goal

• Enables XL/CAUI channel with loss up to 10.5dB, vs max loss of XL/CPPI of 5.2dB (at 5.15GHz)

Copper >10m

MMF > 100m

Module

CDR

ASICXLAUI/

CAUI

Reset jitter budget

Module

CDR

ASICXLAUI/

CAUI

Reset jitter budget

Benefits of a Retiming Architecture

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� Retiming architecture reduces crosstalk

• XLAUI and CAUI will result in many 10Gb/s lanes routing over long traces and through connectors

• Retimer reduces jitter due to crosstalk

Crosstalk

through package

pins/bondwiresCrosstalk

between traces

Crosstalk through

the module

connector

Crosstalk through

the backplane

connector

ModuleASICbackplane

connector

frequency

crosstalk

25G CAUI-4 Increased Interface

Challenges Compared to 10G CAUI

� Trace losses are significantly larger

• eg. Megtron-6 trace loss more than doubles from

0.5dB/in for 10.3Gb/s NRZ signal to 1.1dB/in for a

25.8Gb/s signal

� High-speed module connector must exhibit

excellent return loss performance in order to

minimize chip equalization requirements

� There is a tradeoff between power and reach

which needs to be managed

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Typical 25G Channel Insertion Loss

� For example, chosen equalization scheme must manage 12 dB of loss at Nyquist rate for channel including 8” of stripline serdes-to-module trace in a Nelco 4000-13SI based PCB system

8” chip-to-module

channel insertion loss

Approx. 12dB insertion

loss at Nyquist rate

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CFP2 Design Example

Transmit Equalization Requirements

� Equalization of 12dB insertion loss at Nyquist

could be implemented by a combination of

serdes Tx FFE and module CDR analog

CTLE

• 7 dB from Tx FFE (one pre- and one post-cursor)

• 5 dB from Rx CTLE

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CFP2 Design Example

Transmit waveforms

De-emphasized

Tx Eye

Equalizer

Input Eye

Equalizer

Output Eye

CDR Output

Eye

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Summary

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� A retimed interface enables 100GbE designs• Resets the jitter budget along the channel• Increases the link length• Reduces the requirements of the ASIC• Provides design flexibility• Increases the robustness of the design• Retimed interface will enable next generation 100GbE CFP2

module

Biography

� Ed Frlan is a Principal Product Definition Specialist within the

AMS division of GennumCorp. Prior to Gennum Ed was a

Senior Hardware Architect within the Metro Ethernet Networks

division of Ciena where he was responsible for the system

architecture and synchronization aspects of various line cards

for several applications including Carrier Ethernet, SONET, OTN

and Broadcast Video. Ed holds a Ph.D. degree in Electrical

Engineering from Carleton University.

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Company Overview

� Gennum Corporation (TSX: GND) designs innovative

semiconductor solutions and intellectual property (IP) cores for

the world's most advanced consumer connectivity, enterprise,

video broadcast and data communications products. Leveraging

the company's proven optical, analog and mixed-signal products

and IP, Gennum enables multimedia and data communications

products to send and receive information without compromising

the signal integrity. A recognized award-winner for advances in

high definition (HD) broadcasting, Gennum is headquartered in

Burlington, Canada, and has global design, research and

development and sales offices in Canada, Germany, India,

Japan, Korea, Mexico, Taiwan, the United States and the United

Kingdom.

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