Lam Research Corp. | SEMICON China 2016 1

Etch Challenges and Solutions for 3D NAND

Vahid Vahedi

SEMICON China, ShanghaiMarch 15, 2016

Lam Research Corp. | SEMICON China 2016 2

► Industry technology roadmap: 3D NAND

► 2D (planar) NAND → 3D NAND

► Etch strategies to meet 3D NAND challenges

► Key etch processes in 3D NAND High aspect ratio etch

Hardmask etch

Stair etch

► Summary

Etch Challenges and Solutions for 3D NAND

Lam Research Corp. | SEMICON China 2016 3

3D NANDHigher bit density

Lower cost per GB

MultiplePatterning

Higher density

Feature shrink

FinFETHigher speed

Lower power

Advanced Packaging

Higher functionality

Smaller form factor

Planar Gate FinFET

Planar NAND 3D NAND

Litho-Only Quadruple PatterningDouble Patterning

Wire-Bond Stacked Chip

Industry Technology Roadmap: 3D NAND

WLP TSV

2013 2014 2015 2016 2017 2018 2019 2020 2021VolumeProduction

3D NAND

Planar NAND with Multiple Patterning

Multiple Patterning

20 nm 16 nm

32L 48L 96+L64L

18 nmMemory

(3D NAND)

Source: Lam Research

Lam Research Corp. | SEMICON China 2016 4

2D (planar) NAND → 3D NAND

ControlGate

Floating Gate

electron (representation)

S D

p-Si

Floating gate>1970

ControlGateCharge

Trap

S D

p-Si

Charge trap>2005

3D vertical NAND>2013

1

2

48n

Horizontal string of NAND gates

Lam Research Corp. | SEMICON China 2016 5

Key Etch Processes Defining 3D NAND Memory Array

Memory hole:High aspect ratio Hardmask etch Memory layers etch

Stair:Stair etch

Slit:High aspect ratio Hardmask etch Memory layers etch

Contact:Multi-level contact

Single Memory Cell

Lam Research Corp. | SEMICON China 2016 6

► Etch design principles for critical etch performance Within-die performance — wide operating window and advanced pulsing capability

Uniform results across the wafer — symmetric chambers and independent tuning knobs

Repeatable performance for every wafer and every chamber at low cost– Repeatable subsystems with advanced calibration capability

Enable lowest overall cost of ownership for the scaling to continue

Lam Etch Strategy to Meet 3D NAND Scaling Challenges

Within Die Across the Wafer Wafer-to-Wafer Chamber-to-ChamberBillions of cells per die

Hundreds of dies per wafer

Thousands of wafers per day

Multiple chambers per fab

Enabling High Aspect Ratio Etch

Uniformity Tunability

Repeatable Performance

Lam Research Corp. | SEMICON China 2016 7

3D NAND High Aspect Ratio Etch for Memory Hole

High Aspect Ratio Etch for Memory Hole Defines the channel for the memory cell

Hole etch is the most critical and challenging step in manufacturing of a 3D NAND device

The hole is etched through all the depositedlayers to the bottom stop layer or substrate

A vertical hole etch profile is required to achieve higher yields, device and cost performance

Key Challenges

Profile control: bow-free, straight profile, minimal twisting, ARDE

Selectivity to hardmask

Incomplete etch (underetch)

Uniform across the wafer

More layers → higher aspect ratio → more challenging etch

Single Memory Cell

Cell area = # of pairs x 4*(Feff)2

Feff = Effective area feature size

Twisting

Bowing

CD variationat top vs.bottom

Incompleteetch

Selectivity to hardmask

Lam Research Corp. | SEMICON China 2016 8

3D NAND High Aspect Ratio Etch

Transport limitation: Ion/neutral flux ratio changes with etch depth

Mask consumed by ions at constant rate

Neutrals shadowed and stick, can fail to reach bottom > 40:1

Ions weaken from induced voltages, 50% of ions may not reach bottom >50:1

+

+

+

Engineering difficulty increasing for high aspect ratio etches

10

20

30

40

50

60

2015 2016 2017 2018M

emor

y Ho

le A

spec

t Rat

io

Year in Production

1 pass

1 or 2 pass

Lam estimates

Lam Research Corp. | SEMICON China 2016 9

++

+

+

primary facet

secondaryfacetneck

bow

ion

θ

Breaking Fundamental Trade-offs Is Key High Aspect Ratio Etch

Aspect Ratio

Trade-offProfile control Mask selectivity

Trade-off: Polymer clogging (capping)

Trade-off: Mask faceting bow CD

Trade-off: ARDE limited by ion directionality and transport

Flex™ Series offers differentiated solutions to break process trade-offs

Lam Research Corp. | SEMICON China 2016 10

3D NAND Hardmask Etch for Memory Hole

Hardmask Etch for Memory Hole

Opens the hardmask before the memory hole etch

Defines the initial size and shape/circularityof the memory channel

Sidewall profile (bow, taper, etc) is tuned to enable widest operating window of subsequent memory hole etch

Key Challenges

Uniform profile and CD even due to multiple sources of variability

Straight profile with minimal distortion or twisting

Repeatable performance

Memorylayers

Hardmask

1. Litho 2. Mask thickness

3. Mask open 4. Hole formation

Challenge: Multiple contributions to CD non-uniformity

Lam Research Corp. | SEMICON China 2016 11

3D NAND Stair Etch — Creating Contact Pads Without Litho

Channelhole

Contacts

Padsfor contacts

3D NAND Stair Etch

One contact pad for connection to each memory cell

Defines the size of each pad with controlled etches instead of numerous litho steps

Key Challenges

Stair CD uniformity and repeatability

Photoresist lateral/vertical (L/V) selectivity

Minimize cost of ownership

Etch

Trim

Etch

Trim

3

1

2

4

Lam Research Corp. | SEMICON China 2016 12

3D NAND Stair Etch — Uniformity and Repeatability

Challenges

Extreme precision requiredto maintain stair CDs

Required Solutions

Uniform stair CD at high throughput

Repeatable performance stair-to-stair, wafer-to-wafer

Misaligned contacts from out-of-spec stair CDs

Systematic errors scale with # of trims

100%

150%

200%

0 7 14# of trims

Stair CD CD=CD0 (1+ε)n

ε=5%

ε=2%

ε=1%

Enabling technologies

Symmetric design Orthogonal uniformity

tuning knobs

Enabling technologies

Fast dynamic subsystems Precision software timing

and endpoint

1% 3σ after 7 trims

-8%

-4%

0%

4%

8%Stair CD Variaion

1 2 3 4 5 6 7

W2W w/in ± 1%

Lam Research Corp. | SEMICON China 2016 13

Challenges

Minimizing CoO for the stair module

# of stairs per litho pass limited by resist thickness & L/V etch selectivity

Required Solutions

High lateral/vertical (L/V) selectivity

3D NAND Stair Etch — L/V Resist Selectivity

L

V

Resist

36L 48L 72L 96L

Stair Litho CoO

36L 48L 72L 96L

Stair litho CoO

8 stairs per litho pass

16 stairs per litho pass

litho1

litho2litho3

litho4litho5

litho6litho7

litho8

Higher L/V trim rate reduces # of lithopasses required

litho1

litho2

litho3

litho4

2x selectivity

trim

Lam Research Corp. | SEMICON China 2016 14

Etch Challenges Lam Solutions

High AspectRatio Etch

Profile control (bow-free, ARDE)

Striations/Bending-free profile

CD uniformity

Mask selectivity

Stop layer selectivity

Flex™ family

HardmaskEtch Uniform profile and CD

Minimal distortion Tunable profile Repeatable performance

Kiyo® family

Stair Etch

Stair CD repeatability

High L/V PR trim selectivity

CD uniform across wafer

Kiyo family

3D NAND Etch Challenges and Lam Etch Solutions

Reduce litho passes required

Best-in-class uniformity

and tunability

non-radial CDU

2x Selectivity

Trim

Conventional Trim

High aspect ratio etch with profile, uniformity and selectivity control