ESL Power Estimation: A Design Case Study forEarly Design Phases

Bo Wang1, Yang Xu1, Rafael Rosales2, Ralph Hasholzner1, and Jurgen Teich2

1 Intel Mobile Communications GmbH, Neubiberg, Germany{bo1.wang,yang.a.xu,ralph.hasholzner}@intel.com

2 Hardware/Software Co-Design, Department of Computer Science,Friedrich-Alexander Universitat Erlangen-Nurnberg

{rafael.rosales,juergen.teich}@informatik.uni-erlangen.de

Abstract. Electronic System Level (ESL) power estimation is executedin early design phases to avoid expensive redesigns. In this paper we con-centrate on the evaluation of an existing ESL power estimation method-ology for the modeling of future platforms, with respect to applicability,flexibility and reusability. Two industrial design cases are investigated.In the first one, an existing mobile communication platform supportingGSM paging burst is discussed to elaborate the modeling approach indetail. Based on this, a novel platform for paging burst is modeled andanalyzed. The highly flexible and reusable modeling capabilities are val-idated. This shows that the methodology is applicable to the what-ifanalysis of HW/SW architecture in early design phases.

Keywords: Power Estimation, Electronic System Level, Early DesignPhases, Design Case Studies

1 Introduction

The development of modern portable embedded systems requires not only highlysophisticated functionalities, but also a long battery life. To achieve a low pow-er design, various Dynamic Power Management (DPM) technologies have beenproposed [1] [2], e.g. clocking gating, power gating, dynamic voltage frequencyscaling (DVFS), dynamic body biasing. However, evaluation and selection ofa Dynamic Power Management Policies (DPMP) have been a challenging taskfor system architects to optimally utilize various DPM technologies, especial-ly considering other design constraints, e.g. performance. Firstly, the accurateanalysis of power and DPMP must start in early design phases together withperformance evaluation, even in specification phase without Software (SW) orHardware (HW) implementation details available, to avoid any unacceptableredesign in later design cycles. For instance, DVFS saves power at the cost ofextended execution time which might violate real-time constraints. Improperpower gating causes higher power consumption conversely due to too frequen-t context switching. Secondly, an Electronic System Level (ESL) approach isrequired to achieve globally optimal design decisions for a heterogeneous plat-form under design, typically consisting of multiple digital, analog blocks and

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RF transceivers. Thirdly, the modeling of application use cases is demanded foraccurate power estimation since applications have a vital effect on power con-sumption. For example, it is shown in [3] that a smartphone may consume upto 2-order variable power in different scenarios.

A large number of prominent research has been accomplished and fulfillsthese requirements partially. In [4] [5] [6], cycle-accurate power estimation toolsare presented at instruction level to profile power consumption of SW accurately.But they need rely on C-level source codes which might be unavailable in earlydesign phases. Spreadsheet based approaches [7] are commonly applied in earlydesign phases to calculate the average power based on either measured valuesor estimations. However, dynamic power behaviors, e.g. DPM, are difficult tobe captured adequately. To overcome this, Power State Machines (PSM) arepresented in [8] [9]. The stimuli from a use case modeling drives the transitionof all PSMs of the platform to obtain dynamic power consumption. But theyfail to co-simulate the performance and power due to the weak capability ofmodeling application functionalities. Transaction level simulation methods areproposed to model application functionalities and timing information efficiently.They are able to evaluate power and performance jointly at a high speed [10]and a high accuracy comparable to gate-level simulation [11]. However, both ofthem require SW images, which are unavailable for early design phase.

In order to overcome all the challenges mentioned above, an Approximately-Timed Task-Accurate (ATTA) and power-state-based methodology is proposedfor three prominent advantages [12]: a) very fast power-performance evaluationfor entire heterogeneous platforms including both HW and SW aspects; b) appli-cable to very early design phases, even in specification phase; c) allowing for theDPMP exploration efficiently by modeling power behaviors explicitly and sep-arately with application behaviors. In [12], sufficient accuracy for early designphases, high simulation speed and less modeling effort are validated via modelingan existing mobile communication platform. Further comprehensive evaluationsare required to show that this methodology is applicable to early design phases ofnew generation platforms. Therefore, this paper contributes with the evaluationof this methodology in two aspects:

– applicability for a future HW/SW platform.

– flexibility and reusability for the early-phase what-if analysis of HW/SWarchitecture.

To achieve these, two industrial design cases are investigated. In the first one,an existing platform supporting GSM paging burst is discussed to elaborate themodeling approach in detail. Based on this, a novel platform for paging burstis modeled to evaluate applicability for future HW/SW platforms, as well asflexibility and reusability.

The rest of this paper is organized as follows: Section 2 gives an overviewof the methodology in [12]. In Section 3, two design cases are investigated toelaborate and evaluate the methodology. The paper is concluded in Section 4.

ESL Power Estimation: A Design Case Study for Early Design Phases 3

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Fig. 1. Framework for system-level power analysis of SoCs platform

2 Methodology Overview

The proposed ESL framework for power evaluation [12] is shown in Fig. 1, com-posed of four parts: use case models, HW resource models, a Mapping&ParameterAnnotations (MPA) and a Power&Performance Monitor (PPM). The method-ology is based on the Y-chart approach, separating the modeling of use casebehavior from HW architecture. The implementation-agnostic behavior modelis mapped to HW resources together with parameter annotations to evaluateperformance and power consumption of a system using a simulation-based ap-proach. This back-annotated approach enables to include low level informationinto the high level model and it is achieved through the MPA.

The application behavior model abstracts the use case functionality whichis scheduled and executed on the respective HW resources. The annotated ex-ecution time of each functional activity are used to evaluate its performance.The power behavior of HW resources are explicitly described via the models ofPower State Machine (PSM) and Dynamic Power Management Policy (DPMP),and mapped to the corresponding HW resources. A power consumption value isannotated to each power state, and the transition of power states is driven byDPMP. The power related stimuli are considered via environmental events, e.g.timer interrupt.

During the simulation, a PPM monitors the timing information of tasks andpower states of HW resources, and produces traces to enable system architect-s to analyze the joint performance and power characteristics dynamically andefficiently. We will discuss in more detail the modeling of HW architecture, ap-plication behavior, and power behavior.

The architecture model is specified through an XML annotation file [13].The HW resources are parameterized by providing: a) power attributes, i.e. thepower consumption values for each defined power state, and b) performanceattributes, i.e. the scheduling policy of processing elements and power-state-

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dependent transaction delay for communication. In reality, multiple settings ofpower supply voltage and clock frequency are designed for each HW resource.Each of them could be abstracted as a power state. The number of the modeledpower states depends on the granularity desired. To consider different activityfactors of the resource over time, multiple execution phases within a power statecould be characterized to further refine power level.

Our methodology applies an actor-oriented modeling approach to model theapplication behavior/functionality. A SystemC-based language is used as theactor-oriented modeling infrastructure [14]. In this language, application func-tionality is modeled using communicating actors. Each actor explicitly separatesthe computation from the communication behavior. For the computation behav-ior, a coarse-level granularity is defined to annotate the timing information of agiven functional activity for performance evaluation. This enables to do a veryearly design phase modeling for application functionalities. Actors communicatethrough channels with FIFO semantics, and their communication behavior isdriven by a Finite State Machine (FSM). The FSM defines two elements foreach communication state transition: a) the conditions, namely the availabilityof data tokens at the actor input/output ports and boolean guards, and b) theaction to be performed during transition. A entire system behavior model is anetwork consisting of interconnected actors. The mapping between these actorsand HW resources will determine system performance and power consumption.Additionally, the routing of communication data through the HW componentsis also provided to take into account contention effects on interconnections.

For each resource, the power state transitions are under the control of aDPMP. Two types of models are built to describe the power behavior, namelyPSM and DPMP models. The PSM model describes the transition conditionsand actions from one power state to another. DPMP is modeled as an actor totrigger the power state transition of PSMs. The execution phases within a powerstate is controlled by HW scheduler. The interaction among environment stimuli,DPMP, PSM and the execution phases abstracts the entire power behavior ofthe platform. Additionally, the power state transition timing penalty can be alsotaken into account by annotating a timing value to a power state transition.

3 Design Case Study

In this section, two real-world design cases in mobile communications are inves-tigated: a) a legacy SW/HW solution for GSM paging burst and b) a shortenedsolution for paging burst.

In mobile communications, paging is a special mode to synchronize with thewireless base station and locate mobile subscribers. In order to save power andextend battery life, most of system components are switched off or go to sleepmode when the system is idle. During this period, a cellular phone periodicallywakes up and switches on the corresponding components to receive and processa paging message from a base station. If the paging message indicates no call

ESL Power Estimation: A Design Case Study for Early Design Phases 5

is coming, the phone goes to sleep again and runs at a very low power level,waiting for the next paging message.

We study this scenario for two reasons:

– comprehensive SW/HW, digital/RF components are involved, which is acomplex heterogeneous system.

– dynamic power management activities and power state transitions are per-formed.

The modeling approach is elaborated in detail in the design case of the legacyGSM paging burst – an existing solution. Based on this solution, the concep-t of the shortened paging burst is proposed. The development of the platformincluding SW and HW is investigated in specification phase using the method-ology in Section 2. Applicability, flexibility and reusability of the methodologyis evaluated at a novel platform.

All the behavior models are built in SystemC in an actor-oriented style andall the simulations are executed on a Linux machine with 2 GB memory and a3 GHz CPU.

3.1 Legacy GSM Paging Burst

Modeling Architecture and Resources We modeled the dominant compo-nents involved during paging burst in a real cellular SoC. The simplified archi-tecture is shown in Fig. 2 (a), including a CPU, a DSP subsystem, a memorysubsystem, a Power Management Unit (PMU), a dedicated HW accelerator, aDigRF, and a RF receiver and interconnection. The PMU controls the powersupply for each system component and implements the system-level DPMP. Ageneric RF receiver was modeled as well to co-simulate the interaction betweenthe baseband and RF parts.

As explained in Section 2, the power and performance attributes of eachcomponent are modeled and specified in the Mapping&Parameter Annotations.As an example, modeling of the CPU is elaborated. The attributes of its modelare specified in the annotation file shown in Fig. 2 (b). For the power attribute,four power states were abstracted, OFF (no power supply), LOW (low powersupply voltage and frequency), HIGH (high power supply voltage and frequen-cy), and WFI (wait for interrupt). Additionally, to improve modeling accuracy,three execution phases were characterized in LOW and HIGH power states. TheRUNNING phase represents the CPU is executing tasks with full load. The I-DLE phase represents no tasks are executing on the CPU. The STALLED phaseindicates the CPU is occupied by a task but waiting for other resources, e.g.data from a memory transaction. For the performance attribute, the First ComeFirst Serve (FCFS) policy was assigned as the scheduler of the CPU. And thepower-state-dependent transaction delays were annotated as well, consideringthe coupling effect between power and communication performance. The pa-rameter values in the annotation file were extracted from measurements. Othercomponents shown in Fig. 2 (a) were modeled in the same way. But only two

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Interconnetion

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Fig. 2. Hardware architecture and modeling (a) Simplified architecture of a cellularSoC (b) Annotation file for CPU Model

power states were abstracted, ON and OFF. This takes into account the settingsof supply voltage and frequency in each component, and the desired accuracy ofmodeling.

Modeling Application and Power Behavior The coarse-level task flowof the application behaviors mapped on the CPU was modeled as an actor,shown in Fig. 3(a). During paging burst, the CPU wakes up and executes aseries of the paging configuration and processing tasks, A, B, C, etc. If no call iscoming, the CPU goes to sleep again. Only the task activities in the specificationswere modeled without the need of any implementation details. Moreover, themethodology allows to model the interaction effects among the tasks running onthe different HW resources. This was modeled via communication channels. Forexample, the task A writes the processed data into memory and the DSP sendsan interrupt to notify CPU that a computation has finished. The applicationbehavior models of other components were built in the same way.

The power behavior models are built by DPMP and PSM models. To optimizethe overall power consumption of the platform, a centralized system-level DPMPis applied via PMU and controls the power behavior of each HW resource thatdoesn’t have its own DPMP. To model this, we built the only DPMP model inthe system and mapped it on the PMU. Further, the PSMs of each componentwere modeled. The DPMP model decides the power states of each component.If applications want to change the power state, they may send a request tothe DPMP model. Take the CPU power behavior model as an illustration. TheDPMP model of the PMU is shown in Fig. 3(b) (only parts of the DPMP model)and the PSM of the CPU is shown in Fig. 3(c). The DPMP receives the wake-upstimulus from the environment and triggers the CPU PSM, which checks thetransition condition and switch the power states from OFF to LOW. Then theapplication running on the CPU starts a wake-up setup and other paging tasks.

ESL Power Estimation: A Design Case Study for Early Design Phases 7

CPU_App_Actor

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Fig. 3. Application and power behavior model. (a) Application behavior mapped onthe CPU (b) DPMP model of PMU (c) PSM model of CPU

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Fig. 4. Application and power behavior model in shortened GSM paging burst. (a)Application behavior mapped on the CPU (b) DPMP model of PMU (c) PSM modelof CPU

The application could also request the DPMP to switch the power states of theCPU, e.g. from LOW to HIGH when the system is busy and from HIGH to WFIwhen idle. After paging completes, the DPMP switches off the CPU.

The mapping of behavior models on the HW models is specified in the MPA.The timing information of tasks is extracted from trace files and annotated ina power-state-dependent way, taking in account the coupling effects betweenpower and computation performance.

Simulation Result Analysis Fig. 5 (a) shows the simulated and measuredpower consumption of the baseband part (without RF power consumption) dur-ing GSM paging burst (normalized with respect to the highest value in themeasurement). In the sleep phase, the most of system components are switchedoff and the power consumption is nearly zero. Then the system wakes up andrestores configuration of each component before asleep for the last time. During

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this phase, the power consumption is not so high since some components arerunning in the low power state, e.g. CPU. When the system starts paging tasks,the system enters the high power state to achieve high performance. During thisphase, system could go into the WFI power state to save power when the systemis idle and come back when busy. This also indicates that the system has sparecomputation capability.

The methodology achieves: a) sufficient accuracy for early design phases, b)high simulation speed and c) less modeling effort [12].

3.2 Shortened GSM Paging Burst

In order to reduce the power consumption during paging burst, a novel concept,namely shortened GSM paging burst is proposed. The concept is to explorethe parallelism between tasks and execute tasks concurrently, instead of in adedicated processing window or a paging frame. As a consequence, the totalpaging-mode time may be reduced, resulting in the shorter awake time of thesystem. This can achieve a lower energy consumption and a longer standby timeof cellular phone. But the feasibility and the optimal SW/HW architecture mustbe evaluated in early design phases.

Modeling Architecture and Resources Since the existing HW architecturehas spare processing capability, the exploration of HW platform for the shortenedpaging is still based on the legacy platform as the first step to evaluate theperformance and power. Some HW units might be changed, e.g. timers, buthave little effects on power consumption. These changes were ignored duringmodeling. As seen in Section 3.1, the modeling granularity of power states andexecution phases is suitable to achieve sufficient accuracy for early design phases.For this reason, the modeling of power states and the power consumption valueswere maintained for each HW resource. The scheduling policies were unchangedas well. As a consequence, the models of the legacy HW platform can be reusedcompletely. This reusability is quite important and exactly matches a typicalprogress of products development, i.e. a novel platform is largely based on thelegacy generation.

Modeling Application and Power Behavior Given the unchanged dynam-ic power management policy of the system, only plenty of application tasks arerescheduled to achieve higher parallelism. Fig. 4 shows how to model these effectsin the application behavior model. For example, the task B mapped on the CPUwas executed in a dedicated time window in the legacy scheduling shown in Fig.3. According to the new concept, task B is split to subtasks B1 and B2 whichare concurrently executed with task A and task C, respectively. This can bemodeled easily in the application behavior model. However, the accurate timinginformation of B1 and B2 is unavailable without any concrete implementationinformation. In this case, the extrapolated values based on last generation prod-ucts can be used. Considering the subtasks B1 and B2 are supposed to achieve

ESL Power Estimation: A Design Case Study for Early Design Phases 9

the similar functionalities as the legacy task B did, we assumed the sum of theirexecution time is equal to that of the task B. Further, we speculated reasonabletiming information for B1 and B2, taking into account their probable workload.Because the DPMP of the system is unchanged, the power behavior models canbe reused from the legacy paging solution, including the DPMP model mappedon PMU and CPU PSM model. It is shown that the modification of models isquite flexible. Modeling the changes of application behavior doesn’t influencepower behavior models. The same approach was applied to other rescheduledtasks to complete application and power behavior models. The mapping betweenbehavior model and HW resource is unchanged in the MPA.

Simulation Result Analysis The simulation result in Fig. 5 (b) shows thebaseband current over time. The current is normalized with respect to the max-imum measurement current in the legacy platform for paging burst. Comparedto the legacy platform, the peak 2 doesn’t exist in shortened paging solution be-cause of rescheduling of tasks which were executed in a dedicated time window.The peaks 1, 3, 4 and 5 are wider than the corresponding peaks in the legacypaging. The reason is that the concurrent execution of the rescheduled tasks oc-cupies HW resources for a longer time. However, the overall system-awake timeis shortened by 4.4 ms. This is a reduction of 22.6%.

To evaluate the power savings, energy consumption during paging burst wascalculated. A reduction of 14.9% is achieved compared to the legacy pagingsolution. If taking into account also the leakage current during system sleep be-tween two consecutive paging modes, the overall energy consumption decreasesby 6.7% when the phone is in the standby mode and only receives paging mes-sages periodically. This directly results in an increased mobile phone standbytime.

The models are highly flexible and reusable. Since application behaviors,power behaviors and HW resources are modeled separately, any modification inone aspect can be achieved easily and independently, and doesn’t influence otheraspects. This allows for the considerable reuse in other aspects. For these reasons,modeling and programming the shortened paging design case took less than 2days for one engineer. The simulation is very fast, only running around 100 ms.It is concluded that the ESL power analysis methodology in [12] is applicable towhat-if analysis in early design phases in a time-efficient and accurate way forfuture mobile communication platforms.

4 Conclusion

In this paper two industrial design cases are investigated to evaluate an existingESL power estimation methodology for early design phases. At first, the model-ing approach is elaborated in detail by studying an existing platform supportingGSM paging burst. Based on this, a novel SW/HW architecture is modeled andanalyzed with respect to the power and performance. It is estimated that thepaging period is shortened by 4.4 ms, translating to a reduction of 22.6%. As a

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Fig. 5. Baseband power consumption over time. (a) Simulation and measurement re-sult of legacy paging solution (b) Simulation result comparison between legacy andshortened paging solutions

consequence, the energy consumption decreases by 14.9% during paging burst,and the standby time of the phone is extended by 6.7%. The modeling work isfinished within 2 days for one engineer and the simulation runs only for 100 ms.It’s shown that the methodology is flexible enough to model any variations inone aspect of application behaviors, dynamic power management policies andHW resources without influences on other aspects. The models of the existingplatform are highly reusable to achieve very less modeling effort when evaluat-ing the new generation platform. The methodology is applicable to the what-ifanalysis of HW/SW architecture in early design phases.

Acknowledgments. This work was supported in part by the Project Pow-erEval (funded by Bayerisches Wirtschaftsministerium, Bavaria, Germany undersupport code IUK314/001)

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