Ese570 mos theory_p206
Transcript of Ese570 mos theory_p206
1
EE 560MOS TRANSISTOR THEORY
EE 560MOS TRANSISTOR THEORY
Kenneth R. Laker, University of Pennsylvania
PART 2
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GCA (gradual channel approximaton) MOS Tranistor ModelStrong Inversion Operation
Kenneth R. Laker, University of Pennsylvania
2
VS = 0 V
DS =V
D = V
DSAT
channel
VDS
=VD = small
nMOS TRANSISTOR IN LINEAR REGION
nMOS TRANSISTOR AT EDGE OF SATURATION REGION
pinch-off point
SiO2
depletion regionsubstrate or bulk B p
VS = 0
channel
ID
substrate or bulk B p
depletion region
SiO2
CGC
CBC
CGC
CBC
VGS
= VG > V
T0
VGS
= VG > V
T0
Kenneth R. Laker, University of Pennsylvania
3
nMOS TRANSISTOR IN SATURATION REGION
VS = 0
pinch-off point
channel
depletion region
substrate or bulk B p
SIO2
CGC
CBC
VDS - VDSAT
VCS(y) = VDSAT
x
y = 0
y
VGD
= VG - V
D < V
T0
VDS
= VD > V
DSATVGS
= VG > V
T0
ID
substrate or bulk B p
VS = V
B = 0
VDS
y = L
yx
y = 0
dy
Sourceside
Drainside
y = Ly = 0 y Channel length = L
inversion layer (channel)
Channel width = W
Kenneth R. Laker, University of Pennsylvania
4MOSFET CURRENT - VOLTAGE CHARACTERISTICS
CGC
CBC
VGS
= VG > V
T0
5MOSFET CURRENT - VOLTAGE CHARACTERISTICS
Kenneth R. Laker, University of Pennsylvania
Mobile charge in channel:
µn = electron mobility
= cm2/Vsec[µ −> U0 in SPICE]
dR = − dyW
1µ n QI (y)
QI(y) = −Cox[VGS − VCS(y) − VT 0 ]C
C/s
Incremental R for differential channel segment
VG > V
T0 ID
substrate or bulk B p
VS = V
B = 0
VDS
y = L
yx
y = 0V
CS(y)
CGC
CBC
VGS
= VG > V
T0
Assumptions:V
T0(y) = V
T0
VGS
> VT0
VGD
= VGS
- VDS
> VT0
Ey >> E
x
Boundary conditions:V
CS(y = 0) = V
S = 0
VCS
(y = L) = VDS
(C/cm2)
6MOSFET CURRENT - VOLTAGE CHARACTERISTICS
Kenneth R. Laker, University of Pennsylvania
dVCS = IDdR = − ID
Wµn QI (y)dy
dR = − dyW
1µ n QI (y)
QI(y) = −Cox[VGS − VCS(y) − VT 0 ]
IDdy = −W µn0
L
∫ Q I (y)0
VDS
∫ dVCS
i.e.
= W µn Cox[(VGS− VT 0 ) VDS − VDS2 / 2]
ID = µn Cox
2WL
[2(VGS− VT 0 ) VDS − VDS2 ]
Integrating along the channel 0 < y < L and 0 < VCS
< VDS
:
Voltage drop across incremental segment dy
Boundary conditions:V
CS(y = 0) = V
S = 0
VCS
(y = L) = VDS
ID = µn Cox
2WL
[2(VGS− VT 0 ) VDS − VDS2 ]
Kenneth R. Laker, University of Pennsylvania
7MOSFET CURRENT - VOLTAGE CHARACTERISTICS
= k'2
WL
[2(VGS− VT 0 ) VDS − VDS2 ]
= k2
[2(VGS− VT 0 ) VDS− VDS2 ]
k' = µ n Cox
[k' -> KP in SPICE]
k = k'WL
Kenneth R. Laker, University of Pennsylvania
8MOSFET CURRENT - VOLTAGE CHARACTERISTICSEXAMPLE 3.4For an n-MOS transistor with µ
n = 600 cm2/Vsec, C
ox = 7 x 10-8 F/cm2,
W = 20 µm, L = 2 µm, VT0
= 1.0 V, plot the relationship between ID
and VDS
, VGS
.
k = µ n Cox
WL
= (600cm2/Vsec)(7x10−8 F/cm2 )20µ m2µ m
= 0.42 mA/V2
ID = k2
[2(VGS − VT 0 ) VDS − VDS2 ] where k = µ n Cox
WL
F = C/V
ID = 0.21mA/V2[2(VGS −1.0)VDS− VDS2 ]
ID (mA)
VDS
(V)0
2.0
4.0
1.0 3.0 5.0
VGS
= 5V
VGS
= 4V
VGS
= 3V
VDS
= VGS
- VT0V
DS ≤ V
GS − V
T0 Assumptions:V
GS > V
T0
VGD
= VGS
− VDS
> VT0
LINEAR OR TRIODE REGION
9MOSFET CURRENT - VOLTAGE CHARACTERISTICS
Kenneth R. Laker, University of Pennsylvania
VDS
≥ VGS
- VT0
= VDSAT SATURATION REGION
ID = µn Cox
2WL
[2(VGS− VT 0 ) VDS − VDS2 ] @V
DS = V
DSAT = V
GS - V
T0
= µ n Cox
2WL
[2(VGS − VT 0 )(VGS − VT 0 ) − (VGS− VT 0 )2]
ID (sat) = µn Cox
2WL
(VGS− VT 0 )2
ID (mA)
VDS
(V)0
2.0
4.0
1.0 3.0 5.0
VGS
= 5V
VGS
= 4V
VGS
= 3V
VDS
= VGS
- VT0
LINEAR SAT
ID(sat)
VGS
VT0
10MOSFET CURRENT - VOLTAGE CHARACTERISTICS
Kenneth R. Laker, University of Pennsylvania
CHANNEL LENGTH MODULATION
Boundary conditions:V
CS(y = 0) = V
S = 0
VCS
(y = L) = VDS
QI(y) = −Cox[VGS − VCS(y) − VT 0 ]
QI(y = 0) = −Cox[VGS − VT 0]
= 0 @ VDS
= VDSAT
L' = L − ∆L effective channel lengthV
CS(y = L') = V
DSAT
VS = 0
substrate or bulk B p
LL'∆L
Q1(y = L) = −Cox[VGS− VDS− VT 0 ]
CGC
CBC
VGS
=VG > V
T0V
DS =V
D > V
DSAT
Kenneth R. Laker, University of Pennsylvania
11MOSFET CURRENT - VOLTAGE CHARACTERISTICS
ID (sat) = µn Cox
2WL'
(VGS− VT 0 )2 = µn Cox
2W
L(1 − ∆ L
L)(VGS− VT 0 )2
∆ L ∝ VDS − VDSATwhere
1
1− ∆ L
L
= 1 + λVDSemperical relation:
λ = channel length modulation coefficent (V-1)
[λ -> LAMBDA in SPICE]
VS = 0
substrate or bulk B p
LL'∆LC
GC
CBC
VGS
=VG > V
T0V
DS =V
D > V
DSAT
ID (sat) = µn Cox
2WL'
(VGS− VT 0 )2 = µn Cox
2W
L(1 − ∆ L
L)(VGS− VT 0 )2
12MOSFET CURRENT - VOLTAGE CHARACTERISTICS
Kenneth R. Laker, University of Pennsylvania
1
1− ∆ L
L
= 1 + λ VDS
ID (mA)
VDS
(V)0
2.0
4.0
1.0 3.0 5.0
VGS
= 5V
VGS
= 4V
VGS
= 3V
VDS
= VGS
- VT0
λ ≠ 0
λ ≠ 0
λ ≠ 0
assume λVDS
<< 1
ID (sat) = µn Cox
2WL
(VGS− VT 0 )2 (1+ λ VDS) LEVEL 1 Model
13MOSFET CURRENT - VOLTAGE CHARACTERISTICS
Kenneth R. Laker, University of Pennsylvania
SUBSTRATE BIAS EFFECT
ID = f(V
GS, V
DS, V
SB)
(sat)
LEVEL 1 Model
14MOSFET CURRENT - VOLTAGE CHARACTERISTICS
Kenneth R. Laker, University of Pennsylvania
ID
D
G B
S
+
+
+-V
GS
VDS
VSBI
D
D
G B
S
+
+
+-VGS
VDS
VSB
n-MOS p-MOS
n-MOS for
VGS > VT, VDS < VGS - VT
p-MOS
VGS < VT, VDS > VGS - VT
ID = 0 VGS ≤ VT
forID = 0 VGS ≥ VT
VGS < VT, VDS < VGS - VT
VGS > VT, VDS > VGS - VT
-- -
-
15MOSFET CURRENT - VOLTAGE CHARACTERISTICS
Kenneth R. Laker, University of Pennsylvania
kn = µ n Cox
WL
kp = µ p Cox
WL
MEASUREMENT OF PARAMETERS (VT0
, γ, λ, kn, k
p)
ID (sat) = kn
2(VGS− VT 0 )2
ID(sat) = kn
2(VGS − VT 0 )
ID
D
GB
S
+
+V
GS
VDS
= VGS
VSB
VT1
ID
VGS
VT0
VSB
= 0 VSB
> 0
Gamma
16MOSFET CURRENT - VOLTAGE CHARACTERISTICS
Kenneth R. Laker, University of Pennsylvania
ID
D
GB
S
+
VGS
= VT0
+ 1 V
VDS
> VGS
- VT0
VBS
= 0
+
Lambda
VDS
ID
ID1
ID2
VDS1
VDS2
VGS
= VT0
+ 1 ID (sat) = kn(VGS− VT 0 )2 (1+ λ VDS)
VGS
= VT0
+ 1 V
ID 2
ID1
= 1+ λVD S 2
1 + λ VDS1
DC current meter
Kenneth R. Laker, University of Pennsylvania
17EFFECTIVE CHANNEL LENGTH AND WIDTH
Leff
= LM - 2LD - DL
SPICE Parameters
LD -> under diffusion
DL -> error in photolith and etch
Weff
= WM - DW
SPICE Parameters
DW -> error in photolith and etch
n+
p
GDS
n+
CGC
CBCn+ n+
LD
Leff
LM
LD
B
substrate or bulk B p
L
EFFECTIVE CHANNEL LENGTH AND WIDTH
CGC
CBC
18MOSFET - SCALINGSCALING -> refers to ordered reduction in dimensions of the MOSFET and other VLSI features• Reduce Size of VLSI chips.• Change operational charateristics of MOSFETs and parasitics.• Phyiscal limits restrict degree of scaling that can be achieved.
First-order "constant field" MOS scaling theory:
The electric field E is kept constant, and the scaled device is obtained by applying a dimensionless scale-factor α to reduce dimensions by (1/α) and maintain E unchanged:
a. All dimensions, including those vertical to the surface (1/α)
b. device voltages (1/α)
c. the concentration densities (α).
Kenneth R. Laker, University of Pennsylvania
SCALING FACTOR = α > 1 --> S
α(1/α) = 1(1/α)/(1/α) = 1<=>
Constant Voltage Scaling, i.e. VDD
is kept constant, while the process dimensions are scaled by (1/α).
a. All dimensions, including those vertical to the surface (1/α)
b. device voltages (1)
c. the concentration densities (α2) to preserve charge-field relations.
Lateral Scaling: only the gate length is scaled L = 1/α (gate-shrink).
Alternative Scaling Rules:19MOSFET - SCALING
Kenneth R. Laker, University of Pennsylvania
Feature Size(µm)
Year 1991 1993 1997 1999 2001 2003 2005
1.00 0.80 0.60 0.35 0.25 0.18 0.13 0.09
Historical reduction in min feature size for typical CMOS Process
α2(1/α) = α1/(1/α) = α
<=>
1995
Kenneth R. Laker, University of Pennsylvania
20Influence of Scaling on MOS Device Performance
PARAMETER SCALING MODEL
Constant Field Constant Voltage Lateral
Length (L) 1/α 1/α 1/α
Width (W) 1/α 1/α 1
Supply Voltage (V) 1/α 1 1
Gate Oxide thickness (tox
) 1/α 1/α 1
Junction depth (Xj) 1/α 1/α 1
Substrate Doping (NA) α α2 1
Current (I) - (W/L) (1/tox
)V2 1/α α α
Power Dissipation (P) - IV 1/α2 α α
Power Density (P/Area) 1 **(α3)** α2
Electric Field Across Gate Oxide - V/tox
1 α 1
Load Capacitance (C) - WL (1/tox
) 1/α 1/α 1/α
Gate Delay (T) - VC/I 1/α 1/α2 1/α2
Kenneth R. Laker, University of Pennsylvania
21MOSFET CAPACITANCES
n+
p
GDS
n+
CGC
CBCn+ n+
LD
Leff
LM
LD
B
p
n+ n+
LD
LD
Y
CGC
CBC
p
substrate or bulk B
substrate or bulk B
22MOSFET CAPACITANCES
Kenneth R. Laker, University of Pennsylvania
S
MOSFET
(DC MODEL)
D
BG
Cgd
Cgs
Cgb
Cdb
Csb
Cgd
, Cgs
, Cgb
-> Oxide Capacitances
Cdb
, Csb
-> Junction Capacitances
23MOSFET CAPACITANCES
OXIDE Capacitances
a. Overlap Caps
Cox = εoxtox
b. Gate - ChannelMOSFET - Cut-off Region
Cgb
= Cox
W Leff
Cgs = Cgd = 0
Kenneth R. Laker, University of Pennsylvania
p
CGS0(overlap) = Cox W LD
CGD0(overlap) = Cox W LD
ALL MOSFET OPERATION REGIONS
CGB0(overlap) = Cox WovLeff
SPICE: Cox
LD = CGS0; C
oxL
D = CGD0; C
oxW
ov = CGB0
LD = LD in SPICE
Cgb
, Cgb
and Cgb
(no conducting channel in cut-off)
Kenneth R. Laker, University of Pennsylvania
24MOSFET CAPACITANCESb. Gate - Channel
Cgb
= 0
Cgs
= (1/2) Cox
W Leff
MOSFET - Linear Region
Cgd
= (1/2) Cox
W Leff
Cgb
= 0
Cgs
= (2/3) Cox
W Leff
Cgd
= 0
p
p
Kenneth R. Laker, University of Pennsylvania
25
Capacitance Cut-off Linear Saturation
Cgb
(total)
Cgd
(total)
Cgs
(total)
Cox
WLeff
+ CGB0
0 + CGB0
0.5Cox
WLeff
+ C
GD0
(2/3)Cox
WLeff
+ CGS0
(C/Cox
WL)
VGS
SaturationCut-off Linear
VT
VT + V
DS
1
2/31/2
Cgb C
gs
Cgd
0 + CGD0
0 +CGS0
0.5Cox
WLeff
+ C
GS0
Gate -to Channel/Bulk Cap Contribution
0 + CGB0
0 + CGD0
CGS0
CGD0
=C
GB0
Kenneth R. Laker, University of Pennsylvania
26JUNCTION Capacitances -> Cdb
, Csb
p xd
xj
Channeln+ n+W
xj
Y
1
2
3
4
5
DrainSource
Channeln+ n+W
xj
Y
1
2
3
4
5
DrainSource
Kenneth R. Laker, University of Pennsylvania
27JUNCTION Capacitances -> Cdb
, Csb
Junction Area Type
1
2
3
4
5
W xj
Y xj
W xj
Y xj
WY
n+/p
n+/p
n+/p+
n+/p+
n+/p+
p - Substrate -> NA
p+ - Channel-stop -> 10NA
[xj -> XJ in SPICE]
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Kenneth R. Laker, University of Pennsylvania
φ0 = kTq
lnNAND
n i2
built-in junction potential
xd = 2εSi
q1
NA
+ 1ND
(φ0 − V) V = Ext bias --> V
BD , V
BS
Q j = AqNAND
NA + ND
xd = A 2εSi q
NAND
NA + ND
(φ0 − V)
Depletion-region charge
px
d
xj
NA
ND
JUNCTION Capacitances -> Cdb
, Csb
n+, p junctions
A = junction area
[AS, AD -> Source, Drain Areas in SPICE]
[φ0 -> PB in SPICE]
29
Kenneth R. Laker, University of Pennsylvania
Cj(V) = C
j0 when V = 0
m = grading coefficentm = 1/2 for abrupt junction
[m = MJ in SPICE]
EQUIVALENT LARGE SIGNAL CAPACTIANCE
(F/cm2)
(F)
C j0 = εSi q2
NAND
NA + ND
1φ0
0 < Keq
< 1 --> Voltage Equiv Factor
[Cj0 -> CJ in SPICE]
[φ0 -> PB in SPICE]
n+, p+ junctions30
Kenneth R. Laker, University of Pennsylvania
(Sidewalls)
C j 0 s w = εSi q2
NA (sw)ND
NA (sw) + ND
1φ0 s w
(F/cm2)
Since all sidewalls have depth = xj:
(F/cm)
m(sw) = 1/2
EQUIVALENT LARGE SIGNAL CAPACTIANCE
P = sidewall perimeter
[m(sw) -> MJSW in SPICE]
[Cjsw
-> CJSW in SPICE]
[xj -> XJ in SPICE]
[PS, PD -> Source, Drain Perimeters in SPICE]
Cjsw
= Cj0sw
xj
Keq (sw) = − 2φ0 s w
(V2 − V1)1 − V2
φ0 s w
1 /2
− 1 − V1
φ0 s w
1 /2
31
Kenneth R. Laker, University of Pennsylvania
EXAMPLE 3-8Determine the total junction capacitance at the drain, i.e. C
db, for
the n-channel enhancement MOSFET in Fig. 1. The process parameters are
Substrate doping NA = 2 x 1015 cm-3
Source/drain (n+) doping ND = 1020 cm-3
Sidewall (p+) doping NA(sw) = 4 x 1016 cm-3
Gate oxide thickness tox
= 45 nmJunction depth x
j = 1.0 µm
10 µm
5 µm
2 µm
n+ n+
G
D S
Figure 1
Source, Drain are surrounded by p+ channel-stop. The substrate is biased at 0V. Assume the drain voltage range is 0.5 V to 5.0 V.
C j 0 s w = εSi q2
NA (sw)ND
NA (sw) + ND
1φ0 s w
C j0 = εSi q2
NAND
NA + ND
1φ0
where
32
φ0 = kTq
lnNAND
n i2
= 0.026Vln
(2x1015)1020
2.1x1020
= 0.896V
10 µm
5 µm
2 µm
n+ n+
G
D S
Figure 1
NA = 2 x 1015 cm-3
ND = 1020 cm-3
NA(sw) = 4 x 1016 cm-3
tox
= 45 nmx
j = 1.0 µm
φ0, φ
0sw
φ0 s w = kTq
lnNA (sw)ND
ni2
= 0.026Vln
(4 x1016 )1020
2.1x1020
= 0.975V
C j0 = εSi q2
NAND
NA + ND
1φ0
= (1.04x10−12 F/cm)(1.6x10−19 C)2
(2x1015)1020
2x1015 +1020
10.896V
= 1.35x10−8 F/cm2
33
Kenneth R. Laker, University of Pennsylvania
Cj0, C
j0sw
F = C/V
34
Kenneth R. Laker, University of Pennsylvania
C j0 sw = εSi q2
NA (sw)ND
NA(sw) + ND
1φ0sw
= (1.04 x10−12 F/cm)(1.6x10−19 C)2
(4 x1016)1020
4x1016 + 1020
10.975V
= 5.83x10−8 F/cm2
Cjsw
Cjsw
= Cj0sw
xj = (5.83x10−8 F/cm2 )(10−4 cm) = 5.83pF/cm
Keq
, Keq
(sw)V
BD2 = V
B - V
D2 = 0 - 5V = -5V
VBD1
= VB - V
D1 = 0 - 0.5V = -0.5V
and xj = 1.0 µm = 10-4 cm
Kenneth R. Laker, University of Pennsylvania
Area, Perimeter
10 µm
5 µm
2 µm
n+ n+
G
D S
Figure 1
AD: n+/p junctions:
AD = (5 x 1) µm2 + (10 x 5) µm2
= 55 µm2
PD: n+/p+ junctions:
PD = 2Y + W = 20 µm + 5 µm = 25 µm
Channeln+ n+
W = 5 µm
xj = 1µm
Y=10µm
1
2
3
4
5
DrainSource
PD
35
Short Channel Effects - Leff
--> xj
Narrow Channel Effects - W --> xdm
Kenneth R. Laker, University of Pennsylvania
36
Subthreshold Current - VGS
< VT0
Important 2nd Order Effects
VELOSITY SATURATIONMobility Degradation due to Lateral Electric Field:
(very small channel lengths + high supply voltages)
velosity(vD)
E
vDsat
slope = µ0
slope µs
Ecrit
µ0 = v
sat/E
crit
Note µs < µ
0
[SPICE Parameters: U0 -> µ0, UCRIT -> E
crit, VMAX -> v
sat]
ID(sat) = W v
DSAT C
ox (V
GS - V
T)
Kenneth R. Laker, University of Pennsylvania
36
Note: ID(sat) = linear f(V
GS - V
T), independent of L
Ey
Mobility Degradation due to Normal Electric Field:(due to gate voltage across very thin oxide-depletion layer)
[SPICE Parameter: THETA -> θ]
Ex
θ = imperical mobility modulation factor
37
Short Channel Effect - Leff
--> xj (source, drain diffusion depth)
Kenneth R. Laker, University of Pennsylvania
VT0
(short channel) = VT0
- ∆VT0
∆LS, ∆L
D = lateral extensions at source, drain of depletion
region due to reverse biased sourse, drain junctions with substrate
Narrow Channel Effect - W --> xdm
(depletion region depth)
[SPICE Parameter: DELTA -> δ = imperical channel width factor]
VT0
(narrow channel) = VT0
+ ∆VT0
Subthreshold Current - VGS
< VT0
(Spice Model)
Ion = ID in strong inversion and VGS = Von is the boundary weak and strong inversion
Kenneth R. Laker, University of Pennsylvania
38SPICE SIMUATION - MODELSLevel 1 (MOS1) - analylitical mode, I
D(sat) is described by square
law - strong inversion (with Channel Length Modulation). Based on GCA (gradual channel approximaton) equations in Ch3.
Level 2 (MOS2) - anaylitical model, more detailed than MOS1. Includes second order effects, e.g. mobility degradation, small channel effects and sub-threshold currents. Relaxes some simplifying GCA assumptions.
Level 3 (MOS3) - semi-emperical model. Uses simpler expressions than MOS2 plus emperical equations to fit experimental data. Improves accuracy and reduces simulation time.
BSIM3 (Berkeley Short-Channel IGFET Model) - includes sub-micron MOSFET characteristics. Analytically simple, makes full use of parameters extracted from experimental data.
M1 4 3 5 0 NFET W=4U L=1U AS=15P AD=15P PS=11.5U PD=11.5U....MODEL NFET NMOS+ TOX=200E-10+ CGBO=200P CGSO=300P CGDO=300P+ CJ=200U CJSW=400P MJ=0.5 MJSW=0.3 PB=0.7
M1 4 3 5 0 NFET W=4U L=1U AS=15P AD=15P PS=11.5U PD=11.5U D G S B
SPICE MODELING OF MOS CAPACITANCES
Cgb
= W × L × Cox
= (4E-6 m) × (1E-6 m) × (17E-3 F/m2) = 6.8 fF
U = 10-6
P = 10-12
m
m F/m
F/mF/m2
m2 m
V
Kenneth R. Laker, University of Pennsylvania
39
M1 4 3 5 0 NFET W=4U L=1U AS=15P AD=15P PS=11.5U PD=11.5U..MODEL NFET NMOS+ TOX=200E-8+ CGBO=200P CGSO=300P CGDO=300P+ CJ=200U CJSW=400P MJ=0.5 MJSW=0.3 PB=0.7
CJ = zero-bias junction capacitance per junction area
(200 × 10-6 F/m2 = 2 × 10-4 pF/µm2)
CJSW = zero-bias junction capacitance per junction periphery
(400 × 10-12 F/m = 4 × 10-10 pF/µm)
MJ = grading coefficient of junction bottom (0.5)
MJSW = grading coefficient of junction side-wall (0.3)
VJ = the junction potential (Vsb, V
db for n-channel, V
bs, V
bd for p-channel)
PB = the built-in voltage (+0.7 V)
Area = AS or AD, the area of source or drain (15 × 10-12 m2 = 15 µm2)
Periphery = PS or PD, the periphery of source or drain
(11.5 × 10-6 m = 11.5 µm) Kenneth R. Laker, University of Pennsylvania
40